Real-Time Clock (DS 1215)
Next, the 64-bit signature must be sent to the timekeeper by executing
64 consecutive write cycles containing the proper data on data bit 0,
the least significant bit of the data bus. The proper data is illustrated
in Figure 10-2 and is listed here in hex values: C5, 3A, A3, 5C, C5,
3A, A3, 5C. All accesses prior to recognition of the 64-bit pattern are
directed to the RAM. After recognition is established, the next 64
read or write cycles either extract or update data in the real-time
clock. The associated RAM memory is not selected during this time.
A few comments about the pattern recognition cycles are needed here.
When the first write cycle is executed, it is compared to bit 1 of the
64-bit comparison register. If a match is found, the pointer increments
to the next location of the comparison register and awaits the next
write cycle. If a match is not found, the pointer does not advance and
all subsequent write cycles are ignored. If a read cycle to this address
occurs at any time during the pattern recognition, the present sequence
is aborted and the comparison register pointer is reset.
Pattern
recognition continues for a total of 64 write cycles to this address as
described above. Cycles to other locations outside the memory block
occupied by the associated RAM and timekeeper can be interleaved
with cycles to the timekeeper without interrupting the pattern
recognition sequence or data transfer sequence to the timekeeper.
10-4
