Counter/Timers (8254)
Operation Common to All Modes
Programming
When a Control Word is written to a counter, all Control Logic is
immediately reset and OUT goes to a known initial state. No CLK
pulses are required for this.
Gate
The GATE input is always sampled on the rising edge of CLK. In
Modes 0, 2, 3, and 4, the GATE input is level sensitive and the logic
level is sampled on the rising edge of CLK. In Modes 1, 2, 3, and 5,
the GATE input is rising-edge sensitive. In these modes, a rising edge
of GATE (trigger) sets an edge sensitive flip-flop in the counter. This
flip-flop is then sampled on the next rising edge of CLK. The flip-flop
is reset immediately after it is sampled. In this way, a trigger is
detected no matter when it occurs—a high logic level need not be
maintained until the next rising edge of CLK. Note that in Modes 2
and 3, the GATE input is edge and level sensitive. In Modes 2 and 3,
if a CLK source other than the system clock is used, GATE should be
pulsed immediately following WR* of a new count value.
11-23
