Theory of Operation
Polled Interrupts on the STD Bus
The PIC can be programmed to supply a unique vector for each of
these interrupt inputs. This means only one STD bus interrupt per
request can be uniquely defined as shown in Figure 3-2. Since STD
DOS expects the use of INTRQ1* and INTRQ2* for particular I/O
devices, this leaves only the INTRQ* signal for all remaining I/O
devices in the system. These devices may share this INTRQ* signal,
in which case the application program must poll each possible source
to determine which generated the interrupt. Such a procedure is fine
for most applications providing each interrupt source can be polled. A
software priority can be established by polling sources in a specific
order.
In general, sharing interrupts requires the use of level-triggered
interrupt sources. In this way, if one interrupt exists and another
arrives, the level remains active even when the first request has been
removed. The level will continue to activate the request at the
interrupt controller. Conversely, if edge-triggered interrupts are used,
activation of the interrupt request by one device essentially masks the
edge created by the second device, and the interrupt is not seen by the
interrupt controller even though the active logic level remains.
The 8259A PIC is programmable for either all level-triggered or all
edge-triggered interrupts. Use of counter/timer 0 for the system clock
tick requires that the PIC be programmed for edge-triggered
interrupts, as is standard for DOS systems. Sharing of INTRQ*
among two or more devices is still possible by monitoring the level of
INTRQ* at the printer port bit ERROR, bit 3 at I/O address 0379h. If
this bit remains a logical 1 after the first interrupt source has been
reset, an interrupt must remain active in the system and the polling
sequence should be restarted.
3-10
