Counter/Timers (8254)
BLOCK DIAGRAM
Figure 11-1 illustrates the block diagram of the 8254. The data bus
buffer is a three-state, bidirectional, 8-bit buffer that interfaces to the
internal data bus on the ZT 8809A. The Read/Write Logic and the
Control Word register generate control signals for the counter/timers,
and address lines A0 and A1 control access to the three counter/timers
and the Control Word register.
As shown in the I/O map on page 5-16, the 8254 is addressed at
0040h through 0047h. Only four I/O addresses are actually needed by
the 8254, and these are redundantly mapped on the ZT 8809A in the
ranges 0040h - 0043h and 0044h - 0047h.
DATA
BUS
BUFFER
READ/
WRITE
LOGIC
CONTROL
WORD
REGISTER
COUNTER
0
INTERNAL BUS
D - D
7
0
RD
WR
A 0
A 1
CS
COUNTER
1
COUNTER
2
8
CLK 0
GATE 0
OUT 0
CLK 1
GATE 1
OUT 1
CLK 2
GATE 2
OUT 2
Figure 11–1. Intel 8254 Timers Block Diagram.
11-3
