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Specifications

Table B-8
J4 Pin Assignments.

Signal

Pin Number

Description

FP1

2

Frontplane Interrupt Level 1

FP3

4

Frontplane Interrupt Level 3

FP5

6

Frontplane Interrupt Level 5

FP6

8

Frontplane Interrupt Level 6

FP7

10

Frontplane Interrupt Level 7

Table B-9
J5 Pin Assignments.

Signal

Pin Number

Description

AC0

1

One Side of AC Input Voltage

AC1

2

Other Side of AC Input Voltage

B-17

Summary of Contents for ZT 8809A

Page 1: ...809A V20 Single Board Computers OPERATING MANUAL FOR ZT 8808A 8809A REVISION A ZT 88CT08A 88CT09A REVISION A May 1 1993 1050 Southwood Drive San Luis Obispo CA 93401 USA FAX 805 541 5088 Telephone 805...

Page 2: ...on RMA number before returning any product to Ziatech for repair Life Support Policy Ziatech products are not authorized for use as critical components in life support devices or systems without the e...

Page 3: ...ice at one of the following numbers Corporate Headquarters 805 541 0488 805 541 5088 FAX You can also use a modem to leave a message on the 24 hour Ziatech Bulletin Board Service BBS by calling 805 54...

Page 4: ...to the ZT 8808A and ZT 88CT08A 88CT09A The following organizational outline describes the focus of each chapter Section headings enclosed in boxes indicate the locations of labeled tabs provided for...

Page 5: ...asic components of the V20 microprocessor its enhancements over 8088 architecture its ability to operate in both native mode and 8080 emulation mode its operation with DMA and the wait state generator...

Page 6: ...09A CMOS Boards describes the functional electrical and environmental characteristics of the CMOS versions of the ZT 8808A and ZT 8809A that differ from the non CMOS versions Appendix A Jumper Configu...

Page 7: ...ct Memory Access DMA 1 7 Optional Battery Backup 1 7 AC DC Power Fail Detection 1 8 Real Time Clock 1 9 Serial Communications 1 9 Counter Timers 1 10 Interrupts 1 11 Centronics Printer General Purpose...

Page 8: ...BUS COMPATIBILITY 3 4 MEMORY AND I O 3 4 SERIAL COMMUNICATIONS 3 4 Serial Port 1 COM1 3 5 Serial Port 2 COM2 3 6 INTERRUPTS 3 8 Interrupt Request Assignments 3 8 Polled Interrupts on the STD Bus 3 10...

Page 9: ...29 Software Outline 4 31 Flowcharts For AC Power Fail Watchdog Interrupts 4 34 EXAMPLE 3 REAL TIME CLOCK DRIVERS 4 40 Objectives 4 40 System Configuration 4 40 Software Outline 4 40 Chapter 5 MEMORY...

Page 10: ...ve Routine CALLN 6 15 Return from Interrupt RETI 6 15 Register Use in Emulation Mode 6 16 DMA SUPPORT 6 18 RESET STATE 6 20 WAIT STATE GENERATOR 6 21 Chapter 7 NUMERIC DATA PROCESSOR 8087 7 1 OVERVIEW...

Page 11: ...12 OPTIONAL PRINTER CABLE PINOUT 9 14 PRINTER PORT RESET STATE 9 15 Chapter 10 REAL TIME CLOCK DS 1215 10 1 OVERVIEW 10 1 OPERATION 10 3 TIMECHIP COMPARISON REGISTER DEFINITION 10 5 TIMEKEEPER REGISTE...

Page 12: ...ntrol Words OCW1 3 12 16 8259A I O PORT ADDRESSES 12 21 INTERRUPT ASSIGNMENTS ON THE ZT 8809A 12 22 OPERATION OF THE INTERRUPT CONTROLLER 12 24 Priorities 12 24 Interrupt Triggering 12 27 Interrupt St...

Page 13: ...aracteristics B 3 STD Bus Loading Characteristics B 3 MECHANICAL B 6 CONNECTORS B 9 CABLES B 20 TIMING B 23 Appendix C CUSTOMER SUPPORT C 1 OVERVIEW C 1 TROUBLESHOOTING C 2 Powering Up STD ROM C 2 Pow...

Page 14: ...6C452 Printer Port Output Characteristics 9 3 Table 9 2 Parallel Port Register Definitions 9 5 Table 9 3 Parallel Port Register Addresses 9 5 Table 9 4 Shared Printer Signals 9 13 Table 9 5 ZT 90039 C...

Page 15: ...Tables Table B 9 J5 Pin Assignments B 17 Table B 10 J6 Pin Assignments B 18 Table B 11 J7 Pin Assignments B 19...

Page 16: ...figuration 5 5 Figure 5 3 STD DOS Map with 640K On Board RAM 5 6 Figure 5 4 STD DOS With 640K RAM Jumper Configuration 5 7 Figure 5 5 Non DOS Factory Default Memory Map 5 8 Figure 5 6 Non DOS Factory...

Page 17: ...ure A 9 W33 W36 W38 W46 W68 Jumper Blocks A 26 Figure A 10 Socket 3D1 Configuration A 31 Figure A 11 W37 W47 50 W66 W67 Jumper Blocks A 34 Figure A 12 W51 W59 Jumper Block A 37 Figure A 13 W60 W65 Jum...

Page 18: ...ions 1 9 Counter Timers 1 10 Interrupts 1 11 Centronics Printer General Purpose I O Port 1 12 Optional Numeric Data Coprocessor 8087 1 12 Clock Slowdown Halt Restart CMOS boards only 1 13 OVERVIEW The...

Page 19: ...Kbyte RAM in socket 3D1 this configuration assumes no EPROM in socket 3D1 If you have been using an additional memory board ZT 8824 ZT 8820B ZT 8825 or other to achieve 640 Kbytes of system RAM you ma...

Page 20: ...erature and low power applications All references in this manual to the ZT 8808A and ZT 8809A are also appropriate for the ZT 88CT08A and ZT 88CT09A Refer to Chapter 13 for information pertaining spec...

Page 21: ...plane connectors Optional Numeric Data Processor 8087 via zSBC 337 Wait state generator Interrupt Controller 8259A 2 Two RS 232 C serial channels VL 16C452 one RS 422 485 selectable Three Counter Time...

Page 22: ...Serial Centronics Printer I O 32K RAM Optional Battery Backup Clock Slowdown and Halt Restart AC DC Power Fail Real time Clock V20 CPU 256K RAM 256K ROM or 384K RAM 128K ROM RAM Optionally Battery ba...

Page 23: ...e shift and rotate by immediate value move string stack manipulations and 8080 emulation mode The 8080 emulation mode enables existing 8 bit 8080 software to run on new 16 bit hardware with few or no...

Page 24: ...via BUSRQ pin 42 and the ZT 8809A responds with BUSAK once the microprocessor has signaled its release of the bus When the DMA transfer is complete the DMA device releases BUSRQ and the ZT 8809A then...

Page 25: ...ode as described above AC power fail detection is also available for early warning of impending low DC voltage to give the processor time to store critical data while DC voltage is still above 4 75 V...

Page 26: ...es in the timekeeper function Serial Communications The ZT 8809A contains two asynchronous RS 232 C communications channels one of which is selectable for RS 422 485 Both use the same type of UART chi...

Page 27: ...external frequency or event input The six programmable counter timer modes are as follows 1 Interrupt on end of count 2 Frequency divider 3 Square wave generator 4 Software triggered strobe 5 Retrigg...

Page 28: ...ure follows Revision 2 3 and later of the STD 80 Series Bus Specification which allows for the RESERVED and CNTRL STD bus pins 37 and 50 respectively to be interrupt sources as well as INTRQ pin 44 Th...

Page 29: ...or this interrupt is within the printer interface chip the VL 16C452 This chip also contains the two 16C450 equivalent serial ports All lines have corresponding register bits within the 16C452 Optiona...

Page 30: ...programmatic control of the slowdown feature If the printer requires this bit for proper control most do not a jumper selection is also provided to allow hardware selection of this feature Interrupt r...

Page 31: ...7 Configuring the ZT 8809A for STD ROM 2 9 STD ROM Memory Requirements 2 9 STD ROM Cable Requirements 2 10 STD ROM Jumper Configuration 2 10 Powering Up STD ROM 2 11 Configuring the ZT 8809A for STD D...

Page 32: ...ferences to the ZT 8809A also pertain to the ZT 8808A ZT 88CT08A and ZT 88CT09A UNPACKING Please check the shipping carton for damage If the shipping carton and contents are damaged notify the carrier...

Page 33: ...mputer or ZT 88CT08A or ZT 88CT09A Single Board 80C88 Computer ZT 8808A 8809A Operating Manual in binder Anti static packing material Attach the sticker packaged with the manual to the spine of the bi...

Page 34: ...t is used Refer to the board outline in Appendix B for board dimensions with and without the zSBC 337 module attached Power Requirements Power requirements for the ZT 8808A and ZT 8809A are 5 VDC at 1...

Page 35: ...heir turn on times are generally slower than linear power supplies If the above recommendations are not observed the 82C84A B may cause erratic behavior or the system may fail to operate upon power up...

Page 36: ...e It is critical to the ZT 8809A RS 232 C serial interface that Auxiliary Ground AUXGND on the STD bus be connected at the backplane to the 5 V ground reference GND Ziatech backplanes are shipped in t...

Page 37: ...ROM system is used primarily for applications written in assembly language and ROM able high level languages STD DOS for the ZT 8809A is intended for designers who wish to develop an application usin...

Page 38: ...50 W66 W47 W49 W48 W37 W33 W34 W36 W35 W38 W40 W39 W43 W46 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W44 W45 LPT INTERRUPTS TIMER COUNTER COM2 COM1 W67 W68 W1 A B...

Page 39: ...our ZT 8809A STD ROM Memory Requirements The STD ROM debug monitor is shipped in a 64 Kbyte EPROM Install this EPROM into the 32 pin socket at location 5D1 right justified with the board oriented comp...

Page 40: ...able is ZT 90026 STD ROM Jumper Configuration The following jumper configuration should be used for STD ROM Refer to Figure 2 1 on page 2 8 for a visual representation of this jumper configuration INS...

Page 41: ...tall the ZT 8809A into the STD bus card cage Be sure to attach the D type connector end of the cable to the appropriate IBM PC or compatible Follow these steps to power on the system with a PC or comp...

Page 42: ...nd RAM chips are installed in the proper sockets EPROM should be installed in socket 5D1 RAM should be installed in socket 7D1 4 Check pin 1 orientation of the installed EPROM and RAM s Pin 1 should b...

Page 43: ...Ziatech configures the ZT 8809A properly prior to shipment and tests it as a system If the ZT 8809A and STD DOS are ordered separately or the ZT 8809A was altered in any way after shipment instruction...

Page 44: ...W47 W49 W48 W37 W33 W34 W36 W35 W38 W40 W39 W43 W46 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W44 W45 LPT INTERRUPTS TIMER COUNTER COM2 COM1 W67 W68 W1 A B B A B...

Page 45: ...ped with 256 Kbytes The two 128 Kbyte static RAMs occupy socket locations 7D1 and 9D1 occupying the memory address range from 0 through 3FFFFh Again be sure to orient pin 1 consistently with the EPROM...

Page 46: ...pment Figure 2 2 on page 2 14 illustrates this jumper configuration INSTALL W2 3 4A 5B 6A 7B 9B 10B 11A 12 13A 14 15B 17B 18B 19 20 21B 22 23 28 29 34 35A 36A 37 38B 39 44A top post to left post of 40...

Page 47: ...serial cable from the proper connector on the ZT 8809A to COM1 on the IBM or compatible PC 2 Install the Host Development Software diskette into drive A of your IBM or compatible PC 3 Type A VSC and...

Page 48: ...re shipped configured for an analog color monitor Refer to the ZT 8980 Hardware Operating Manual for jumpering information c Be sure the video board is installed into the card cage along with the ZT 8...

Page 49: ...also be config ured for static RAM All RAM may be battery backed Memory access times required are 380 ns for a ZT 8808A and 210 ns for a ZT 8809A If DMA to or from on board memory is used chip access...

Page 50: ...256 Kbyte ROM Drive w 256 Kbyte EPROM 128 Kbyte ROM Drive w 128 Kbyte EPROM On Board RAM w 128 Kbyte RAMs Note Shaded portion represents off board memory address space C0000h 32 Kbyte RAM Drive and T...

Page 51: ...40000h 3FFFFh 0h 32 Kbyte RAM Drive and Timekeeper 128 Kbytes w 64 Kbyte EPROM On board RAM w 128 Kbyte RAMs Note Shaded portion represents off board memory address space E0000h DFFFFh Figure 2 4 STD...

Page 52: ...g for 64 Kbytes of I O addresses Eight bit I O boards are also compatible with the ZT 8809A provided the equivalent 8 bit addresses occupied by the on board devices are avoided For example the interru...

Page 53: ...000h Serial Port 1 COM 1 Printer Port 1 LPT 1 8259A Interrupt Controller Note Shaded portion represents off board I O address space Serial Port 2 COM 2 8254 Timers 0378h 0377h 0300h 02F7h 0048h 0047h...

Page 54: ...DOS system memory is now available This made it necessary to move the ZT 8844 video and ZT 8980 network BIOS extensions from address range 9C000h through 93FFFh to address range C0000h through C3FFFh...

Page 55: ...A or ZT 8844 Rev B or later should be ordered with ZT 8809A DOS systems If you are upgrading an existing system contact Ziatech for upgrade charges and for a Return Material Authorization RMA number...

Page 56: ...ignments 3 8 Polled Interrupts on the STD Bus 3 10 STD Bus Vectored Interrupts 3 12 STD Bus Cascaded Interrupts 3 13 Non Maskable Interrupts 3 14 DIRECT MEMORY ACCESS DMA 3 15 Advantages of DMA 3 15 D...

Page 57: ...compatibility Serial communications using RS 232 C or RS 422 485 Expanding the ZT 8809A interrupt structure Direct Memory Access DMA support and benefits Methods of battery backup with DC and AC powe...

Page 58: ...ZT 8809A processor performance relative to that of the IBM PC The test compared several processing tasks the test results are presented in Table 3 1 Table 3 1 Processor Speed Comparison Average Test S...

Page 59: ...ZT 8844 Enhanced Graphics Adapter EGA card See the discussion of the interrupt system later in this chapter for details on these interrupts The ZT 8809A also complies with the STD 32 Bus Specification...

Page 60: ...M Development Systems to attach to an IBM PC or compatible COM1 port You can use optional cables ZT 90014 or ZT 90027 to connect this serial port from the J1 frontplane connector to another piece of R...

Page 61: ...also refer to Appendix A for the description of W13 and to Chapter 9 regarding shared signals at the printer port if requiring software control of the RS 485 driver enable The various serial communic...

Page 62: ...m data rate is limited to 56 Kbaud by the UART A terminated twisted pair should be used to protect the integrity of the RS 485 signals A typical twisted pair has a characteristic impedance in the rang...

Page 63: ...sibilities which are assigned via jumper selections W2 through W11 This figure indicates the factory default assignments with a dagger symbol Three of these interrupt assignments are critical for STD...

Page 64: ...2 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 8087 Interrupt INTRQ1 FP1 INTRQ FP3 COM2 Timer 1 COM1 Power Fail FP5 INTRQ2 FP6 LPT1 FP7 Interrupt Level Jumper Selections W5 W4 W6 W7 W8 W2 W9 W3 W10 W11 Figure 3 1...

Page 65: ...if one interrupt exists and another arrives the level remains active even when the first request has been removed The level will continue to activate the request at the interrupt controller Conversel...

Page 66: ...ation INTERRUPT SOURCE 1 ZT 8808A ZT 8809A INTRQ INTAK INTRQ INTAK INTRQ INTAK INTERRUPT SOURCE 2 INTERRUPT SOURCE N INTRQ INTAK STD BUS INTERRUPT STATUS PORT ISP ISP ISP Figure 3 2 Polled Interrupt S...

Page 67: ...In this configuration up to six STD bus interrupting devices can provide a unique vector for more efficient servicing than is possible by polling This number may be decreased if STD DOS is present on...

Page 68: ...P TO EIGHT INTER RUPTS INTRQ INTAK STD BUS Figure 3 4 Large Scale Vectored Structure Backplane interrupt INTRQ and any of the frontplane interrupts may be used to cascade interrupt controllers The int...

Page 69: ...be disabled by jumpers on board The three sources of interrupt are 1 STD bus NMIRQ 2 AC Power Fail 3 8087 Numeric Data Processor interrupt These sources are logically ORed together and routed to the...

Page 70: ...us improving system throughput Data transfer is normally supervised by the CPU In a memory to I O transfer the CPU must first fetch the memory read instruction from program memory read the data from m...

Page 71: ...asserting the bus acknowledge signal BUSAK Simultaneously the ZT 8809A turns the address buffers inward to allow access to on board memory by the DMA controller The controller is then free to transfer...

Page 72: ...Theory of Operation A0 A19 D0 D7 BUSRQ BUSAK RD WR MEMRQ MCSYNC STD BUS I O OR MEMORY WITH DMA ZT 8808A ZT 8809A Figure 3 5 DMA With STD Bus Controller 3 17...

Page 73: ...advantages of system integrity and battery backup System integrity is improved because the system is not allowed to operate if DC voltage is less than 4 75 V System Reset is held active both on power...

Page 74: ...ble from Ziatech as part number ZT 90071 One end of the converter plugs into the same AC source as the power supply to monitor AC to the STD system The other end of the converter must be attached to c...

Page 75: ...s the system STD DOS assumes the application will supply the appropriate non maskable or maskable interrupt service routine for power fail If more than one source of non maskable interrupt is in the s...

Page 76: ...ect the wall transformer maximum 30 VAC to the AC input of the ZT 8809A at connector J5 and the output of a variable AC power supply Variac 4 Turn on the Variac and adjust the output voltage to 95 VAC...

Page 77: ...uation may be used to assign the resistor values VSense R1 R2 x 2 15 V R1 where VSense battery voltage minimum allowed 4 8 V minus the diode drop 0 7 V of CR1 or CR2 Example R1 is a variable 10 k resi...

Page 78: ...ttery Battery life is calculated for both typical and worst case situations in the following equations assuming the STD bus system is powered for 8 hours a day These equations show how battery life de...

Page 79: ...c part assumed a Typical Data Retention Time Total Current Drain Clock RAM Buffer 128 Kbyte RAM 1 uA 1 uA 8 uA 1 uA 11 uA Battery Life 1 AHr x 1 Day x 1 24 8 Hr 11 uA 5896 Days 16 1 years Note Again t...

Page 80: ...to the 32 Kbyte static RAM on board provided jumper W17 is installed The write signal to this RAM is gated by the inversion of AFD If jumper W17 is not installed the RAM may be written to regardless o...

Page 81: ...ng PBRESET with the additional restriction that the gate must be able to sink 0 2 mA During a reset the CPU the two serial ports and the printer port are reset to initial states these states are detai...

Page 82: ...he ZT 88CT09A extend the operating temperature range to between 40 and 85 Celsius All on board logic is CMOS and utilizes an advanced speed TTL compatible CMOS logic family ACT to allow support of bot...

Page 83: ...d a logical 0 selects the slowed clock frequency and a logical 1 selects the normal frequency provided jumper W46B is installed Note SLIN is also used to map in the lower half of a 256K EPROM If W67 i...

Page 84: ...restart the processor clock is a part of the 82C85 clock chip supplied on the ZT 88CT08A and ZT 88CT09A boards only This chip monitors the status lines from the CPU When a processor halt status is see...

Page 85: ...G SLAVE INTERRUPTS 4 13 Objectives 4 13 System Configuration 4 14 Software Outline 4 14 Program Code 4 17 EXAMPLE 2 POWER FAIL WATCHDOG TIMER 4 28 Objectives 4 28 System Level Issues 4 28 System Requi...

Page 86: ...upt controller and the minimum steps required to handle one interrupt from the on board timer the second part shows the use of the ZT 8809A with an external interrupt controller on the ZT 8840 Quad UA...

Page 87: ...errupt service routine The example shown strobes the LED after a certain timeout interrupt provided by the timer 2 System Configuration The only assumption made by this example is that the ZT 8809A be...

Page 88: ...3 No slave interrupt controllers Send ICW4 SFNM Buffered Master Normal EOI 8088 Send OCW1 Unmask all interrupts for STD DOS use END Initialization of the Interrupt Vector BEGIN Initialize low memory w...

Page 89: ...set for Mode 2 as a Rate Generator Send low byte of count Send high byte of count END MAIN Program BEGIN Initialize the segment registers and stack Initialize the interrupt vector for the ISR Call IN...

Page 90: ...THER WITH A COUNTER TIMER INITIALIZATION OF THE 8259A AND THE INTERRUPT VECTOR IS SHOWN ALONG WITH INITIALIZATION OF THE COUNTER TIMER 2 THE FRAMEWORK OF AN INTERRUPT SERVICE ROUTINE IS ALSO IMPORTANT...

Page 91: ...SLAVES ICW4_8809A EQU 00011101B 8088 NORM EOI BUF MASTER OCW1_8809A EQU 00000000B ENABLE ALL INTERRUPTS FOR STD DOS USE ZT 8809A 8254 REGISTER EQUATES BY PORT ADDRESS CNTRL_WORD EQU 0043H TIMERS CONT...

Page 92: ...RG 0 TYPE_0 DD DIV BY ZERO NOT USED TYPE_1 DD SINGLE STEP TYPE_2 DD NON MASKABLE INT TYPE_3 DD BREAKPOINT NOT USED TYPE_4 DD OVERFLOW INTERRUPT POINTER TABLE IS LOCATED JUST ABOVE THE FIRST EIGHT INTE...

Page 93: ...EGMENT IS LOCATED IN RAM FOR AN ARBITRARY STACK SIZE STACK SEGMENT STACK DW 20 DUP UNINITIALIZED STACK STACK_TOP LABEL WORD OFFSET OF TOS STACK ENDS DATA SEGMENT DATA SEGMENT NO DATA IS USED IN THIS P...

Page 94: ...S READ AND EXTRACTED THEN INVERTED AND OR D BACK INTO THE BYTE READ THE BYTE IS THEN REWRITTEN TO THE PRINTER PORT INPUTS NONE OUTPUTS NONE CALLS NONE DESTROYS NONE PUSH AX SAVE REGISTERS USED PUSH DX...

Page 95: ...ICW MOV AL ICW3_8809A OUT DX AL WRITE 3RD ICW MOV AL ICW4_8809A WRITE 4TH ICW OUT DX AL OUTPUT 4TH ICW MOV AL OCW1_8809A WRITE OCW1 ASSUMES STD DOS USE OUT DX AL OUTPUT MASK RET INIT_PIC ENDP INIT_TMR...

Page 96: ...V DI OFFSET TYPE_10 MOV CX 1 1 VECTOR TO BE INITIALIZED VECT MOV WORD PTR DI OFFSET LED_STROBE ADD DI 2 MOV DI CS ADD DI 2 LOOP VECT POP DS INITIALIZE THE COUNTER TIMER 2 FOR THE RATE GENERATOR TO ALL...

Page 97: ...ervice routine for the slave interrupt used Write a software routine that initializes the serial port on the ZT 8840 Quad Serial port card for a simple serial output This routine can be used to initia...

Page 98: ...8809A No jumper changes required 2 ZT 8840 Remove jumpers W1 W3 to assign the board to I O address E0h Software Outline INIT_PIC_8809A Routine BEGIN Initialize the 8809A Interrupt Controller Send ICW1...

Page 99: ...Normal EOI 8088 Send OCW1 Unmask interrupt IR0 END INIT_VECT Routine BEGIN Initialize low memory with a pointer to the interrupt service routine ISR Write offset of ISR to lower word Write code segme...

Page 100: ...ment registers and stack Use the routine to initialize the vector s Call INIT_UART Call INIT_PIC_8809A Call INIT_PIC 8840 Enable the interrupt inside the UART for transmit buffer empty Enable processo...

Page 101: ...TINE IS ALSO IMPORTANT AND DEMONSTRATES THE USE OF THE END OF INTERRUPT EOI SYSTEM CONFIGURATION THE SYSTEM IS ASSUMED TO CONTAIN ONE ZT 8808A OR ZT 8809A WITH STD DOS SOFTWARE INSTALLED IN ADDITION A...

Page 102: ..._8840 EQU 0E7H PORT A ICW1_8840 EQU 00010001B EDGE CASCADE ICW4 NEEDED OCW2_8840 EQU 01100000B SPECIFIC EOI FOR IR0 REG B ICW2 3 4 OCW1 IMR PORT_B_8840 EQU 0EFH PORT B ICW2_8840 EQU 11111000B TYPES 24...

Page 103: ...8 EQU 03H 8 BIT WORD STB EQU 04H 2 STOP BITS PEN EQU 10H PARITY ENABLE EPS EQU 20H STICK PARITY SBK EQU 40H SET BREAK DLAB EQU 80H DIV LATCH ACCESS DIVISOR LATCH VALUES REG 3 DLAB 1 BD111 EQU 1047 110...

Page 104: ...RECV LINE DECT MACRO DEFINITIONS GET MACRO SRC MOV DX SRC GET I O PORT IN AL DX INPUT DATA ENDM PUT MACRO DST MOV DX DST GET I O PORT OUT DX AL OUTPUT DATA ENDM INTERRUPT POINTERS SEGMENT INTERRUPT PO...

Page 105: ...YPES ORG 248 4 TYPE_248 DD 8259A IR0 UART 1 TYPE_249 DD 8259A IR1 UART 2 TYPE_250 DD 8259A IR2 UART 3 TYPE_251 DD 8259A IR3 UART 4 TYPE_252 DD 8259A IR4 AVAIL TYPE_253 DD 8259A IR5 AVAIL TYPE_254 DD 8...

Page 106: ...8259A PIC ON THE ZT 8840 THE INT_FLAG LOCATION WILL RECORD THAT THE INTERRUPT WAS RECEIVED WITH A ZERO VALUE IT IS ASSUMED THE FLAG IS INITIALLY 0FFH INPUTS NONE OUTPUTS INT_FLAG 0H CALLS NONE DESTRO...

Page 107: ...TE 4TH ICW OUT DX AL OUTPUT 4TH ICW MOV AL OCW1_8809A WRITE OCW1 OUT DX AL OUTPUT MASK RET INIT_PIC_8809A ENDP INIT_PIC_8840 PROC THIS PROCEDURE IS CALLED TO INITIALIZE THE 8259A PIC ON THE ZT 8840 TH...

Page 108: ...EITHER ON OR OFF INPUTS NONE OUTPUTS NONE CALLS NONE DESTROYS NONE PUSH AX SAVE REGISTERS USED PUSH BX PUSH CX PUSH DX MOV BL 2 GO THRU TWICE DO_TWICE GET PRTR_CTRL READ THE CONTROL BYTE MOV AH AL SA...

Page 109: ...OF UART TO BE INIT OUTPUTS NONE CALLS NONE DESTROYS AX DX F FS MOV AL WL8 DLAB 8 BIT DLAB PUT UART1 PORT_LINEC OUTPUT LINE CONTROL MOV DX UART1 GET UART ADD DX PORT_DLALB MOV AX BD962 9600 BAUD OUT DX...

Page 110: ...BLE TO INDICATE NO INTERRUPT AT PRESENT MOV INT_FLAG 0FFH INITIALIZE THE SERIAL PORT 0 AND THE 8259A INTERRUPT CONTROLLER ON THE ZT 8840 QUAD UART BOARD CALL INIT_UART CALL INIT_PIC_8840 INITIALIZE ZT...

Page 111: ...TUS AND AL THRE CHECK IT FOR TXMIT BUF EMPTY JZ WAIT_RDY WAIT IF NOT EMPTY MOV AL 0AAH PLACE A BYTE IN THE OUTREG PUT UART1 PORT_XMT50 AGAIN XOR CX CX ZERO THE CX REG MAX COUNT WAIT_LP LOOP WAIT_LP WA...

Page 112: ...Chapter 3 Theory of Operation AC power fail protection makes use of the non maskable interrupt to indicate that AC power is failing and DC power will soon follow As shown in the following example the...

Page 113: ...ach to W46B if a ZT 8844 EGA video board is installed in the system be sure to disable AutoSwitch by removing W5 and SW5 since AutoSwitch takes over the NMI vector 2 If detecting system battery failur...

Page 114: ...e AC power being restored to a good level without DC power going below 4 75 V Therefore the system may not be reset every time To monitor when the non maskable interrupt goes away in this situation yo...

Page 115: ...T routine Else A cold start so call INIT routine Remaining code to initialize the software and hardware including 8259A PIC that resides here END RESET Routine BEGIN Initialize the NMI routine pointer...

Page 116: ...er the watchdog timer Return END NON MASKABLE INTERRUPT Service Routine BEGIN Trigger the Watchdog Timer Check for the cause of the NMI at the 8259A Interrupt Request register bit 5 If set to 1 A powe...

Page 117: ...to read the bit and check Power fail condition persists If set to 0 power fail has resulted in a brownout condition and the system did not need to stop Vcc remained above 4 75 V Call the RESET routin...

Page 118: ...N PROGRAM START SET ES BATTERY BACKED RAM DC00h IS STD DOS DEFAULT SYSTEM DATA SAVED FLAG SET YES NO MUST BE A WARM START CALL RESET ROUTINE MUST BE A COLD START CALL INIT ROUTINE NORMAL MAIN PROGRAM...

Page 119: ...tion Examples RESET ROUTINE START RETURN INITIALIZE THE NMI INTERRUPT POINTER RESTORE CRITICAL PROGRAM DATA RESTORE PROGRAM SEGMENT REGISTERS TRIGGER THE WATCHDOG TIMER CLEAR THE SYSTEM DATA SAVED FLA...

Page 120: ...I INTERRUPT POINTER INITIALIZE THE SEGMENT REGISTERS INITIALIZE THE SOFTWARE DATA TRIGGER THE WATCHDOG TIMER INITIALIZE THE INTERRUPT CONTROLLER MASKING THE POWER FAIL INTERRUPT LEVEL 5 INITIALIZE THE...

Page 121: ...SOURCES ELSE WHERE IN THE SYSTEM AND HANDLE THEM READ INTERRUPT RE QUEST REGISTER BIT 5 POWER FAIL NMI SO DO THE FOLLOWING SAVE REGISTERS IE SEGMENT AX BX CX DX SI DI BP SP IN BATTERY BACKED RAM SAVE...

Page 122: ...BATTERY SUPPLY VOLTAGE TO SYSTEM YES HALT PROCESSOR TO AWAIT MAIN BATTERY SUPPLY REPLACEMENT READ SLIN BIT AT PRINTER PORT CONTROL REGISTER ADDRESS 037Ah NO END SET SLIN BIT AT PRINTER PORT CONTROL RE...

Page 123: ...Examples CALL RESET ROUTINE NO END RETURN FROM INTERRUPT REINITIALIZE THE INTER RUPT CONTROLLER TO CLEAR IRR THE POWER FAIL CONDITION IS ENDED IT MUST HAVE BEEN A BROWNOUT SITUATION WITH NO HARDWARE...

Page 124: ...guration The ZT 8809A must be configured for the factory default jumper assignments for this example It is assumed that STD DOS is not installed since the clock is handled by STD DOS Software Outline...

Page 125: ...ce to reset the comparison register to be sure it is no longer accessible END MAIN Routine BEGIN Call INIT_CLK to be able to access the real time clock Call WRIT_CLK to write the initial time to the c...

Page 126: ...Y DEVICE LOCATIONS 5 11 Sockets 3D1 and 5D1 5 12 Sockets 7D1 and 9D1 5 13 DEVICE ACCESS TIMES 5 14 INPUT OUTPUT ADDRESSING 5 15 OVERVIEW This chapter describes the memory and I O capabilities of the Z...

Page 127: ...nsion MEMEX The Memory Expansion MEMEX signal is defined in the STD 80 Series Bus Specification for use with 16 bit memory cards The ZT 8809A can tie this signal to Vcc or ground via jumper W60 It doe...

Page 128: ...s code This is especially important for STD DOS systems where critical system configuration variables are stored in the on board 32 Kbyte RAM drive STD DOS controls the write protection of this RAM Fo...

Page 129: ...ed for a 128 Kbyte EPROM drive and the RAM sockets hold a total of 256 Kbytes to be used for system RAM Note that the 32 Kbyte RAM drive and timekeeper are shadowed behind the lower 128K address space...

Page 130: ...W47 W49 W48 W37 W33 W34 W36 W35 W38 W40 W39 W43 W46 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W44 W45 LPT INTERRUPTS TIMER COUNTER COM2 COM1 W67 W68 W1 A B B A B...

Page 131: ...m RAM FFFFFh D8000h A0000h 9FFFFh 0h 256 Kbyte ROM Drive w 256 Kbyte EPROM 640 Kbytes on board w a 128 Kbyte RAM in socket 3D1 and a 512 Kbyte RAM in socket 7D1 Note Shaded portion represents off boar...

Page 132: ...W47 W49 W48 W37 W33 W34 W36 W35 W38 W40 W39 W43 W46 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W44 W45 LPT INTERRUPTS TIMER COUNTER COM2 COM1 W67 W68 W1 A B B A B...

Page 133: ...PROM The other two sockets are configured for two 128 Kbyte RAMs for a total of 256 Kbytes of user RAM This memory configuration might be used for an STD ROM system FFFFFh D8000h D7FFFh 40000h 3FFFFh...

Page 134: ...W59 W50 W66 W47 W49 W48 W37 W33 W34 W36 W35 W38 W40 W39 W43 W46 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W44 W45 LPT INTERRUPTS TIMER COUNTER COM2 COM1 W67 W68 W...

Page 135: ...ttery backup with jumper W38 The choice of battery backup of a subset rather than all of RAM memory is designed to conserve battery power and therefore lengthen battery life Note for ZT 8809A STD DOS...

Page 136: ...ions of the RAM and EPROM sockets on the ZT 8809A Location 5D1 is the EPROM socket locations 7D1 and 9D1 are the RAM sockets and 3D1 is the RAM EPROM selectable socket 3D1 RAM EPROM SELECTABLE SOCKET...

Page 137: ...igurations 3D1 5D1 BRAM Socket 3D1 Socket 5D1 BRAM 1 Disabled Disabled F0000 F7FFF 32K 2 F0000 F7FFF 32K F8000 FFFFF 32K E8000 EFFFF 32K 3 E0000 EFFFF 64K F0000 FFFFF 64K D8000 DFFFF 32K 4 C0000 DFFFF...

Page 138: ...ns Table 5 2 Memory Configurations 7D1 9D1 Socket 7D1 Socket 9D1 1 00000 1FFFF 128K 20000 3FFFF 128K 2 00000 7FFFF 512K Disabled 3 Disabled Disabled Note Jumpers W67 and W68 affect the addressing of a...

Page 139: ...chip select access times allowed by the ZT 8808A and ZT 8809A for on board RAM and EPROM devices Each device should be selected with a chip select access time less than this maximum Table 5 3 Device A...

Page 140: ...ory address with the 32 Kbyte static RAM on board Refer to the description of the real time clock in Chapter 10 for further details on this shared memory address Figure 5 8 represents an I O map for b...

Page 141: ...iven by the ZT 8809A Factory default ties IOEXP to ground FFFFh 0400h 03FFh 03F8h 03F7h 0380h 037Fh 02FFh 02F8h 0040h 0000h Serial Port 1 COM 1 Printer Port 1 LPT 1 8259A Interrupt Controller Note Sha...

Page 142: ...Data Bus 6 9 Effective Address Generator 6 9 16 32 Bit Temporary Shift Registers TA TB 6 10 Loop Counter LC 6 10 Program Counter PC and Prefetch Pointer PFP 6 10 Enhanced and Unique Instructions 6 11...

Page 143: ...ypes Any 16 bit memory data fetch or write cycle is automatically performed as two 8 bit transfers where the least significant byte of the word is stored in the lower address location and the most sig...

Page 144: ...s shown no 8088 equivalent exists for this V20 register Segment Registers The V20 can directly address up to one megabyte of memory in segments of 64 Kbytes or less The starting address of a segment i...

Page 145: ...tack is always referenced by the stack segment register SS and the top of the stack is always referenced by the stack pointer register SP The stack always grows down in 8088 8086 memory organization S...

Page 146: ...the source data segment is pointed to by the IX SI register The segment register used to point to the destination string is the DS1 ES register Its offset into the destination data segment is pointed...

Page 147: ...ly accessible to the programmer General Purpose Registers There are four 16 bit general purpose registers each of which can be used as 8 bit registers by referencing their high or low byte names All o...

Page 148: ...base pointers are known as the BP and SP BP and SP These are primarily used to reference the stack The SP is generally used to point to the top of stack and the BP to variables within the stack This i...

Page 149: ...lags are generally tested by conditional jump and branch instructions to affect program execution The control flags are used by the programmer to direct CPU operation They are set to logical 1 or rese...

Page 150: ...XU in order to reduce the number of processing steps for instruction execution The two data buses are both 16 bits wide improving the addition subtraction and logical and comparison operations by appr...

Page 151: ...nt a number of times before completing These instructions are primitive block transfers controlled by a repeat prefix instruction and multiple bit shift or rotate Use of the loop counter improves proc...

Page 152: ...manipulation shift by immediate value move string instructions The unique instructions include packed BCD bit field manipulation repeat until carry flag clears or sets mode operations additional float...

Page 153: ...ilable The V20 processor powers up in native mode the normal mode of operation The mode flag in the PSW FL register bit 15 indicates operation in the native mode when set to 1 and emulation mode when...

Page 154: ...he methods used to transfer between them HOLD REQ HOLD ACK 8088 86 Enhanced and Unique Instruction Set 8080 Emulation Idle at 10 Power INT and ID RETEM CALLN HOLD REQ HOLD ACK Standby Mode HALT HLT RE...

Page 155: ...de It is prohibited to nest BRKEM instructions In other words the routine must finish with a return from emulation before another emulation call may be made using BRKEM If an interrupt occurs during t...

Page 156: ...PSW on the stack as 0 Then the MD bit is set to a logical 1 in the PSW FL and the contents of the PS and PC CS and IP are loaded with the new segment and offset address of the native mode subroutine R...

Page 157: ...the V20 The V20 registers must therefore consistently take the place of corresponding 8080 registers during emulation mode These register uses are defined in Table 6 2 Table 6 2 8080 Emulation Registe...

Page 158: ...n the other mode The SP IX IY and AH registers and the four segment registers PS SS DS0 and DS1 used in the native mode are not affected by operations in 8080 emulation mode In the 8080 emulation mode...

Page 159: ...pulses the Request Acknowledge RQ AK RQ GT signal to the V20 indicating that the V20 should relinquish the processor bus After completing its current instruction the V20 pulses RQ AK back to the ZT 88...

Page 160: ...strates the signals required for a transfer between an STD bus DMA controller and the ZT 8809A A0 A19 D0 D7 BUSRQ BUSAK RD WR MEMRQ MCSYNC STD BUS I O OR MEMORY WITH DMA ZT 8808A ZT 8809A Figure 6 3 D...

Page 161: ...hich is pin 48 on the STD bus Debouncing circuitry on board allows for any pushbutton switch or logic level to drive PBRESET low The driver of PBRESET must meet the following requirements open collect...

Page 162: ...nal which in turn causes the READY line to be driven low inactive Use of the external board s wait request which should occur only when that board is selected yields optimum system performance In this...

Page 163: ...oating point mathematics subsystem to reside on a single silicon substrate The 8087 Numeric Data Processor NDP is designed to function as a tightly coupled coprocessor in conjunction with the 8088 ser...

Page 164: ...by monitoring the same instruction stream and executing selected instructions from it For example while the V20 deals with memory segmentation calculating the addresses of operands in memory the 8087...

Page 165: ...g just below the piggyback board The piggyback board hovers partially above the configurable RAM EPROM memory socket which is not necessarily used for STD DOS and STD ROM The zSBC 337 therefore should...

Page 166: ...et provided by Ziatech is mounted to the socket pins behind the V20 chip on the zSBC 337 module 4 Apply the 40 pin dual inline socket on the base of the zSBC 337 to the vacated V20 socket on the ZT 88...

Page 167: ...nserted through the spacer Suggested part numbers include a Spacer 7 16 or 9 16 spacer x 187 outer diameter Bivar 9908 562 9 16 for use with hybrid RAM in socket 3D1 Bivar 9908 437 7 16 for all other...

Page 168: ...AM in socket 3D1 the memory socket under the zSBC 337 module an extra spacer socket may be required Ziatech recommends the 40 pin collet socket made by Augat part number 540 AG19D This configuration a...

Page 169: ...7 2 The 8087 waits for the grant pulse When received the 8087 initiates a bus transfer in the following clock cycle 3 The 8087 generates a release pulse to the CPU one clock cycle after the completion...

Page 170: ...ys reads the low order word of any 8087 memory operand The 8087 saves the address and data read To read any subsequent words of the operand the 8087 must become a local bus master by requesting the bu...

Page 171: ...invalid error is masked the NDP generates a special value called indefinite as the result of any invalid operation Any arithmetic operation with an indefinite operand always generates an indefinite re...

Page 172: ...ise due to invalid input values program error or hardware faults An immediate action is required since the integrity of the program and hardware is in question In this case the interrupt INT signal ca...

Page 173: ...g event Choose a high priority interrupt input to the PIC that terminates all numerics related activity This is a special case since the interrupt handler may never return to the point of interruption...

Page 174: ...numeric interrupts Connect the 8087 INT signal to multiple interrupt inputs One input would still be the lowest priority input as in case 4 Interrupt handlers that may generate a numeric interrupt re...

Page 175: ...onic Engineers Jan 1980 Palmer John Wymore Charles Making Mainframe Mathematics Accessible to MicroComputers Electronics 8 May 1982 or AR 135 from Intel Corporation Rash Bill Getting Started with the...

Page 176: ...t Outputs INT0 INT1 8 12 Ring Indicator Inputs RI0 RI1 8 13 Receive Line Signal Detect RLSD0 RLSD1 8 13 Reset Control RESET 8 14 Request To Send RTS0 RTS1 8 15 Serial Data Inputs SIN0 SIN1 8 15 Serial...

Page 177: ...DOS systems These two serial ports are contained within the VL 16C452 Communications Element from VLSI Technologies The first section of this chapter details an overview of the software communication...

Page 178: ...formally defining the ZT 8809A as DCE Both serial ports are jumper configurable for DTE or DCE refer to Appendix A for these jumper assignments The protocol shown in Figure 8 1 on page 8 5 could be u...

Page 179: ...e RTS line on the ZT 8809A is asserted by writing to the Modem Control register setting bit 1 When transmitting data the system software must be sure the transmitter output buffer is empty the previou...

Page 180: ...ent both devices from transmitting at the same instant The system designer must assign either the DCE or the DTE to transmit only after having received a message indicating it is okay to transmit Figu...

Page 181: ...errupts Details on the different aspects of interrupt usage are discussed later in the serial interrupt register sections of this chapter Functionally whenever an incoming data stream fills the receiv...

Page 182: ...A J1 B B B A A A Wire wrap to loop back RTS to CTS on COM2 Wire wrap to loop back DTR to DSR on COM2 Wire wrap to loop back RTS to CTS on COM1 Wire wrap to loop back DTR to DSR on COM1 Note dotted li...

Page 183: ...conversion on data characters received from a peripheral device or a modem and parallel to serial conversion on data characters received from the STD CPU The STD CPU can read the complete status of t...

Page 184: ...NERATOR LINE STATUS REGISTER TRANSMITTER TIMING CONTROL TRANSMITTER HOLDING REGISTER TRANSMITTER SHIFT REGISTER MODEM CONTROL REGISTER MODEM CONTROL LOGIC MODEM STATUS REGISTER INTERRUPT ENABLE REGIST...

Page 185: ...are on board Use jumpers W14 W19 W21 W22 and W29 W32 to select between the two types As shown in the table on page 3 7 RS 232 C is a single ended serial communications protocol that allows one driver...

Page 186: ...ous reading of the associated MSR in each serial port causes the setting of the DCTS bit in the respective MSR bit 0 When CTS is active low the modem is indicating that data on the associated serial o...

Page 187: ...errupt goes active high when one of the following interrupt sources has an active condition and is enabled by the Interrupt Enable register IER of its associated channel Receiver Error flag Received D...

Page 188: ...rrupt Enable register bit 3 being set to 1 and RI changes from high to low an interrupt is generated for that UART Receive Line Signal Detect RLSD0 RLSD1 When active low RLSD sometimes referred to as...

Page 189: ...strates the effect of reset on the serial ports Table 8 1 16C452 Reset State Register Signal Reset Control Reset Interrupt Enable Register Reset All bits low 0 3 forced and 4 7 permanent Interrupt Ide...

Page 190: ...ion of the line Serial Data Inputs SIN0 SIN1 The serial data inputs move information from the communication line or modem to the UART receiver circuits A mark 1 is high a space 0 is low Data on serial...

Page 191: ...OM1 and 02F8h for serial port 2 COM2 The offset of each register from the base is shown in Table 8 3 on pages 8 18 and 8 19 and in the I O Port Assignments table on page 8 17 Note that the state of th...

Page 192: ...trol Ch1 Line Control Ch1 4 3FCh Modem Cntrl Ch1 Modem Cntrl Ch1 5 3FDh Line Status Ch1 Line Status Ch1 6 3FEh Modem Status Ch1 7 3FFh 0 2F8h Data Buffer Ch2 Data Buffer Ch2 1 2F9h Intr Enable Ch2 Int...

Page 193: ...R IER IIR LCR 0 Data Bit 1 Data Bit 1 1 Enable Transmit Buffer Empty Interrupt RSI Interupt ID Bit 0 Word Length Select Bit 1 WLS1 2 Data Bit 2 Data Bit 2 Enable Receive Status Interrupt TBI Interrupt...

Page 194: ...D9 Request to Send RTS Delta Data Set Ready DDSR SCR1 2 D2 D10 OUT1 Not available externally Trailing Edge Ring Indicator TERI SCR2 3 D3 D11 OUT2 Interrupt output enable Delta Data Carrier Detect DDC...

Page 195: ...0 of a data word is always the first serial data bit received and transmitted The 16C452 data registers are double buffered so that read and write operations can be performed at the same time the UAR...

Page 196: ...ontrol register for inspection This feature simplifies system programming and eliminates the need for storing line characteristics in system memory Contents of the LCR are included in Table 8 3 on pag...

Page 197: ...it When bit 3 is a logical 1 a parity bit is generated transmit data or checked receive data between the last data word bit and stop bit of the serial data Bit 4 This is the Even Parity Select bit Whe...

Page 198: ...used no erroneous or extraneous characters are transmitted because of the break 1 Load an all 0s pad character in response to THRE 2 Set Break in response to the next THRE 3 Wait for the transmitter...

Page 199: ...loading either of the divisor latches a 16 bit baud counter immediately becomes effective Table 8 4 illustrates the use of the baud generator with the on board 1 8432 MHz oscillator The baud rate div...

Page 200: ...ate Table Baud Rates Using 1 8432 MHz Clock F Baud Rate Divisor Error B D 50 2304 75 1536 110 1047 0 026 134 5 857 0 058 150 768 300 384 600 192 1200 96 1800 64 2000 58 69 2400 48 3600 32 4800 24 7200...

Page 201: ...is the Overrun Error OE indicator It indicates that data in the Receiver Buffer register was not read by the CPU before the next character was transferred into the Receiver Buffer register thereby des...

Page 202: ...er for transmission In addition this bit causes the 16C452 to issue an interrupt to the CPU when the THRE Interrupt Enable is set high The THRE bit is set to logical 1 when a character is transferred...

Page 203: ...dentification Register Interrupt Set and Reset Functions Bit 2 Bit 1 Bit 0 Priority Level Interrupt Flag None Interrupt Reset Control 1 1 0 Highest Receiver Line Status Overrun Error or Parity Error o...

Page 204: ...8 and 8 19 and are described below Bit 0 This bit can be used in either a hardwired prioritized or a polled environment to indicate whether an interrupt is pending When bit 0 is a logical 0 an interru...

Page 205: ...ur Disabling the interrupt system inhibits the Interrupt Identification register IIR and the active high INTRPT output from the chip All other system functions operate in their normal manner including...

Page 206: ...cal 1 the RTS output is set active low When bit 1 is reset to logical 0 the RTS output is set inactive high Bit 2 This bit would normally control the Output 1 OUT1 signal which is an auxiliary user de...

Page 207: ...ature allows the processor to verify the transmit data and receive data paths of the 16C452 In the diagnostic mode the receiver and transmitter interrupts are fully operational The Modem Control Inter...

Page 208: ...the last time it was read by the CPU Bit 1 This bit is the Delta Data Set Ready DDSR indicator Bit 1 indicates that the DSR input to the chip has changed state since the last time it was read by the C...

Page 209: ...ctivated by any change of status Reading the MSR clears these indications but has no effect on the status bits The status bits reflect the state of the input pins regardless of the mask control signal...

Page 210: ...G OF PRINTER PORT SIGNALS 9 12 OPTIONAL PRINTER CABLE PINOUT 9 14 PRINTER PORT RESET STATE 9 15 OVERVIEW This chapter provides a descsription of the Centronics printer interface instructions for using...

Page 211: ...tus These signal groups are available at the Data Port Control Port and Status Port registers respectively The open collector lines have internal 2 5 k pullups to 5 V Figure 9 1 is a block diagram of...

Page 212: ...rent drive capabilities of the 16C452 printer port signals are tabulated below in Table 9 1 Table 9 1 16C452 Printer Port Output Characteristics OUTPUTS Signal IOL mA IOH mA PD0 7 12 0 2 0 INIT AFD ST...

Page 213: ...e keyboard The second method of printing is from within an application For details on this and the Print command refer to your STD DOS system manual and the IBM DOS Reference Manual If STD DOS is inst...

Page 214: ...pectively Tables 9 2 and 9 3 show register definitions and corresponding addresses Table 9 2 Parallel Port Register Definitions REGISTER REGISTER BITS Data Port PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 R W Sta...

Page 215: ...esistor on LPTOE to bring it low when it is not driven at connector J6 making it an output port The optional ZT 90039 cable for the printer ties LPTOE to ground so that it may remain configured as an...

Page 216: ...xception exists with the ERROR signal The ERROR signal is used by STD DOS to monitor the Interrupt Request INTRQ signal from the backplane If the INTRQ line is still active after one source of interru...

Page 217: ...O signals are inverted at the frontplane except INIT This means that for all Control Port signals except INIT and IRQ ENB writing a logical 1 to the register drives a logical 0 to the frontplane conn...

Page 218: ...terrupts are generated For STD DOS use the IRQ ENB bit is set to 0 since STD DOS does not use the printer port interrupt If using the printer port for general purpose I O keep IRQ ENB disabled unless...

Page 219: ...attery backed RAM drive This feature is controlled by STD DOS only and is useful for protecting the RAM drive from being overwritten by errant applications software The RAM drive usually contains impo...

Page 220: ...be controlled by jumpers W46A and B SLIN is also used to map in the lower 128K memory space of 256K EPROMs placed in socket 5D1 This means that systems requiring the use of SLIN as a printer port sign...

Page 221: ...dit the SYSTEM CFG file on the RAM drive which is a battery backed RAM disk designed to hold system configuration variables and batch files Refer to the STD DOS system manual for further information o...

Page 222: ...system a subset of these four signals may be soldered depending on the jumper selections made for W37 W39 W13 and W46 respectively To prepare for soldering first remove the shrink tubing at the ends...

Page 223: ...robe STB 1 1 Autofeed AFD 2 14 B Parallel Data 0 PD0 3 2 Error ERROR 4 15 B Parallel Data 1 PD1 5 3 Initialize INIT 6 16 B Parallel Data 2 PD2 7 4 Select In SLIN 8 17 B Parallel Data 3 PD3 9 5 Printer...

Page 224: ...ignal does not affect the printer port inside the VL 16C452 Following a power up or pushbutton reset the Data and Control Ports initially assume a random state The Status Port is an input port and alw...

Page 225: ...limits The device is a Dallas Semiconductor DS 1215 that may be battery backed with an optional battery mounted on the ZT 8809A This battery backs up the RAM on board and maintains the timekeeping ope...

Page 226: ...g to jumpers W57 59 the real time clock may be addressed there as well Factory default is D8000h The timekeeper remains in the back ground allowing free access to the RAM as long as Vcc remains above...

Page 227: ...S function 2 call DOS updates the software clock on intervals set by Timer 0 its System Tick See Chapter 11 for further details on the Timer 0 System Tick The following detailed description of the tim...

Page 228: ...d here When the first write cycle is executed it is compared to bit 1 of the 64 bit comparison register If a match is found the pointer increments to the next location of the comparison register and a...

Page 229: ...e 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 7 6 5 4 3 2 1 0 C5 3A 5C C5 3A A3 5C A3 1 1 0 0 0 1 0 1 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0...

Page 230: ...ups of eight bits Writing and reading individual bits within a register could produce erroneous results These read write registers are defined in Figure 10 3 Reading or writing these registers is alwa...

Page 231: ...5 4 3 2 1 0 0 1 SEC 0 01 SEC 10 SEC SECONDS 10 MIN MINUTES 0 0 7 7 7 12 24 0 10 A P HR HOUR DAY DATE MONTH YEAR 10 YEAR 0 0 0SC RST 0 10 DATE 0 0 0 0 0 10 MONTH 7 7 7 7 Range BCD 00 99 00 59 01 12 01...

Page 232: ...the reset bit should be set to 1 indicating that the reset function is ignored on the chip Reset s purpose is to abort data transfer without changing data in the timekeeper registers it is not used If...

Page 233: ...h Command 11 8 Read Back Command 11 11 Mode Definitions 11 16 Mode 0 Interrupt on Terminal Count 11 16 Mode 1 Hardware Retriggerable One Shot 11 17 Mode 2 Rate Generator 11 18 Mode 3 Square Wave Mode...

Page 234: ...ace of a software timing loop or for event tracking When used for a timing loop the programmer configures a timer for the proper time delay and some time later an interrupt from the timer signifies th...

Page 235: ...A1 control access to the three counter timers and the Control Word register As shown in the I O map on page 5 16 the 8254 is addressed at 0040h through 0047h Only four I O addresses are actually neede...

Page 236: ...igure 11 2 shows the internal block diagram of the counter timer Although the Control Word register is not a part of the counter timer itself its contents determine how the counter operates and it is...

Page 237: ...pectively When a new count is written to the counter it is first stored in the CR high and low bytes one byte at a time and later transferred to the CE as a 16 bit word The CRM and CRL are cleared whe...

Page 238: ...fies the counter being addressed the mode programmed whether or not reading or writing will next take place and whether or not BCD counting is desired Figure 11 3 illustrates the encoding of the Contr...

Page 239: ...Counter SC1 0 0 1 1 SC0 0 1 0 1 Select Counter 0 Select Counter 1 Select Counter 2 Read Back Command See Read Operations RW Read Write RW1 RW0 0 Counter Latch Command See Read t Operations Read Write...

Page 240: ...the counters 0 1 or 2 access them at I O port addresses 0040h 0041h or 0042h respectively Keep in mind that if the Control Word indicates a read of two bytes then two separate byte I O inputs must be...

Page 241: ...and Format The selected counter s output latch OL latches the count at the time the Counter Latch command is received This count is held in the latch until it is read by the CPU or until the counter i...

Page 242: ...d though not necessarily one right after the other Another feature of the 8254 is that reads and writes of the same counter may be interleaved for example if the counter is pro grammed for two byte co...

Page 243: ...bits D1 through D3 to 1 This single command is functionally equivalent to several Counter Latch commands one for each counter latched Each counter s latched count is held until it is read or until th...

Page 244: ...the current state of the OUT pin This allows you to monitor the counter s output via software possibly eliminating some hardware from a system D7 D6 D5 D4 D3 D2 D1 D0 Output Null Count RW1 RW0 M2 M1...

Page 245: ...he count value will not reflect the new count just written The operation of Null Count is shown in Figure 11 6 This Action Causes A Write to the Control Word register 1 Null Count 1 B Write to the Cou...

Page 246: ...This is functionally the same as issuing two separate Read Back commands at once and the above discussions also apply here Specifically if multiple count and or status Read Back commands are issued to...

Page 247: ...ack status of Status latched for counter 1 counter 1 1 1 1 0 1 1 0 0 Read back status of Status latched for counters 2 1 counter 2 but not counter 1 1 1 0 1 1 0 0 0 Read back count of Count latched fo...

Page 248: ...1988 pages 2 35 through 2 40 Mode 0 Interrupt on Terminal Count Mode 0 is typically used for event counting After the Control Word is written OUT is initially low and remains low until the counter re...

Page 249: ...riggerable One Shot OUT is initially high OUT goes low on the CLK pulse following a trigger to begin the one shot pulse and remains low until the counter reaches zero OUT then goes high and remains hi...

Page 250: ...gger reloads the counter with the initial count on the next CLK pulse OUT goes low N CLK pulses after the trigger Thus the GATE input can be used to synchronize the counter After writing a Control Wor...

Page 251: ...hronize the counter After writing a Control Word and initial count the counter is loaded on the next CLK pulse This allows the counter to be synchronized by software Writing a new count while counting...

Page 252: ...s initially high When the initial count expires OUT goes low for one CLK pulse and then goes high again The counting sequence is triggered by writing the initial count GATE 1 enables counting GATE 0 d...

Page 253: ...trigger This CLK pulse does not decrement the count So for an initial count of N OUT does not strobe low until N 1 CLK pulses after a trigger A trigger results in the counter being loaded with the ini...

Page 254: ...ables Counting Counting 1 1 Initiates Counting 2 Resets Output after Next Clock 2 1 Disables Counting Initiates Enables 2 Sets Output Counting Counting Immediately High 3 1 Disables Counting Initiates...

Page 255: ...3 and 5 the GATE input is rising edge sensitive In these modes a rising edge of GATE trigger sets an edge sensitive flip flop in the counter This flip flop is then sampled on the next rising edge of...

Page 256: ...ero In Modes 0 1 4 and 5 the counter wraps around to the highest count either FFFF hex for binary counting or 9999 for BCD counting and continues counting Modes 2 and 3 are periodic The counter reload...

Page 257: ...real time clock with this System Tick Counter 0 is dedicated for STD DOS use and should not be altered in any way by user programs The remaining counters 1 and 2 are free for application use and may b...

Page 258: ...ogic 12 9 Read Write Control Logic 12 10 Initialization and Operation Registers 12 10 Cascade Buffer Comparator 12 10 PROGRAMMABLE REGISTERS 12 11 Initialization Control Words ICW1 4 12 12 ICW1 12 12...

Page 259: ...ial Mask Mode 12 26 Poll Mode 12 27 Interrupt Triggering 12 27 Level Triggered Mode 12 28 Edge Triggered Mode 12 29 Interrupt Status 12 29 EOI COMMANDS 12 31 Nonspecific EOI Commands 12 31 Specific EO...

Page 260: ...upporting peripheral devices such as serial controllers and counter timers The major features of the PIC are as follows Eight individually maskable interrupts Extended operation for additional interru...

Page 261: ...tatus and pre interrupt program location which are used to return from the service routine The V20 then issues the first of two INTA pulses that signal the 8259A that the V20 has honored its interrupt...

Page 262: ...ter address Locations 0 through 3FFh should be reserved for the interrupt vector table alone Furthermore memory locations 00 through 7Fh types 0 31 are reserved for use by Intel Corporation for Intel...

Page 263: ...RET Interrupt Return instruction The IRET instruction pops the pre interrupt instruction pointer code segment and flags off the stack Thus the main program resumes where it was interrupted with the sa...

Page 264: ...Each of these functional blocks is described in the following sections DATA BUS BUFFER READ WRITE CON TROL LOGIC CONTROL WORD REGISTER INTERNAL BUS RD WR AO CS INTERRUPT REQUEST REGISTER IRR CONTROL L...

Page 265: ...the ZT 8809A Each interrupt source is available at a wirewrap pin and one of each pair of wirewrap pins is jumper selected to drive the interrupt at the PIC Refer to Appendix A to reassign these jump...

Page 266: ...t In Service register ISR maintains a bit position for each interrupt request that is currently being serviced More than one bit can be set if an interrupt is currently under service and a second inte...

Page 267: ...rupt priority rotation and the reading of certain PIC registers ICW1 through ICW4 are described more fully beginning on page 12 12 Description of the OCWs begins on page 12 16 Cascade Buffer Comparato...

Page 268: ...ected a specific sequence of read and write operations is needed to pass multiple bytes through two I O addresses The following subsections describe these registers and the methods used to access them...

Page 269: ...located at I O address 20h ICW1 consists of the following a Bits 0 and 4 are both logical 1s and identify the word as ICW1 for an 8088 CPU operation b Bit 1 denotes whether or not the PIC is employed...

Page 270: ...0 0 0 0 0 ID2 ID1 ID0 D7 D6 D5 D4 D3 D2 D1 D0 ICW3 Slave Device 1 SINGLE 0 NOT SINGLE 1 LEVEL TRIGGERED INPUT 0 EDGE TRIGGERED INPUT I O ADDRESS 20h 1 IR INPUT HAS A SLAVE 0 IR INPUT DOES NOT HAVE A...

Page 271: ...be defined as a multiple of 8 for the eight interrupts in the PIC Hence D0 D2 are always 0 for ICW2 The memory address of the vector table is obtained by multiplying the type by 4 For example to use...

Page 272: ...PIC on the ZT 8809A b Bit 1 programs the End Of Interrupt EOI function Code bit 1 logical 1 if an EOI is to be automatically executed hardware as the interrupt service routine is entered Code bit 1 lo...

Page 273: ...ICW1 and ICW2 b If slave PICs are used write ICW3 and ICW4 If no slave PICs are used omit ICW3 and write ICW4 only 3 Initialize each slave PIC by writing ICWs in the following sequence ICW1 ICW2 ICW3...

Page 274: ...I Command Rotate in Automatic EOI Mode Set Rotate in Automatic EOI Mode Clear Set Priority Command No operation Rotate on Specific EOI Command OCW2 D7 D6 D5 D4 D3 D2 D1 D0 ESMMSMM 0 1 P RR RIS 0 0 1 0...

Page 275: ...End Of Interrupt automatic rotation and specific rotation operations It is located at I O address 20h Associated commands and modes of these operations with the exception of AEOI initialization are se...

Page 276: ...L2 bits are disabled R The R bit is used to control all 8259A rotation operations If the R bit is set to 1 a form of priority rotation is executed depending on the state of the SL and EOI bits If R i...

Page 277: ...the poll command is not issued The poll command overrides a read register command if they are set simultaneously SMM The SMM bit is used to set the special mask mode If SMM is set to 1 the special mas...

Page 278: ...errupt level IL when the PIC is programmed for poll mode I O address 21h is used to write ICW2 ICW4 and to read IMR Slave PICs if employed are accessed via the STD bus and their I O addresses are dete...

Page 279: ...el you may wire wrap it to that source if a simple jumper selection is not available Be sure to pay attention to the active level of the source and whether STD DOS requires the use of that interrupt l...

Page 280: ...errupt Level A B A B A B A B A B A B A B A B W5 IRO W4 IR1 W6 IR2 W7 IR3 W8 IR4 W2 W9 IR5 W3 W10 IR6 W11 IR7 8087 Interrupt Timer 0 INTRQ1 FP1 INTRQ Timer 2 FP3 COM2 Timer 1 COM1 Power Fail FP5 FP6 IN...

Page 281: ...de Specific Rotating Mode Special Mask Mode Poll Mode Fully Nested Mode In this mode PIC input signals are assigned a priority from 0 through 7 Interrupt IR0 has the highest priority and IR7 has the l...

Page 282: ...ion time In this mode the master ignores interrupt requests of lower priority than the set ISR bit and responds to all requests of equal or higher priority Thus if a slave receives a request with high...

Page 283: ...ific Rotating Mode In this mode the software can change interrupt priority by specifying the lowest priority which automatically sets the highest priority For example if IR5 is assigned the lowest pri...

Page 284: ...C treats an I O Read Control as an interrupt acknowledge sets its In Service flip flop if there is a pending interrupt request and reads the priority level This mode is useful if there is a common ser...

Page 285: ...a safeguard You may accomplish this by using the IR7 routine as a clean up routine that might recheck the 8259A status or merely return program execution to its pre interrupt location Depending upon t...

Page 286: ...in the form of a negative pulse to the 8259A Another advantage is that it can be used with the automatic EOI mode without the cautions needed in the level triggered mode In most cases the edge trigge...

Page 287: ...en selected Thus all that is necessary to read the contents of the same register more than once is the RD pulse and the correct addressing A0 0 Upon initialization the selection of registers defaults...

Page 288: ...correct bit in the ISR To take advantage of the nonspecific EOI the 8259A must be in a mode of operation in which it can predetermine in service routine levels For this reason the nonspecific EOI comm...

Page 289: ...any other routines were in service at the same time a nonspecific EOI might reset the wrong ISR bit Thus the specific EOI command is the best choice in this case or for that matter at any time in whic...

Page 290: ...m of operation When To Use Automatic EOI Mode As with the other EOIs selection of the automatic EOI mode is dependent upon the application If interrupts are controlled at a predetermined rate thus pre...

Page 291: ...reset signal upon power up or when pushbutton reset is applied to the ZT 8809A The part powers up in an undefined state and may drive the interrupt request to the processor You MUST initialize the 82...

Page 292: ...RVIEW The ZT 8808A and ZT 8809A processor boards are also available in CMOS versions the ZT 88CT08A and ZT 88CT09A respectively The CMOS versions provide lower power and extended temperature operation...

Page 293: ...in the middle of the device name for example 74ACT573 and they are compatible with both CMOS and TTL logic input levels Both the C and the CT part types drive CMOS logic levels on the output The ZT 88...

Page 294: ...state its address and data buses to allow another bus master to drive the bus Since the CPU is fully buffered from the STD bus these buffers actually three state their outputs at DMA time and their i...

Page 295: ...part number is zSBC 337CT the 8087 2 is used with the ZT 88CT09A When ordering the zSBC 337CT module with the ZT 88CT08A or ZT 88CT09A refer to the part as OPT 337CT Remember that this extended temper...

Page 296: ...ware through a printer port output or in hardware through jumper W46 The printer port bit Select In SLIN controls the speed of the processor clock only if jumper W46B is installed SLIN is at address 0...

Page 297: ...feature We recommend that you not use this feature with STD DOS on the ZT 88CT08A and ZT 88CT09A Halt With Restart Via Interrupt To further decrease power consumption from the Clock Slowdown mode des...

Page 298: ...oller 8259A 2 Initialize the pointer to the Interrupt Service Routine 3 Be sure the event to restart the processor is initialized 4 Enable processor interrupts 5 Execute a processor halt instruction T...

Page 299: ...switching speed and load capacitance power is specified for the ZT 88CT08A and ZT 88CT09A uniquely Capacitive load is also identified for these power ratings If using a Ziatech supplied card cage and...

Page 300: ...ted power con sumption measures 115 mA with the same memory configuration and capacitive load This provides a power reduction of roughly 40 percent from the typical value Bus Loading Since power consu...

Page 301: ...ions on the board Figure A 14 on page A 54 is provided for documenting your custom jumper configuration See Figure 2 1 page 2 8 for the STD ROM jumper configuration and Figure A 16 page A 56 for the S...

Page 302: ...Jumper Configurations J4 J5 W1 W2 W3 W4 A B W5 A B W6 A B W7 A B W8 A B W9 A B W10 A B W11 A B W12 Figure A 1 W1 W12 Jumper Block A 2...

Page 303: ...of the ZT 90071 24 VAC Transformer plugged into connector J5 The ZT 8809A power fail circuitry is then able to detect AC power failure and generate a non maskable interrupt to the processor for early...

Page 304: ...jumper W9 Factory default installs this jumper W2 Function IN PNMI or FP5 may drive IR5 OUT Alternate source may drive IR5 W3 Jumper W3 ties the STD bus pin INTRQ2 previously CNTRL or frontplane inte...

Page 305: ...for STD DOS and STD ROM systems W4A W4B Function IN OUT INTRQ1 previously RESERVED STD bus signal drives IR1 OUT IN FP1 frontplane signal drives IR1 W5 A B Install W5A when using the 8087 plug in modu...

Page 306: ...to IR2 Factory default installs W6A W6A W6B Function IN OUT INTRQ STD bus signal drives IR2 OUT IN Timer 2 output drives IR2 W7 A B Install W7A to bring frontplane interrupt request 3 FP3 inverted on...

Page 307: ...ives IR4 OUT IN Serial port 1 COM1 drives IR4 W9 A B Select jumper W9A to bring the power fail non maskable interrupt request PNMI to interrupt request 5 IR5 on the interrupt controller provided jumpe...

Page 308: ...IR6 on the interrupt controller provided jumper W3 is also installed Select jumper W10B to bring the STD bus INTRQ2 pin 50 to IR6 assuming again jumper W3 is installed Refer to the descrip tions of j...

Page 309: ...bring frontplane interrupt request 7 FP7 to interrupt re quest 7 IR7 on the 8259A interrupt con troller Install jumper W11B to bring the printer interrupt request LPT1 to IR7 Factory default installs...

Page 310: ...hort the W12 pin nearest the extractor to STD bus ground pins 3 and 4 Factory default installs W12 Note If the battery is not installed ensure proper operation of timekeeper and 32K static RAM by inst...

Page 311: ...Configurations W17 W18 W19 W20 W21 W28 W27 W26 W25 W24 W23 W22 W29 W31 W32 A B A B W30 A B A B A B W13 W14 W15 W16 ZT 8809A REV A J6 J3 J2 J1 LPT TIMER COUNTER COM2 COM1 Figure A 2 W13 W32 Jumper Bloc...

Page 312: ...3B to enable the drivers unconditionally as for an RS 422 interface Install W13B to allow control of the enabling and disabling of these drivers through the INIT control line available on the printer...

Page 313: ...485 drivers to avoid interference by the RS 232 C drivers and receivers Factory default installs jumper W13A Refer to Chapter 9 for further details on the printer interface and Chapter 8 for further d...

Page 314: ...W14 to disable the receivers and remove it to enable the receivers Refer to the table on page A 17 if attempting to use the RS 422 485 receivers to avoid interference by RS 232 C drivers and receiver...

Page 315: ...mplete serial jumper assignments W15A W15B Function IN OUT RS 485 operation serial port 2 connector J2 OUT IN RS 232 operation serial port 2 connector J2 W16 Install W16 to provide ground for the RS 4...

Page 316: ...ce Remove both W17A and W17B to leave J2 pin 1 open Factory default installs W17B W17A W17B Function IN OUT RS 485 operation serial port 2 connector J2 OUT IN RS 232 operation serial port 2 connector...

Page 317: ...sure to read the description of W13 if using the RS 422 485 drivers and the de scription of W66 to enable COM2 Figures A 3 through A 6 illustrate jumper configurations for the COM2 options listed belo...

Page 318: ...W18 W19 W20 W21 W28 W27 W26 W25 W24 W23 W22 W29 W31 W32 W30 W13 W14 W15 W16 ZT 8809A REV A J6 J3 J2 J1 LPT TIMER COUNTER COM2 COM1 Figure A 3 COM2 Configured as RS 232 C DCE Jumpers W13 W19 W21 W22 W...

Page 319: ...W19 W20 W21 W28 W27 W26 W25 W24 W23 W22 W29 W31 W32 A B A B W30 W13 W14 W15 W16 ZT 8809A REV A J6 J3 J2 J1 LPT TIMER COUNTER COM2 COM1 Figure A 4 COM2 Configured as RS 232 C DTE Jumpers W13 W19 W21 W...

Page 320: ...W19 W20 W21 W28 W27 W26 W25 W24 W23 W22 W29 W31 W32 W30 W13 W14 W15 W16 ZT 8809A REV A J6 J3 J2 J1 B B B B B A LPT TIMER COUNTER COM2 COM1 Figure A 5 COM2 Configured as RS 422 DCE Jumpers W13 W19 W21...

Page 321: ...8809A REV A J6 J3 J2 J1 B B B B B A LPT TIMER COUNTER COM2 COM1 Note Select W13B and refer to Chapter 9 if controlling the RS 485 driver output enables dynamically in software via printer port signal...

Page 322: ...allow communication with COM1 on the IBM PC see Figure A 8 W23 W28 Function IN Serial port 1 as DCE see Figure 8 CROSSED Serial port 1 as DTE see Figure 7 W33 Install W33 to bring the 1 19318 MHz clo...

Page 323: ...nfigurations W17 W18 W19 W20 W21 W28 W27 W26 W25 W24 W23 W22 W29 W31 W32 W30 W13 W14 W15 W16 ZT 8809A REV A J6 J3 J2 J1 B B B B B A LPT TIMER COUNTER COM2 COM1 Figure A 7 COM1 Configured for DTE Opera...

Page 324: ...21 W28 W27 W26 W25 W24 W23 W22 W29 W31 W32 W30 W13 W14 W15 W16 ZT 8809A REV A J6 J3 J2 J1 B B B B B A LPT TIMER COUNTER COM2 COM1 Figure A 8 COM1 Configured for DCE Operation Default jumper configurat...

Page 325: ...W34 Function IN Timer 2 clock input is 1 19318 MHz OUT Timer 2 clock input is from J3 pin 8 W35 A B Select W35B to battery back the two RAM sock ets at locations 7D1 and 9D1 with the optional battery...

Page 326: ...Jumper Configurations W33 W46 A B A B W43 A B A B A B A B W39 A B W36 W35 W45 W34 W44 W40 W38 W42 W41 W68 A B Figure A 9 W33 W36 W38 W46 W68 Jumper Blocks A 26...

Page 327: ...eed AFD to control the LED and the write protect enable on the 32 Kbyte RAM at location 7D2 Remove it if using this printer port signal leaving the RAM write enabled and the LED off AFD is used by the...

Page 328: ...W38B to tie pin 16 of that socket directly to ground Factory default installs W38B Note Since the RAM in 3D1 is a possible loca tion for a RAM drive in a 640 Kbyte system jumper W38A allows independe...

Page 329: ...ce to be read as a status bit at the printer port signal ERROR This assumes that ERROR is not being used at the printer STD DOS uses ERROR for reading INTRQ so the ZT 90039 printer cable does not driv...

Page 330: ...ed for this socket is assigned according to jumper assignments W55 W59 Factory default assigns a 128 Kbyte EPROM for an STD DOS EPROM drive to socket 3D1 For STD ROM systems factory default assigns a...

Page 331: ...128K byte EPROM W44A W40 256 byte EPROM W40 128K byte RAM or 32K byte RAM W43 W44A W40 W42 NOTE Dotted lines represent wire wraps Only jumpers W40 W43 and W44 affect socket 3D1 Shaded areas should rem...

Page 332: ...ust also be selected for proper operation Socket 3D1 occupies the lower half if containing EPROM and socket 5D1 oc cupies the upper half of the on board EPROM address space The following table shows t...

Page 333: ...ng W46A disconnects the SLIN signal from the 82C85 SLO F input and instead brings the SLO F input low to select slow operation of the CPU This frees the SLIN bit for use by the printer Removing W46A a...

Page 334: ...Jumper Configurations W49 W48 A W47 B A B W37 W66 A W50 B C J7 W67 Figure A 11 W37 W47 50 W66 W67 Jumper Blocks A 34...

Page 335: ...w ledge line INTA to the 8259A to allow it to supply the vectors to the microprocessor if a slave is not the interrupting device Install W47A to allow an off board interrupt con troller to be the mast...

Page 336: ...input INT Install W50B to bring the STD bus interrupt request INTRQ inverted once directly to the CPU INT input This disconnects the on board 8259A INT Do this when using an off board master 8259A wit...

Page 337: ...Jumper Configurations W51 W52 W53 W54 W55 W56 W57 W58 W59 B A W50 W66 B A B A W48 W49 W47 J7 Figure A 12 W51 W59 Jumper Block A 37...

Page 338: ...he CPU non maskable interrupt input NMI Two other sources for NMI are power fail and STD bus non maskable interrupt request NMIRQ Note that power fail causes an NMI only if jumper W1 is installed Remo...

Page 339: ...onal AC transformer The DCPWRDWN is sent to allow other boards in the system to protect their static RAM at the same time as the processor Removing W53 prevents the ZT 8809A from driving the DCPWRDWN...

Page 340: ...ove W54 when installing the optional zSBC 337 module for use of an 8087 Nu meric Data Processor with the ZT 8809A Install W54 when this module is not to be used Factory default installs W54 W54 Functi...

Page 341: ...DOS W55 W59 W56 W57 W58 STD ROM W55 W57 W59 W58 Notes 1 W68A must be installed for 512K RAM devices Use the B position for 128K and smaller devices 2 W67 must be installed for 256K EPROMs installed in...

Page 342: ...FF 20000 3FFFF E8000 EFFFF In In In Out In E0000 EFFFF F0000 FFFFF 0 1FFFF 20000 3FFFF D8000 DFFFF In In In Out Out C0000 DFFFF E0000 FFFFF 0 1FFFF 20000 3FFFF B8000 BFFFF In In Out In In 80000 BFFFF...

Page 343: ...C0000 FFFFF 0 7FFFF In Out Out In Out 80000 9FFFF E0000 FFFFF 0 7FFFF D8000 DFFFF D8000 DFFFF Disabled 20000 3FFFF 0 1FFFF 0 7FFFF E0000 FFFFF 40000 5FFFF In Out Out Out In Disabled Disabled In Out O...

Page 344: ...ut Out In In Out E0000 EFFFF F0000 FFFFF Disabled D8000 DFFFF Out Out In Out In C0000 DFFFF E0000 FFFFF Disabled B8000 BFFFF Out Out In Out Out 80000 BFFFF C0000 FFFFF Disabled 78000 7FFFF Out Out Out...

Page 345: ...ll MEMEX up through a 2 2 k resistor to 5 V Factory default installs W60 W60 Function IN MEMEX tied to Logic Ground OUT MEMEX tied to Vcc W61 Install W61 to ground the STD bus signal IOEXP Remove W61...

Page 346: ...Jumper Configurations W61 W60 W62 W63 W64 A B A B W65 Figure A 13 W60 W65 Jumper Block A 46...

Page 347: ...rrupt controller IR6 via an inverter which requires the removal of W62 This allows for an extra interrupt request through the STD bus backplane Refer to the descriptions of jumpers W10 and W3 Factory...

Page 348: ...ust be attached for proper operation of the RS 232 C drivers and receivers Ziatech supplied card cage and power supply assemblies already connect AUXGND with GND in the backplane therefore installatio...

Page 349: ...ith the 8288 Memory Write control MWTC Install W64B to drive WR with the 8288 Advanced Memory Write control AMWC The AMWC signal starts one clock earlier with respect to MWTC in the four clock CPU cyc...

Page 350: ...s with the 8288 I O Write control IOWC Install W65A to drive WR with the 8288 Ad vanced I O Write control AIOWC The AIOWC signal starts one clock earlier with respect to IOWC in the four clock CPU cyc...

Page 351: ...e system at the COM2 I O port address This is useful for example when a separate serial card such as the ZT 8841 is to be used for COM2 Factory default installs W66 The location of W66 is shown in Fig...

Page 352: ...of a 256K EPROM placed in socket 5D1 Jumpers W55 and W56 must also be selected correctly for a 256K device Refer to the Memory Addressing table for jumpers W55 59 on pages A 42 to A 44 Factory defaul...

Page 353: ...cts Vcc to socket 7D1 pin 30 for 128K and smaller RAM devices The A position connects address line LA17 to socket 7D1 pin 30 for 512K RAM devices Factory default installs W68B The location of W68 is s...

Page 354: ...5 W56 W57 W58 W59 W50 W66 W47 W49 W48 W37 W33 W34 W36 W35 W38 W40 W39 W43 W46 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W44 W45 LPT INTERRUPTS TIMER COUNTER COM2...

Page 355: ...W50 W66 W47 W49 W48 W37 W33 W34 W36 W35 W38 W40 W39 W43 W46 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W44 W45 LPT INTERRUPTS TIMER COUNTER COM2 COM1 W67 W68 W1 A...

Page 356: ...W66 W47 W49 W48 W37 W33 W34 W36 W35 W38 W40 W39 W43 W46 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W44 W45 LPT INTERRUPTS TIMER COUNTER COM2 COM1 W67 W68 W1 A B B...

Page 357: ...Battery Backup Characteristics B 3 STD Bus Loading Characteristics B 3 MECHANICAL B 6 CONNECTORS B 9 CABLES B 20 TIMING B 23 OVERVIEW This appendix contains the electrical mechanical and environmenta...

Page 358: ...88CT09A Supply Voltage Vcc 0 to 7 V Supply Voltage AUX V 0 to 15 V Supply Voltage AUX V 0 to 15 V Operating Temperature 40 to 85 Celsius Storage Temperature 40 to 85 Celsius DC Operating Characterist...

Page 359: ...STD bus cards In the STD bus systems one unit load is equal to one LSTTL load as follows Maximum high level input current 20 A Maximum low level input current 400 A The STD bus unit load reflects inp...

Page 360: ...11 P13 P16 P18 P20 P22 P15 P17 P19 P21 P24 P26 P28 P30 P23 P25 P27 P29 P32 P34 P36 P38 P31 P33 P35 P37 P40 P42 P44 P46 P39 P41 P43 P45 P48 P50 P52 P47 P49 P51 P54 P56 P53 P55 PIN CIRCUIT SIDE OUTPUT D...

Page 361: ...E23 E26 E28 E30 E32 E25 E27 E29 E31 E34 E36 E38 E40 E33 E35 E37 E39 E42 E44 E46 E48 E41 E43 E45 E47 E49 E51 E53 E55 PIN CIRCUIT SIDE OUTPUT DRIVE INPUT LOAD MNEMONIC PIN COMPONENT SIDE OUTPUT DRIVE I...

Page 362: ...to the ZT 8809A in the card cage so as to not short the battery socket pins to an adjacent card In general this is not a problem in 5 8 inch spacing card cages the spacing used in Ziatech card cage po...

Page 363: ...0 50 in max Component Height Top w 128 Kbyte Hybrid RAMs 15 2 mm 0 60 in max Component Height Top w 8087 zSBC 337 20 8 mm 0 82 in max Component Height Bottom 3 175 mm 0 125 in max COMPONENT SIDE 6 50...

Page 364: ...ecifications 4 500 3 610 455 525 2 16 12 2 05 6 500 All dimensions in inches 40 230 C1 C2 V20 8087 CPU BOARD 210 690 Sockets for V20 zSBC 337 Spacer Socket Figure B 2 Board Dimensions With zSBC 337 B...

Page 365: ...Viking 3VH28 1CND5 or equivalent for a three level wire wrap The pin assignments are shown in Table B 1 on page B 4 E The E connector extends the P connector to interface the ZT 8809A to the STD 32 b...

Page 366: ...ector J5 is a two pin vertical header used to connect to an AC wall transformer or other AC source for power fail detection See page 3 19 for more information The pin assignments are shown in Table B...

Page 367: ...3 P14 E27 E28 P15 P16 E29 E30 P17 P18 E31 E32 P19 P20 E33 E34 P21 P22 E35 E36 P23 P24 E37 E38 P25 P26 E39 E40 P27 P28 E41 E42 P29 P30 E43 E44 P31 P32 E45 E46 P33 P34 E47 E48 P35 P36 E49 E50 P37 P38 E5...

Page 368: ...Specifications ZT8809A REV A W1 J4 J3 J2 J1 J5 J6 J7 Pin 1 Pin 1 P1 LPT INTERRUPTS TIMER COUNTER COM2 COM1 Figure B 4 ZT 8809A Connector Locations B 12...

Page 369: ...quest to Send CTS 9 7 Clear to Send DSR 11 14 Data Set Ready DTR 14 11 Data Terminal Ready RI 12 12 Ring Indicator DCD 10 10 Data Carrier Detect GND 1 13 1 13 Ground NC 2 4 6 8 2 4 6 8 No Connection S...

Page 370: ...quest to Send CTS 9 7 Clear to Send DSR 11 14 Data Set Ready DTR 14 11 Data Terminal Ready RI 12 12 Ring Indicator DCD 10 10 Data Carrier Detect GND 1 13 1 13 Ground NC 2 4 6 8 2 4 6 8 No Connection S...

Page 371: ...ta negative SDB 2 Send Data positive RDA 14 Receive Data negative RDB 13 Receive Data positive RSA 3 Request to Send negative RSB 4 Request to Send positive CSA 12 Clear to Send negative CSB 11 Clear...

Page 372: ...ription OUT0 1 Counter Timer 0 Output GAT0 2 Counter Timer 0 Gate CLK1 4 Counter Timer 1 Clock In GAT1 5 Counter Timer 1 Gate OUT1 6 Counter Timer 1 Output CLK2 8 Counter Timer 2 Clock In GAT2 9 Count...

Page 373: ...terrupt Level 1 FP3 4 Frontplane Interrupt Level 3 FP5 6 Frontplane Interrupt Level 5 FP6 8 Frontplane Interrupt Level 6 FP7 10 Frontplane Interrupt Level 7 Table B 9 J5 Pin Assignments Signal Pin Num...

Page 374: ...Data Bit 3 PD4 11 6 Parallel Data Bit 4 PD5 13 7 Parallel Data Bit 5 PD6 15 8 Parallel Data Bit 6 PD7 17 9 Parallel Data Bit 7 ACK 19 10 Acknowlege STB 1 1 Strobe AFD 2 14 Autofeed ERROR 4 15 Printer...

Page 375: ...Specifications Table B 11 J7 Pin Assignments Signal Pin Number Description NDPINT 1 Numeric Data Processor Interrupt NC 2 No Connect B 19...

Page 376: ...E 40 1 PIN 1 BLUE WIRE TB ANSLEY 622 25S FEMALE 25 PIN D CONNECTOR PIN 1 TB ANSLEY 622 1430 FEMALE 025 SQ 14 PIN CONNECTOR POLARIZED TRIM 15 25 AT CONNECTOR P1 J1 P1 J1 1 2 3 4 5 6 7 8 9 10 11 12 13 1...

Page 377: ...1 PIN 1 BLUE WIRE TB ANSLEY 622 25P MALE 25 PIN D CONNECTOR PIN 1 TB ANSLEY 622 1430 FEMALE 025 SQ 14 PIN CONNECTOR POLARIZED TRIM 15 25 AT CONNECTOR J1 P1 P1 J1 P1 J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14...

Page 378: ...train relief TB Ansley 171 20 20 conductor 28 guage stranded flat cable Pin 1 Pin 1 Stripe Pin Assignment Chart Wire No 25 Pin D Pin No 1 1 2 14 3 2 4 15 5 3 6 16 7 4 8 17 9 5 10 18 20 11 6 12 21 23 1...

Page 379: ...he CLOCK signal has rise and fall times of less than 10 ns as illustrated below tW1 tW2 tW3 8088 CLOCK 8088 CLOCK 8088 CLOCK period high width low width 200 118 69 125 69 44 125 69 200 118 69 44 8808A...

Page 380: ...Delay from CLOCK to MCSYNC high Delay from CLOCK to Address 0 15 MEMEX IOEXP Delay from CLOCK to STATUS Delay from CLOCK to IORQ Delay from CLOCK to MEMRQ STATUS hold after CLOCK IORQ hold after CLOC...

Page 381: ...id Delay from CLOCK to to Address 16 19 Delay from CLOCK to RD low Delay from CLOCK to RD high Delay from RD to Data valid Address 0 15 MEMEX IOEXP hold after CLOCK Address 16 19 hold after MCSYNC RD...

Page 382: ...m CLOCK to Data Valid Delay from CLOCK to Advanced WR low Delay from CLOCK to Advanced WR high Address 0 15 MEMEX IOEXP hold after CLOCK Address 16 19 hold after MCSYNC WR Data hold after CLOCK Data h...

Page 383: ...mes given in nanoseconds Delay from CLOCK to MCSYNC low Delay from CLOCK to MCSYNC high WAITRQ hold after CLOCK WAITRQ low setup to CLOCK WAITRQ high setup to CLOCK Address 0 19 setup to WAITRQ end of...

Page 384: ...onds Delay from CLOCK to BUSAK low Delay from CLOCK to BUSAK high Delay from BUSAK to Data Bus 3 State Delay from BUSAK to Data Bus driven Delay from BUSAK to Address Bus 3 State Delay from BUSAK to A...

Page 385: ...OCK to Address 16 19 Delay from CLOCK to INTAK low Delay from CLOCK to INTAK high Delay from CLOCK to Data Bus 3 State Delay from INTAK to Cascade from CPU Delay from INTAK to A0 A15 3 State Delay fro...

Page 386: ...12 17 91 C 8 Revision A 8 19 92 C 8 ZT 88CT08A 88CT09A REVISION HISTORY C 8 RELIABILITY C 9 WARRANTY C 10 TECHNICAL ASSISTANCE C 11 RETURNING FOR SERVICE C 12 OVERVIEW This appendix offers technical a...

Page 387: ...tached the D type connector end of the cable to the appropriate IBM PC or compatible or to a terminal Follow these steps to power on the system with a PC or compatible 1 Turn on the PC and wait for th...

Page 388: ...and RAM chips are installed in the proper sockets EPROM should be installed in socket 5D1 RAM should be installed in socket 7D1 4 Check pin 1 orientation of the installed EPROM and RAM s Pin 1 should...

Page 389: ...rial cable from the proper serial port connector on the ZT 8809A to COM1 on the IBM or compatible PC 2 Install the Host Development Software diskette into drive A of your IBM or compatible PC 3 Type A...

Page 390: ...chrome monitor If your monitor is not monochrome refer to the ZT 8844 Hardware Operating Manual for jumpering information b The ZT 8980 VGA video board is shipped configured for an analog color monito...

Page 391: ...OS If it lit but the RAM test did not start the most likely problem is the serial communications between the STD system and the host computer a Check that the serial cable is connected from the proper...

Page 392: ...contains the configuration variables c Check the placement of the STD DOS EPROM in socket 5D1 and the 256 Kbytes of RAM in sockets 7D1 and 9D1 3 If the system previously booted but no longer does cha...

Page 393: ...twork showed a revision level 0 The board contained wires to correct the item listed below No boards were shipped without this correction Improper layout of W68 A cuttable trace on the solder side of...

Page 394: ...unclean interactions between parts of the system are eliminated 2 The advanced low power Schottky TTL parts used in the ZT 8809A are high reliability parts available from several manufacturers The 74...

Page 395: ...the original manufacturer Notice Contact Ziatech for a Return Materials Authorization RMA number before returning any product to Ziatech for repair Life Support Policy Ziatech products are not author...

Page 396: ...e of the following numbers Corporate Headquarters 805 541 0488 805 541 5088 FAX You can also use your modem to leave a message on the 24 hour Ziatech Bulletin Board Service BBS by calling 805 541 8218...

Page 397: ...oduct I D number 4 If possible the name of technically qualified individual at your company familiar with the mode of failure on the board If the unit is out of warranty service is available at a pred...

Page 398: ...mple interrupts 4 3 architectural enhancements of the V20 6 9 automatic EOI mode 12 32 automatic rotating mode 12 26 automation engine 2 18 C 6 B base pointers 6 7 battery backup 1 3 1 7 2 15 3 23 5 1...

Page 399: ...d interrupts 3 13 Centronics printer interface 1 12 2 16 5 15 9 1 block diagram 9 2 control port interrupt capability 9 9 control port register 9 8 control port shared signals 9 10 data port register...

Page 400: ...ment VL 16C452 8 2 block diagram 8 9 compatibility with IBM PC 1 1 1 9 configuring the ZT 8809A A 1 for STD DOS 2 13 for STD ROM 2 9 connectors B 9 control flags 6 8 Control Logic 12 9 cooling systems...

Page 401: ...DDSR 8 33 delta received line signal detector DRLSD 8 33 device access times 5 14 diagnostic testing 16C452 8 32 direct memory access DMA 1 7 3 15 7 8 advantages 3 15 DMA support 6 18 operation 3 16...

Page 402: ...B 2 ZT 88CT08A 88CT09A 2 6 13 8 B 2 establishing serial communications 8 5 execution unit EXU 6 2 F features of the ZT 8809A 1 4 flags control flags 6 8 status flags 6 8 flowcharts for AC power fail w...

Page 403: ...n and operation registers 12 10 initialization control words ICW1 4 12 12 interrupt assignments 12 22 interrupt in service register ISR 12 9 interrupt mask register IMR 12 8 interrupt request register...

Page 404: ...addressing 2 22 map STD DOS STD ROM 2 23 port addresses and interrupts 8259A 12 21 port assignments 8 17 I O addressing 1 6 IOEXP 5 16 IORQ 5 15 J J1 B 9 J2 B 9 J3 B 9 jumper configurations non DOS fa...

Page 405: ...D ROM systems 2 21 5 8 MEMRQ 5 2 modem control register MCR 8 30 modem status interrupt 8 30 modem status register MSR 8 33 mode operations 8080 emulation mode 6 12 mounting the ZT 8809A 2 6 N NMIRQ 1...

Page 406: ...nested mode 12 25 special mask mode 12 26 specific rotating mode 12 26 output 1 OUT1 3 5 8 31 output 2 OUT2 3 5 8 31 overrun error OE indicator 8 26 P parity error PE indicator 8 26 PBRESET 3 26 6 20...

Page 407: ...31 program status word PSW FL 6 8 R rate generator 11 18 read back command counter timers 11 11 example 11 15 read operations for counter timers 11 8 read write control logic 12 10 READY 6 21 real ti...

Page 408: ...tion 8 10 S scratchpad register 8 20 segment registers 6 3 serial channel interrupt outputs INT 8 12 serial communications 1 9 2 4 2 6 2 16 3 4 3 26 A 50 EIA standards 3 6 protocol 8 3 serial data inp...

Page 409: ...OM 1 3 software triggered strobe 11 20 special fully nested mode 12 25 special mask mode 12 26 specifications absolute maximum ratings B 2 battery backup characteristics B 3 DC operating characteristi...

Page 410: ...STD ROM cable requirements 2 10 configuring the ZT 8809A 2 9 default memory map 2 21 5 8 development system 2 7 jumper configuration 2 10 5 9 A 55 memory requirements 2 9 powering up 2 11 use of count...

Page 411: ...register empty THRE indicator 8 27 interrupt 8 30 transmitter shift register empty TEMT indicator 8 27 troubleshooting STD DOS C 4 STD ROM C 2 Turbo Debugger 2 7 C 2 U UART 1 9 4 13 unpacking 2 2 V ve...

Page 412: ...8844 EGA card 2 7 2 18 3 4 3 8 4 29 C 5 BIOS extensions 2 24 ZT 90039 printer cable 2 16 9 14 drawing B 22 ZT 90014 serial cable 2 12 3 5 C 3 drawing B 20 ZT 90027 serial cable 3 5 drawing B 21 ZT 884...

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