Serial Communications (16C452)
Interrupt Enable Register
(2F9h, 3F9h; R/W)
The Interrupt Enable register (IER) enables the four interrupt sources
of the serial interface to separately activate the on-board interrupt
hardware. It is possible to totally disable the interrupt system by
resetting bits 0-3 of the IER. Similarly, by setting the appropriate bits
of this register to logical 1, selected interrupts can be enabled. Keep in
mind that the Modem Control register (MCR) bit 3, the interrupt
output enable bit, must be set for interrupts to occur.
Disabling the interrupt system inhibits the Interrupt Identification
register (IIR) and the active (high) INTRPT output from the chip. All
other system functions operate in their normal manner, including the
setting of the Line Status and Modem Status registers. Contents of the
IER are included in Table 8-3 on pages 8-18 and 8-19 and are
described below.
Bit 0
This bit enables the Received Data Available
Interrupt when set to logical 1.
Bit 1
This bit enables the Transmitter Holding Register
Empty Interrupt when set to logical 1.
Bit 2
This bit enables the Receiver Line Status Interrupt
when set to logical 1.
Bit 3
This bit enables the Modem Status Interrupt when set
to logical 1.
Bits 4 - 7
These four bits are always logical 0.
8-30
