Interrupt Controller (8259A)
OPERATION OVERVIEW
The basic functions of the PIC are to resolve the priority of interrupt
requests, issue a single interrupt request to the V20 based on that
priority, and send the V20 a vector address pointing to the interrupt
service routine for the proper device.
When an interrupt request is enabled in the PIC and interrupts are
enabled at the CPU, the occurrence of an interrupt prompts the CPU
to enter its interrupt acknowledge cycle. The flag register (FL) is
pushed onto the stack, as in a PUSHF instruction, and the IF flag is
cleared, disabling interrupts. The contents of both the code segment
(CS) and instruction pointer (IP) registers are then also pushed onto
the stack. Thus, the stack retains pre-interrupt flag status and pre-
interrupt program location, which are used to return from the service
routine. The V20 then issues the first of two INTA* pulses that signal
the 8259A that the V20 has honored its interrupt request.
The 8259A is now ready to vector program execution to the
corresponding service routine. This is done during the sequence of the
two INTA* pulses issued by the V20. Unlike operation with the
8080A or 8085A, the 8259A does not place a CALL instruction and
the starting address of the service routine on the data bus. Instead, the
first INTA* pulse is used only to signal the 8259A of the honored
request. The second INTA* pulse causes the 8259A to place a single
interrupt vector byte onto the data bus. Not used as a direct address,
this interrupt vector byte pertains to one of 256 interrupt "types"
supported by the V20 memory. Program execution is vectored to the
corresponding service routine by the contents of a specified interrupt
type.
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