Xilinx ChipScope Pro, User Manual

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18 www.xilinx.com ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 1: Introduction
IBERT Core
The IBERT core has all the logic to control, monitor, and change transceiver parameters and
perform bit error ratio tests. The IBERT core has three major components:
•
BERT Logic
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The BERT logic instantiates the actual transceiver component, and contains the
pattern generators and checkers. A variety of patterns are available, including
simple clock-type patterns, full PRBS (pseudo random bit sequence) patterns, and
framed counter patterns utilizing commas and comma detection.
•
Dynamic Reconfiguration Port (DRP) Logic
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Each transceiver has a Dynamic Reconfiguration Port (DRP) on it, so that
transceiver attributes can be changed in system. All attributes and DRP addresses
are readable and writable in the IBERT core. The DRP for each transceiver can be
accessed individually.
•
Control and status logic
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Manages the operation of the IBERT core.
IBERT Design Flow
Because the IBERT is a self-contained design, the design flow is very simple. When using
the ChipScope IBERT Core Generator to generate IBERT core designs for Virtex-5 devices,
the design directory and bit file name are specified, options are chosen, and the Generator
runs the entire implementation flow, including bitstream creation, in one step.
The design flow for generating IBERT core designs for Virtex-7, Kintex-7, Virtex-6, and
Spartan-6 devices are very similar except the Xilinx CORE Generator tool is used. The main
difference is that the design directory and device information is specified in the Xilinx
CORE Generator project. In both cases, you are not required to explicitly run any other
Xilinx tool to generate an IBERT core design bit file.
IBERT Feature Descriptions
The features of the IBERT core vary according to the targeted FPGA device architecture.
The MGT features that are supported are as follows:
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IBERT v2.0 for Virtex-5 FPGA GTX Transceivers ( Table 1-4, page 20 )
−
Full PMA control, including differential swing, emphasis, RX Equalization, and
DFE.
−
Ability to change line rate at runtime.
−
Limited PCS support, including loopback (8b/10b encoding, clock correction, and
channel bonding are not supported).
−
40-bit fabric data width (4-byte mode).
•
IBERT v2.0 core for Virtex-6 FPGA GTX transceivers ( Table 1-5, page 21 )
−
Full PMA control, including differential swing, emphasis, RX equalization, and
DFE.
−
Ability to change line rates at runtime.
−
Ability to set reference clock sources at generate time.
−
Limited PCS support, including loopback. Pattern encoding, clock correction and
channel bonding are not supported.