ChipScope Pro Software and Cores User Guide
219
UG029 (v14.3) October 16, 2012
ChipScope Pro Analyzer Core Troubleshooting
7.
Is the DONE pin of the FPGA device
being held low on the board?
If there are multiple FPGAs on the
board with the DONE pins tied
together, this error might occur in a
situation where DONE is held Low
by unconfigured devices and
configuration does not fully
complete.
If YES: To work around this issue, ensure that all FPGAs on the board are
configured or that the DriveDONE bitgen option is set for the target
device.
If NO: Go to Issue #8.
8.
Have the core constraints being
applied correctly?
If NO or NOT SURE: Check that a PERIOD constraint has been added to
the clock used as the Clock for your ILA. If there is no constraint on this net
in the ISE project, the ChipScope constraints are not applied correctly and
might result in the cores not being recognized. Also check that the NCF file
associated with the core was applied. If the core netlist file (*.ngc/ngo) was
moved during implementation the associated constraint file (*.ncf) might
not have been moved.
If YES: Open a case with Xilinx Technical Support including the
following information:
•
cs_analyzer.log
•
Archived ISE project including inserter project
(<project_name>.cdc)
Table A-8:
Troubleshooting Core Detection Issues
(Cont’d)
Issue(s)
Solution(s) or Work-Around(s)
