ChipScope Pro Software and Cores User Guide
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UG029 (v14.3) October 16, 2012
ChipScope Pro Analyzer Features
Plug-in dialog box (consult with the plug-in provider for details). After the plug-in
parameters are entered, click
OK
to open a connection to the JTAG plug-in.
Polling the Auto Core Status
When the cores are armed, the interface cable queries the cores on a regular basis to
determine the status of the capture. If other programs are using the cable at the same time
as the ChipScope Pro Analyzer tool, it can often be beneficial to turn this polling off. This
can be done in the
JTAG Chain
menu by un-checking
JTAG Chain >
Auto Core Status
Poll
. If this option is unchecked, when the Run or Trigger Immediate operation is
performed, the ChipScope Pro Analyzer tool does not query the cores automatically to
determine the status.
Note that this does not completely disable communication with the cable; it only disables
the periodic polling when cores are armed. If one or more cores trigger after the polling has
been turned off, the capture buffer is not downloaded from the device and displayed in
any of the data viewer(s) until the
Auto Core Status Poll
option is turned on again.
Configuring the Target Device(s)
You can use the ChipScope Pro Analyzer tool with one or more valid target devices. The
first step is to set up all the devices in the boundary scan chain.
Setting Up the Boundary Scan (JTAG) Chain
After the ChipScope Pro Analyzer tool has successfully communicated with a download
cable, it automatically queries the boundary scan (JTAG) chain to find its composition. All
Xilinx FPGA, CPLD, PROM, and System ACE™ devices are automatically detected. The
entire IDCODE can be verified for valid target devices. To view the chain composition,
select
JTAG Chain >
JTAG Chain Setup
. A dialog box appears with all detected devices in
order.
For devices that are not automatically detected, you must specify the IR (Instruction
Register) length to insure proper communication to the cores. This information can be
found in the BSDL file for the device. USERCODEs can be read out of the ChipScope Pro
target FPGA devices by selecting
Read USERCODEs
.
The ChipScope Pro Analyzer tool automatically keeps track of the test access port (TAP)
state of the devices in the JTAG chain, by default. If the ChipScope Pro Analyzer tool is
used in conjunction with other JTAG controllers (such as the System ACE CF controller or
processor debug tools), then the actual TAP state of the target devices can differ from the
tracking copy of the ChipScope Pro Analyzer tool. In this case, the ChipScope Pro Analyzer
tool must always put the TAP controllers into a known state (for example, the Run-
Test/Idle state) before starting any JTAG transaction sequences. Clicking on the
Advanced
button on the JTAG Chain Device Order dialog box reveals the parameters that control the
start and end states of JTAG transactions. Use the
Start transactions in Test-Logic/Reset,
End in Run-Test/Idle
selection if the JTAG chain is shared with other JTAG controllers.
Device Configuration
The ChipScope Pro Analyzer tool can configure target FPGA devices using the following
download cables in JTAG mode only: Platform Cable USB, Parallel Cable III, Parallel Cable
IV.
If the target device is to be programmed using a download cable by way of the JTAG port,
select the
Device
menu, select the device you wish to configure, and select the
Configure
