46
ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 3:
Using the ChipScope Pro Core Inserter
TDM Rate
The
time division multiplexing
(TDM) rate is used to increase the amount of data transmitted
over each data pin by as much as 200 percent. The ATC2 core does not use on-chip memory
resources to store the captured trace data. Instead, it transmits the data to be captured by
an Agilent logic analyzer that is attached to the FPGA pins using a special probe connector.
The data can be transmitted out the device pins at the same rate as the incoming DATA
port (TDM rate = 1x) or twice the rate as the DATA port (TDM rate = 2x). The TDM rate can
be set to “2x” only when the capture mode is set to STATE.
Data Width
The width of each input data port of the ATC2 core depends on the capture mode and the
TDM rate. In STATE mode, the width of each data port is equal to (ATD pin count) * (TDM
rate). In TIMING mode, the width of each data port is equal to (ATD pin count + 1) * (TDM
rate) because the ATCK pin is used as an extra data pin.
Pin Parameters
The settings in the Individual Pin Settings table control the location, I/O standard, output
drive and slew rate of each individual ATCK and ATD pin. The output clock (ATCK) and
data (ATD) pins are instantiated inside the ATC2 core for your convenience. This means
that although you do not have to bring the ATCK and ATD pins through every level of
hierarchy to the top-level of your design manually; you do need to specify the location and
other characteristics of these pins in the CORE Generator. These pin attributes are then
added to the *.ncf file of the ATC2 core.
Pin Name
The ATC2 core has two types of output pins: ATCK and ATD. The ATCK pin is used as a
clock pin when the capture mode is set to STATE and is used as a data pin when the
capture mode is set to TIMING. The ATD pins are always used as data pins. The names of
the pins cannot be changed.
Pin Loc
The Pin Loc column is used to set the location of the ATCK or ATD pin.
IO Standard
The IO Standard column is used to set the I/O standard of each ATCK or ATD pin. The I/O
standards that are available for selection depend on the device family and driver endpoint
type. The names of the I/O standards are the same as those in the IOSTANDARD section
of the
Constraints Guide
in the
.
VCCO
The VCCO column setting denotes the output voltage of the pin driver and depends on the
IO Standard selection.
Drive
The Drive column setting denotes the maximum output current drive of the pin driver and
ranges from 2 to 24 mA, depending on the IO Standard selection.
Slew Rate
The Slew Rate column can be set to either FAST or SLOW for each ATCK or ATD pin.
