ChipScope Pro Software and Cores User Guide
215
UG029 (v14.3) October 16, 2012
Xilinx JTAG Programming Cable Troubleshooting
6.
Do you have more than five
devices in your JTAG chain and
use un-buffered TCK and TMS
nets?
If YES: You might need to buffer your TCK and TMS signals. A general rule of
thumb is that for chains over five devices you should use buffers. The LS244 is
an example of a buffer that has been used successfully with Xilinx devices. As
specified by the IEEE 1149.1 standard, the TMS and TDI pins both have internal
pull-up resistors. These internal pull-up resistors of 50-150k are active,
regardless of the mode selected. Please refer to the appropriate configuration
user guide for the FPGA device family to obtain the resistor value:
•
Spartan-3 FPGA Configuration User Guide
•
Spartan-6 FPGA Configuration User Guide
•
Virtex-4 FPGA Configuration User Guide
•
Virtex-5 FPGA Configuration User Guide
•
Virtex-6 FPGA Configuration User Guide
If NO: Go to Issue #7
7.
Are you running TCK to fast?
If YES or NOT SURE: Reduce the speed of the cable using the JTAG Chain >
Xilinx Platform USB Cable > Speed option to slow the frequency of the TCK pin
to the lowest setting.
If NO: Open a case with Xilinx Technical Support including the following
information:
•
Xinfo
•
cs_analyzer.log
•
Screenshots of the JTAG lines (TDI, TDO, TCK and TMS) during a JTAG
operation. Preferably the screen shot is close to the target FPGA and
focussed in on one rising edge of TCK.
Table A-6:
Troubleshooting JTAG Device Detection Issues
(Cont’d)
Issue(s)
Solution(s) or Work-Around(s)
