16
ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 1:
Introduction
ILA Control and Status Logic
The ILA contains a modest amount of control and status logic that is used to maintain the
normal operation of the core. All logic necessary to properly identify and communicate
with the ILA core is implemented by this control and status logic.
VIO Core
The Virtual Input/Output (VIO) core is a customizable core that can both monitor and
drive internal FPGA signals in real time. Unlike the ILA core, no on- or off-chip RAM is
required. Four kinds of signals are available in a the VIO core:
•
Asynchronous inputs:
−
These are sampled using the JTAG clock signal that is driven from the JTAG cable.
−
The input values are read back periodically and displayed in the ChipScope Pro
Analyzer tool.
•
Synchronous inputs:
−
These are sampled using the design clock.
−
The input values are read back periodically and displayed in the ChipScope Pro
Analyzer tool.
•
Asynchronous outputs:
−
You define these in the ChipScope Pro Analyzer tool and drive them out of the
core to the surrounding design.
−
A logical 1 or 0 value can be defined for individual asynchronous outputs.
•
Synchronous outputs:
−
You
define
these in the ChipScope Pro Analyzer tool. They are
synchronized
to the
design clock and
driven out
of the core to the surrounding design.
−
A logical 1 or 0 can be defined for individual synchronous outputs. Pulse trains of
16 clock cycles worth of 1’s and/or 0’s can also be defined for synchronous
outputs.
Activity Detectors
Every VIO core input has additional cells to capture the presence of transitions on the
input. Because the design clock will most likely be much faster than the sample period of
the ChipScope Pro Analyzer tool, it is possible for the signal being monitored to transition
many times between successive samples. The activity detectors capture this behavior and
the results are displayed along with the value in the ChipScope Pro Analyzer tool.
In the case of a synchronous input, activity cells capable of monitoring for asynchronous
and synchronous events are used. This feature can be used to detect glitches as well as
synchronous transitions on the synchronous input signal.
Pulse Trains
Every VIO synchronous output has the ability to output a static 1, a static 0, or a pulse train
of successive values. A pulse train is a 16-clock cycle sequence of 1's and 0's that drive out
of the core on successive design clock cycles. The pulse train sequence is defined in the
ChipScope Pro Analyzer tool and is executed only one time after it is loaded into the core.
