Xilinx ChipScope Pro, User Manual

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10 www.xilinx.com ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 1: Introduction
ChipScope Pro Cores Description
ICON Core
All the cores use the JTAG boundary scan port to communicate to the host computer via a
JTAG download cable. The ICON core provides a communications path between the JTAG
boundary scan port of the target FPGA and up to 15 ILA, VIO, and/or ATC2 cores (as
shown in
Figure 1-1, page 6 ).
For devices of the Spartan-3, Spartan-3E, Spartan-3A, and Spartan-3A DSP families, the
ICON core uses either the USER1 or USER2 JTAG boundary scan instructions for
communication via the BSCAN primitive. The unused USER1 or USER2 scan chain of the
BSCAN primitive can also be exported for use in your application, if needed.
For all other supported devices, the ICON core uses any one of the USER1, USER2, USER3
or USER4 scan chains available via the BSCAN primitives. It is not necessary to export
unused USER scan chains because each BSCAN primitive implements a single scan chain.
ILA Core
The ILA core is a customizable logic analyzer core that can be used to monitor any internal
signal of your design. Because the ILA core is synchronous to the design being monitored,
all design clock constraints that are applied to your design are also applied to the
components inside the ILA core. The ILA core consists of three major components:
•
Trigger input and output logic:
−
Trigger input logic detects elaborate trigger events.
−
Trigger output logic triggers external test equipment and other logic.
•
Data capture logic:
−
ILA cores capture and store trace data information using on-chip block RAM
resources.
•
Control and status logic:
−
Manages the operation of the ILA core.
ILA Trigger Input Logic
The triggering capabilities of the ILA core include many features that are necessary for
detecting elaborate trigger events. These features are described in
Table 1-3 .
Table 1-3: Trigger Features of the ILA Core
Feature Description
Wide Trigger Ports Each trigger port can be 1 to 256 bits wide.
Multiple Trigger Ports
Each ILA core can have up to 16 trigger ports. The ability to
support multiple trigger ports is necessary in complex systems
where different types of signals or buses must be monitored
using separate match units.
Multiple Match Units per
Trigger Port
Each trigger port can be connected to up to 16 match units. This
feature enables multiple comparisons to be performed on the
trigger port signals.