ChipScope Pro Software and Cores User Guide
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UG029 (v14.3) October 16, 2012
ChipScope Pro Analyzer Features
Update Static Outputs
By default, when one VIO core output is changed, information is immediately sent to the
VIO core to set up that particular output. To update all non-pulse train outputs at once,
click
Update Static Outputs (U!)
toolbar button or select the
VIO
>
Update Static Outputs
menu option.
Reset All Outputs
To reset all outputs to their default state (0 for text fields and toggle buttons, all 0 pulse
train for pulse trains) click the
Reset All Outputs
toolbar button or select the
VIO
>
Reset
All Outputs
menu option.
Clear All Activity
At some point, it might be desirable to reset the activity display for all VIO core inputs. To
do so, press the
Clear All Activity
toolbar button or select the
VIO
>
Clear All Activity
menu option. All input activity is reset, regardless of the selected persistence.
System Monitor
Virtex®-5, Virtex-6, Virtex-7, and Kintex™-7 FPGA and Zynq™-7000 AP SoC devices
include a System Monitor feature, also called Xilinx Analog-to-Digital Converter (XADC).
When combined with a number of on-chip sensors, the ADC can measure FPGA physical
operating parameters, including on-chip power supply voltages and die temperature. For
more information refer to the following documents:
•
Virtex-5 FPGA System Monitor User Guide
•
Virtex-6 FPGA System Monitor User Guide
•
7 Series FPGAs XADC Dual 12-Bit 1MSPS Analog-to-Digital Converter User Guide
The ChipScope Pro Analyzer tool provides real-time JTAG access to the on-chip voltage
and temperature sensors of the System Monitor primitive. All the on-chip sensors are
available before and after the FPGA device has been configured with a valid bitstream. The
System Monitor functionality does not require that you instantiate a System Monitor
primitive block into your design. The only requirement is that the System Monitor-specific
pins on the FPGA device are properly connected on the system board.
In the ChipScope Pro Analyzer project tree, each System Monitor-capable FPGA device in
the JTAG chain has a System Monitor Console node. Right-clicking on the System Monitor
node in the project tree shows an option for opening the System Monitor viewer. Left-
clicking on the System Monitor node in the project tree shows the various sensors in the
signal browser. In the signal (or sensor) browser, you can rename or change the display
units of the various sensors.
System Monitor Console
Each System Monitor sensor value can be displayed in a System Monitor Console history
window or written to a log file. You can enable the following display values for each
sensor:
•
Current value that is read directly from the System Monitor sensor
•
Device maximum and minimum values that are read directly from the System
Monitor sensor peak detectors
