12
ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 1:
Introduction
Choice of Match Function
Event Counter
All the match units of a trigger port can be configured with an
event counter, with a selectable size of 1 to 32 bits. This counter
can be configured at runtime to count events in the following
ways:
•
Exactly
n
occurrences
−
Matches only when exactly
n
consecutive or non-
consecutive events occur
•
At least
n
occurrences
−
Matches and stays asserted after
n
consecutive or
non-consecutive events occur
•
At least
n
consecutive occurrences
−
Matches after
n
consecutive events occur, and stays
asserted until the match function is not satisfied.
Trigger Output Port
The internal trigger condition of the ILA core can be accessed
using the optional trigger output port. This signal can be used as
a trigger for external test equipment by attaching the signal to an
output pin.
However, it can also be used by internal logic as an interrupt, a
trigger, or to cascade multiple ILA cores together.
The trigger output port of the ILA core has a latency of 10 clock
cycles.
The shape (level or pulse) and sense (
active-High or
active-Low) of the trigger output can be controlled at run-time.
a. LUT4-based device families are Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP, and Virtex-4
FPGAs (and the variants of these families).
b. LUT6-based device families include Zynq™ -7000 AP SoCs and, Virtex-5, Virtex-6, Spartan-6, Artix™-
7, Kintex-7, and Virtex-7 FPGAs (and the variants of these families).
Table 1-3:
Trigger Features of the ILA Core
(Cont’d)
Feature
Description
