ChipScope Pro Software and Cores User Guide
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UG029 (v14.3) October 16, 2012
ChipScope Pro Core Inserter Features
Max Frequency Range
The Max Frequency Range parameter is used to specify the maximum frequency range in
which you expect to operate the ATC2 core. The implementation of the ATC2 core is
optimized for the maximum frequency range selection. The valid maximum frequency
ranges are 0-100 MHz, 101-200 MHz, 201-300 MHz, and 301-500 MHz. The maximum
frequency range selection only has an affect on core implementation when the Capture
Mode is set to STATE mode.
Enable Auto Setup
The Enable Auto Setup option is used to enable a feature that allows the Agilent Logic
Analyzer to automatically set up the appropriate ATC2 pin to Logic Analyzer pod
connections. This feature also allows the Agilent Logic Analyzer to automatically
determine the optimal phase and voltage sampling offsets for each ATC2 pin. This feature
is enabled by default.
Enable "Always On" Mode
The Enable "Always On" Mode option is used to force an ATC2 core to always enable its
internal logic and output buffers. The "Always On" mode ensures that signal bank 0 is
driven out to the ATD pins upon FPGA device configuration. This mode makes it possible
to capture events that immediately follow device configuration without having to first set
up the ATC2 core manually. This feature is disabled by default and is only available when
the capture mode is set to TIMING mode.
Pin Edit Mode
The Pin Edit Mode parameter is a time saving feature that allows you to change the IO
Standard, Drive, and Slew Rate pin parameters on individual pins or together as a group of
pins. Setting the Pin Edit Mode to
Individual
allows you to edit the parameters of each pin
independently from one another. Setting the mode to
Same as ATCK
allows you to change
the ATCK pin parameters and forces all ATD pins to the same settings. You must set
unique pin locations for each individual pin regardless of the Pin Edit Mode.
ATD Pin Count
The ATC2 core can implement any number of ATD output pins in the range of 4 through
64.
Endpoint Type
The Endpoint Type setting is used to control whether single-ended or differential output
drivers are used on the ATCK and ATD output pins. All ATCK and ATD pins must use the
same driver endpoint type.
Signal Bank Count
The ATC2 core contains an internal, run-time selectable data signal bank multiplexer. The
Signal Bank Count setting is used to denote the number of data input ports or signal banks
the multiplexer will implement. The valid Signal Bank Count values are 1, 2, 4, 8, 16, 32,
or 64.