20
ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 1:
Introduction
−
Limited PCS support, including loopback. Pattern encoding, clock correction, and
channel bonding are not supported.
Table 1-4:
IBERT v2.0 Core for the Virtex-5 FPGA GTX Transceivers
Feature
Description
Multiple GTX
Transceivers
Up to eight transceivers can be selected per design.
Pattern Generator
One pattern generator per selected GTX transceiver is used.
PRBS 7-bit, PRBS 15-bit PRBS 23-bit, PRBS 31-bit, Clk 2x, and Clk
10x patterns are available. The desired pattern from that set can
be selected individually for each GTX transceiver at runtime.
Pattern Checker
One pattern checker per selected GTX transceiver is used. The
same pattern set is available as the pattern generator. The pattern
can be chosen for each GTX transceiver at runtime.
Fabric Width
The FPGA fabric interface to the GTX_DUAL tile can be either
32- or 40-bits wide and selectable at generate time.
BERT Parameters
Number of bits received in error and total number of words
received are gathered dynamically and read out by the
ChipScope Pro Analyzer tool.
Polarity
The polarity of the TX or RX side of each GTX transceiver can be
changed at runtime.
Reset
Each GTX transceiver and its BER counters can be reset
independently. A reset is also available to reset the entire MGT,
including PLLs.
Link and Lock Status
Link, DCM, and PLL lock status are gathered for each GTX
transceiver in the core.
DRP Read
The contents of the DRP space for each GTX transceiver can be
read independently of all others.
DRP Write
The contents of the DRP space for each GTX transceiver can be
changed at runtime, with single-bit granularity.
Ports Read
The contents of the registers that monitor the GTX transceiver
ports can be read independently of others.
Ports Write
The contents of the registers that control the GTX transceiver's
ports can be changed at runtime.
Status
The dynamic status information for the entire core can be read
out of the core at runtime.
