General Lists
Name
Description
Logics.LE41.Timer Out
Signal: Timer Output
Logics.LE41.Out
Signal: Latched Output (Q)
Logics.LE41.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE41.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE41.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE41.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE41.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE41.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE42.Gate Out
Signal: Output of the logic gate
Logics.LE42.Timer Out
Signal: Timer Output
Logics.LE42.Out
Signal: Latched Output (Q)
Logics.LE42.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE42.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE42.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE42.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE42.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE42.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE43.Gate Out
Signal: Output of the logic gate
Logics.LE43.Timer Out
Signal: Timer Output
Logics.LE43.Out
Signal: Latched Output (Q)
Logics.LE43.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE43.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE43.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE43.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE43.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE43.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE44.Gate Out
Signal: Output of the logic gate
Logics.LE44.Timer Out
Signal: Timer Output
Logics.LE44.Out
Signal: Latched Output (Q)
Logics.LE44.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE44.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE44.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE44.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE44.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE44.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE45.Gate Out
Signal: Output of the logic gate
Logics.LE45.Timer Out
Signal: Timer Output
Logics.LE45.Out
Signal: Latched Output (Q)
Logics.LE45.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE45.Gate In1-I
State of the module input: Assignment of the Input Signal
622
MRU4
DOK-HB-MRU4-2E