General Lists
Name
Description
Logics.LE36.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE36.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE36.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE37.Gate Out
Signal: Output of the logic gate
Logics.LE37.Timer Out
Signal: Timer Output
Logics.LE37.Out
Signal: Latched Output (Q)
Logics.LE37.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE37.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE37.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE37.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE37.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE37.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE38.Gate Out
Signal: Output of the logic gate
Logics.LE38.Timer Out
Signal: Timer Output
Logics.LE38.Out
Signal: Latched Output (Q)
Logics.LE38.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE38.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE38.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE38.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE38.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE38.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE39.Gate Out
Signal: Output of the logic gate
Logics.LE39.Timer Out
Signal: Timer Output
Logics.LE39.Out
Signal: Latched Output (Q)
Logics.LE39.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE39.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE39.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE39.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE39.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE39.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE40.Gate Out
Signal: Output of the logic gate
Logics.LE40.Timer Out
Signal: Timer Output
Logics.LE40.Out
Signal: Latched Output (Q)
Logics.LE40.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE40.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE40.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE40.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE40.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE40.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE41.Gate Out
Signal: Output of the logic gate
621
MRU4
DOK-HB-MRU4-2E