General Lists
Name
Description
Logics.LE67.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE67.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE68.Gate Out
Signal: Output of the logic gate
Logics.LE68.Timer Out
Signal: Timer Output
Logics.LE68.Out
Signal: Latched Output (Q)
Logics.LE68.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE68.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE68.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE68.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE68.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE68.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE69.Gate Out
Signal: Output of the logic gate
Logics.LE69.Timer Out
Signal: Timer Output
Logics.LE69.Out
Signal: Latched Output (Q)
Logics.LE69.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE69.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE69.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE69.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE69.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE69.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE70.Gate Out
Signal: Output of the logic gate
Logics.LE70.Timer Out
Signal: Timer Output
Logics.LE70.Out
Signal: Latched Output (Q)
Logics.LE70.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE70.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE70.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE70.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE70.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE70.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE71.Gate Out
Signal: Output of the logic gate
Logics.LE71.Timer Out
Signal: Timer Output
Logics.LE71.Out
Signal: Latched Output (Q)
Logics.LE71.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE71.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE71.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE71.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE71.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE71.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE72.Gate Out
Signal: Output of the logic gate
Logics.LE72.Timer Out
Signal: Timer Output
628
MRU4
DOK-HB-MRU4-2E