General Lists
Name
Description
Logics.LE32.Out
Signal: Latched Output (Q)
Logics.LE32.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE32.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE32.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE32.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE32.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE32.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE33.Gate Out
Signal: Output of the logic gate
Logics.LE33.Timer Out
Signal: Timer Output
Logics.LE33.Out
Signal: Latched Output (Q)
Logics.LE33.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE33.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE33.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE33.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE33.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE33.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE34.Gate Out
Signal: Output of the logic gate
Logics.LE34.Timer Out
Signal: Timer Output
Logics.LE34.Out
Signal: Latched Output (Q)
Logics.LE34.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE34.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE34.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE34.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE34.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE34.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE35.Gate Out
Signal: Output of the logic gate
Logics.LE35.Timer Out
Signal: Timer Output
Logics.LE35.Out
Signal: Latched Output (Q)
Logics.LE35.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE35.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE35.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE35.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE35.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE35.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE36.Gate Out
Signal: Output of the logic gate
Logics.LE36.Timer Out
Signal: Timer Output
Logics.LE36.Out
Signal: Latched Output (Q)
Logics.LE36.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE36.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE36.Gate In2-I
State of the module input: Assignment of the Input Signal
620
MRU4
DOK-HB-MRU4-2E