Protective Elements
Signals that Trigger a Synchrocheck
Name
Description
-.-
No assignment
SG[1].Sync ON request
Signal: Synchronous ON request
DI Slot X1.DI 1
Signal: Digital Input
DI Slot X1.DI 2
Signal: Digital Input
DI Slot X1.DI 3
Signal: Digital Input
DI Slot X1.DI 4
Signal: Digital Input
DI Slot X1.DI 5
Signal: Digital Input
DI Slot X1.DI 6
Signal: Digital Input
DI Slot X1.DI 7
Signal: Digital Input
DI Slot X1.DI 8
Signal: Digital Input
Logics.LE1.Gate Out
Signal: Output of the logic gate
Logics.LE1.Timer Out
Signal: Timer Output
Logics.LE1.Out
Signal: Latched Output (Q)
Logics.LE1.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE2.Gate Out
Signal: Output of the logic gate
Logics.LE2.Timer Out
Signal: Timer Output
Logics.LE2.Out
Signal: Latched Output (Q)
Logics.LE2.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE3.Gate Out
Signal: Output of the logic gate
Logics.LE3.Timer Out
Signal: Timer Output
Logics.LE3.Out
Signal: Latched Output (Q)
Logics.LE3.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE4.Gate Out
Signal: Output of the logic gate
Logics.LE4.Timer Out
Signal: Timer Output
Logics.LE4.Out
Signal: Latched Output (Q)
Logics.LE4.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE5.Gate Out
Signal: Output of the logic gate
Logics.LE5.Timer Out
Signal: Timer Output
Logics.LE5.Out
Signal: Latched Output (Q)
Logics.LE5.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE6.Gate Out
Signal: Output of the logic gate
Logics.LE6.Timer Out
Signal: Timer Output
Logics.LE6.Out
Signal: Latched Output (Q)
Logics.LE6.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE7.Gate Out
Signal: Output of the logic gate
Logics.LE7.Timer Out
Signal: Timer Output
Logics.LE7.Out
Signal: Latched Output (Q)
446
MRU4
DOK-HB-MRU4-2E