General Lists
Name
Description
Logics.LE23.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE23.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE23.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE23.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE23.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE23.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE24.Gate Out
Signal: Output of the logic gate
Logics.LE24.Timer Out
Signal: Timer Output
Logics.LE24.Out
Signal: Latched Output (Q)
Logics.LE24.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE24.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE24.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE24.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE24.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE24.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE25.Gate Out
Signal: Output of the logic gate
Logics.LE25.Timer Out
Signal: Timer Output
Logics.LE25.Out
Signal: Latched Output (Q)
Logics.LE25.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE25.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE25.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE25.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE25.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE25.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE26.Gate Out
Signal: Output of the logic gate
Logics.LE26.Timer Out
Signal: Timer Output
Logics.LE26.Out
Signal: Latched Output (Q)
Logics.LE26.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE26.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE26.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE26.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE26.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE26.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logics.LE27.Gate Out
Signal: Output of the logic gate
Logics.LE27.Timer Out
Signal: Timer Output
Logics.LE27.Out
Signal: Latched Output (Q)
Logics.LE27.Out inverted
Signal: Negated Latched Output (Q NOT)
Logics.LE27.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE27.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE27.Gate In3-I
State of the module input: Assignment of the Input Signal
618
MRU4
DOK-HB-MRU4-2E