DE4 User Manual
139
www.terasic.com
June 20, 2018
The EXT_PLL_CTRL IP Parameter Setting
Users can refer to the following
Table 5–2
to set the external clock generator for the output
frequency.
Table 5–2 EXT_PLL_CTRL Instruction Ports
clk1_set_wr/ clk2_set_wr/
clk3_set_wr
Output Frequency
(
MHz
)
Description
4’b0001
x
Clock Generator Disable
4’b0010
62.5
Setting External Clock Generator
4’b0011
75
4’b0100
100
4’b0101
125
4’b0110
150
4’b0111
156.23
4’b1000
187
4’b1001
200
4’b1010
250
4’b1011
312.5
4’b1100
625
others
x
Setting Unchanged
The EXT_PLL_CTRL IP Timing Diagram
In this reference design the output frequency is set to 62.5, 75 and 100 MHz with the following
timing diagrams illustrated below.
When the EXT_PLL_CTRL IP receives the ‘conf_wr’ signal, the user needs to define (clk1_set_wr,
clk2_set_wr and clk3_set_wr) to set the External Clock Generator. When the ext_pll_ctrl IP
receives the ‘conf_rd’ signal, it will read the value back to clk1_set_rd, clk2_set_rd, and
clk3_set_rd.
Write Timing Waveform:
As Button0 (PB1) is pressed the 'conf_wr' signal is on the rising edge, serial data is transfered
Summary of Contents for ALTERA DE4
Page 1: ...DE4 User Manual 1 www terasic com June 20 2018 ...
Page 54: ...DE4 User Manual 54 www terasic com June 20 2018 ...
Page 83: ...DE4 User Manual 83 www terasic com June 20 2018 Figure 3 8 Access DDR2 SO DIMM memory ...
Page 92: ...DE4 User Manual 92 www terasic com June 20 2018 Figure 3 17 Fan Control of the DE4 ...
Page 150: ...DE4 User Manual 150 www terasic com June 20 2018 Figure 5 35 SOPC builder ...