Terasic ALTERA DE4 User Manual Download Page 135

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DE4 User Manual

135

www.terasic.com

June 20, 2018

Figure 5

–24 Display progress and result information for the DDR2 demonstration

The External Clock Generator provides designers using the 3 programmable clock geneators via

Texas Instruments chips (CDCM61001RHBT x 2, CDCM61004RHBT) the ability to specify the

clock frequency individually, in addition addressing the input reference clock for the Stratix IV GX

transceivers. The programmable clock is controlled by a control bus connected to the MAX II

EPM2210 device. This can reduce the Stratix IV GX I/O usage while enabling greater functionality

on the FPGA device. The MAX II EPM2210 device is capable of storing the last entered clock

settings at which in the event the board restarts, the last known clock settings are fully restored. In

this demonstration, we illustrate how to utilize the clock generators IP to define the clock output

using the serial bus. The programmable clock output generates clock frequencies of 62.5, 75, 100,

125, 150, 156.25, 187.5, 200, 250, 312.5, and 625MHz for these clock signals:



SATA_REFCLK/PLL_CLKIN (CDC61004RHBT)



HSMA_REFCLK (CDCM61101/01)



HSMB_REFCLK (CDCM61101/02)

Clock signals SATA_REFCLK and PLL_CLKIN are derived from the same programmable clock

Summary of Contents for ALTERA DE4

Page 1: ...DE4 User Manual 1 www terasic com June 20 2018 ...

Page 2: ...22 2 5 HIGH SPEED MEZZANINE CARDS 26 2 6 GPIO EXPANSION HEADERS 37 2 7 DDR2 SO DIMM 41 2 8 USB OTG 49 2 9 SD CARD 52 2 10 CLOCK CIRCUITRY 53 2 11 PCI EXPRESS 57 2 12 GIGABIT ETHERNET GIGE 60 2 13 SERIAL ATA SATA 63 2 14 RS 232 SERIAL PORT 66 2 15 FLASH MEMORY 66 2 16 SSRAM MEMORY 68 2 17 I2C SERIAL EEPROM 70 2 18 TEMPERATURE SENSOR 70 2 19 POWER 71 CHAPTER 3 CONTROL PANEL 74 3 1 CONTROL PANEL SETU...

Page 3: ... 4 2 GENERAL DESIGN FLOW 94 4 3 USING DE4 SYSTEM BUILDER 95 CHAPTER 5 EXAMPLES OF ADVANCED DEMONSTRATION 106 5 1 USB HOST 106 5 2 USB DEVICE 115 5 3 ETHERNET SIMPLE SOCKET SERVER 119 5 4 SD CARD READER 127 5 5 DDR2 SDRAM 131 5 6 EXTERNAL CLOCK GENERATOR 135 5 7 POWER MEASUREMENT 142 5 8 WEB SERVER 146 5 9 SERIAL ATA SATA 155 5 10 HIGH SPEED MEZZANINE CARD HSMC 156 5 11 PCIE DEMONSTRATION 158 ADDIT...

Page 4: ...Stratix IV GX FPGA platform with integrated transceivers have allowed the DE4 to fully compliant with version 2 0 of the PCI Express standard This will accelerate mainstream development of PCI Express based applications enabling customers to deploy designs for a broad range of high speed connectivity applications The DE4 coupled with serial ATA SATA interfaces offer a solution for developing stora...

Page 5: ...via MAX II CPLD and flash memory o Three External Programmable PLL timing chip Component and interfaces o Four Gigabit Ethernet GigE with RJ 45 connector o Two host and two device Serial ATA SATA II ports o Two HSMC connectors o Two 40 pin expansion headers o PCI Express 2 0 x8 lane connector Memory o DDR2 SO DIMM socket o FLASH o SSRAM o SD Card socket o I2C EEPROM General user input output o 8 L...

Page 6: ...asurement o Temperature sensor 1 1 3 3 B Bo oa ar rd d O Ov ve er rv vi ie ew w Figure 1 1 and Figure 1 2 is the top and bottom view of the DE4 board It depicts the layout of the board and indicates the location of the connectors and key components Users can refer to this figure for relative location when the connectors and key components are introduced in the following chapters Figure 1 1 The DE4...

Page 7: ...view 1 1 4 4 B Bl lo oc ck k D Di ia ag gr ra am m Figure 1 3 shows the block diagram of the DE4 board To provide maximum flexibility for the users all key components are connected with the Stratix IV GX FPGA device Thus users can configure the FPGA to implement any system design ...

Page 8: ...DE4 User Manual 8 www terasic com June 20 2018 Figure 1 3 Block diagram of the DE4 board Below is more detailed information regarding the blocks in Figure 1 3 ...

Page 9: ...s o 27 376K total memory Kbits o 1 024 18x18 bit multipliers blocks o 4 PCI Express hard IP Blocks o 744 user I Os o 8 phase locked loops PLLs Configuration device and USB Blaster circuit MAXII CPLD EPM2210 System Controller and Fast Passive Parallel FPP configuration On board USB Blaster for use with the Quartus II Programmer Programmable PLL timing chip configured via MAX II CPLD Support JTAG mo...

Page 10: ...Ds 2 seven segment displays 8 user DIP switches Push buttons 4 user defined inputs Normally high generates one active low pulse when the switch is pressed Slide switches 4 slide switches for user defined inputs When a switch is set to the DOWN or UP position it causes logic 0 or 1 respectively On Board Clocking Circuitry 50MHz 100MHz oscillator 2 SMA connector for external transceiver clock input ...

Page 11: ...motherboard with x8 or x16 PCI Express slot Two High Speed Mezzanine Card HSMC 2 female HSMC connectors Total of 12 pairs CDR based transceivers at data rate up to 8 5Gbps Total 38 LVDS transmitter channels at data rate up to 1 6Gbps and 36 LVDS receiver channels I O voltage 2 5V Two 40 pin expansion headers 72 FPGA I O pins as well as 4 power and ground lines are brought out to two 40 pin expansi...

Page 12: ...ta transfer at high speed full speed and low speed Support both USB host and device Three USB ports one type mini AB for host device and two type A for host Support Nios II with the Terasic driver Power Standalone DC inputs 12V and 3 3V PCI Express edge connector power Optional PCI Express external power source On Board power measurement circuitry ...

Page 13: ...nt kit contents Key features Before you begin Software Installation Development board setup Programming the Stratix IV GX device on the DE4 board Programming through the Flash memory device 2 2 1 1 C Co on nf fi ig gu ur ra at ti io on n O Op pt ti io on ns s JTAG FPGA Programming over USB Blaster The USB blaster is implemented on the DE4 board to provide JTAG configuration through onboard USB to ...

Page 14: ...tus II Programmer by selecting a configuration bit stream file with the sof filename extension Please refer to DE4 Getting Started Guide pdf for more detailed procedure of FPGA programming Figure 2 1 JTAG configuration scheme Flash Programming The DE4 development board contains a common flash interface CFI flash memory to meet the demands for a larger FPGA configuration storage The parallel flash ...

Page 15: ...amming instruction on parallel flash loader on the CFI flash memory Figure 2 2 Flash programming scheme Programming Flash Memory using batch file The DE4 provides a program_flash batch file demonstrations de4_ Stratix device de4_board_ update_portal demo_batch Program_flash to limit the steps that are taken when users program the flash memory on the DE4 Software Requirements Quartus II 9 1 SP2 or ...

Page 16: ... J5 In addition place the sof and elf file optional you wish to program convert in the Program_flash directory Programming Flash Memory with sof using Program_flash bat 1 Launch the program_flash bat batch file from the directory demonstrations de4_ Stratix device de4_board_update_portal demo_batch Program_flash of the DE4 system CD ROM 2 The flash program tool shows the menu options Figure 2 3 Fl...

Page 17: ...of name to be program 5 The following lines will appear during flash programming Extracting Option bits SREC Extracting FPGA Image SREC and Deleting intermediate files If these lines don t appear on the windows command programming on the flash memory is not successfully setup Please make sure Quartus II 9 1 SP2 and Nios II 9 1 IDE SP2 or later is used ...

Page 18: ...DE4 User Manual 18 www terasic com June 20 2018 Figure 2 6 Loading sof file to be program 6 Erasing flash Figure 2 7 Erasing flash 7 Programming flash ...

Page 19: ...DE4 User Manual 19 www terasic com June 20 2018 Figure 2 8 Programming flash 8 Programming complete Figure 2 9 Programming flash complete ...

Page 20: ...tch Board Reference Signal Name Description Default SW8 1 JTAG_HSMA_EN On Bypass HSMA Off HSMA In chain On SW8 2 JTAG_HSMB_EN On Bypass HSMB Off HSMB In chain On SW8 3 JTAG_PCIE_EN On Bypass PCI Express Off PCI Express In Chain On PCI Express Control DIP switch The PCI Express Control DIP switch is provided to enable or disable different configurations of the PCIe Connector Table 2 2 lists the swi...

Page 21: ...ster CPLD D19 Error Illuminates when the MAX II CPLD EPM2210 System Controller fails to configure the FPGA Driven by the MAX II CPLD EPM2210 System Controller D12 USB Blaster Circuit Illuminates when USB blaster circuit transmits or receives data D17 HSMC Port B Present Illuminates when the HSMC port B has a board or cable plugged in such that pin 160 becomes grounded Driven by the add in card D16...

Page 22: ...Stratix IV GX Pin Number PB1 BUTTON0 High Logic Level when button not pressed 3 0 V PIN_AH5 PB2 BUTTON1 High Logic Level when button not pressed 3 0 V PIN_AG5 PB3 BUTTON2 High Logic Level when button not pressed 3 0 V PIN_AG7 PB4 BUTTON3 High Logic Level when button not pressed 3 0 V PIN_AH8 PB5 CPU_RESET_n FPGA reset 2 5 V PIN_V34 PB6 RE_CONFIGn Max II EPM2210 System re configuration A CPU reset ...

Page 23: ...2 6 DIP Switch Pin Assignments Schematic Signal Names and Functions Board Reference Schematic Signal Name Description I O Standard Stratix IV GX Pin Number SW6 SW0 User Defined DIP switch connected to FPGA device When the switch is in the ON position a logic 0 is selected Similarly when the switch is in the OFF position a logic 1 is selected 3 0 V PIN_AB13 SW6 SW1 3 0 V PIN_AB12 SW6 SW2 3 0 V PIN_...

Page 24: ...LED3 2 5 V PIN_P29 D5 LED4 2 5 V PIN_N29 D6 LED5 2 5 V PIN_M29 D7 LED6 2 5 V PIN_M30 D8 LED7 2 5 V PIN_N30 7 Segment Displays The DE4 board has two 7 segment displays As indicated in the schematic in Figure 2 10 the seven segments are connected to pins of the Stratix IV GX FPGA Applying a low or high logic level to a segment to light it up or turns it off Each segment in a display is identified by...

Page 25: ...ames and Functions Board Reference Schematic Signal Name Description I O Standard Stratix IV GX Pin Number HEX1 SEG1_D0 User Defined 7 Segment Display Driving a logic 0 on the I O port turns the 7 segment signal ON Driving a logic 1 on the I O port turns the 7 segment signal OFF 2 5 V PIN_E31 HEX1 SEG1_D1 2 5 V PIN_F31 HEX1 SEG1_D2 2 5 V PIN_G31 HEX1 SEG1_D3 2 5 V PIN_C34 HEX1 SEG1_D4 2 5 V PIN_C3...

Page 26: ...d inputs high speed serial I O transceivers and single ended or differential signaling Both the HSMC interfaces connected to the Stratix IV GX device are female HSMC connectors with each connector having a total of 172pins including 121 signal pins 120 signal pins 1 PSNTn pin 39 power pins and 12 ground pins The HSMC connector is based on the Samtec 0 5 mm pitch surface mount QSH family of high sp...

Page 27: ...er channels and 18 pairs LVDS receiver channels While port B of the HSMC connector consists of 8 pairs CDR based transceivers 19 pairs LVDS transmitter channels and 18 pairs LVDS receiver channels Additionally both ports A and B of the HSMC interfaces have 5 clock inputs and 4 clock outputs 2 differential clock inputs and outputs I O Standards The HSMC interface has programmable bi directional I O...

Page 28: ...nnected to either ports A or B of the HSMC connector shown in Figure 2 13 Figure 2 13 Connection setup between THCB HMF2 adapter card and HSMC JTAG Chain on HSMC The JTAG chain on the HSMC can be activated through the 3 position DIP switch SW8 If there is no connection established on the HSMC connectors the 3 position DIP switch SW8 are to set On where the JTAG signals on the HSMC connectors are b...

Page 29: ...tion DIP switch SW8 is set to Off to which HSMC port is used In this case from Figure 2 15 HSMC port A is used where position 1 of the SW8 is set to Off Similarly if the JTAG interface isn t used on the HSMC based daughter card position 1 of SW8 is set to On bypassing the JTAG signals as shown in Figure 2 16 Figure 2 15 JTAG chain for a daughter card uses JTAG connected to HSMC port A of the DE4 ...

Page 30: ...evice in terms of design capacity In situations where users design exceeds the capacity of the FPGA the HSMC interface can be used to connect to other FPGA system boards creating a multi FPGA scalable system Figure 2 17 illustrates a connection setup between two DE4 boards by connecting through port B and Port A of the HSMC connectors using a Samtec high speed cable Notice the JTAG switch SW8 conf...

Page 31: ...sceiver RX bit 6n 1 4 V PCML PIN_E1 9 HSMB_GXB_TX_p5 Transceiver TX bit 5 1 4 V PCML PIN_K4 10 HSMB_GXB_RX_p5 Transceiver RX bit 5 1 4 V PCML PIN_L2 11 HSMB_GXB_TX_n5 Transceiver RX bit 5n 1 4 V PCML PIN_K3 12 HSMB_GXB_RX_n5 Transceiver RX bit 5n 1 4 V PCML PIN_L1 13 HSMB_GXB_TX_p4 Transceiver TX bit 4 1 4 V PCML PIN_M4 14 HSMB_GXB_RX_p4 Transceiver RX bit 4 1 4 V PCML PIN_N2 15 HSMB_GXB_TX_n4 Tra...

Page 32: ... LVDS TX bit 0 or CMOS I O LVDS or 2 5 V PIN_K9 48 HSMB_RX_p0 LVDS RX bit 0 or CMOS I O LVDS or 2 5 V PIN_D5 49 HSMB_TX_n0 LVDS TX bit 0n or CMOS I O LVDS or 2 5 V PIN_J9 50 HSMB_RX_n0 LVDS RX bit 0n or CMOS I O LVDS or 2 5 V PIN_C5 53 HSMB_TX_p1 LVDS TX bit 1 or CMOS I O LVDS or 2 5 V PIN_K10 54 HSMB_RX_p1 LVDS RX bit 1 or CMOS I O LVDS or 2 5 V PIN_D10 55 HSMB_TX_n1 LVDS TX bit 1n or CMOS I O LV...

Page 33: ...S I O LVDS or 2 5 V PIN_M8 108 HSMB_RX_p9 LVDS RX bit 9 or CMOS I O LVDS or 2 5 V PIN_G8 109 HSMB_TX_n9 LVDS TX bit 9n or CMOS I O LVDS or 2 5 V PIN_M7 110 HSMB_RX_n9 LVDS RX bit 9n or CMOS I O LVDS or 2 5 V PIN_F8 113 HSMB_TX_p10 LVDS TX bit 10 or CMOS I O LVDS or 2 5 V PIN_M11 114 HSMB_RX_p10 LVDS RX bit 10 or CMOS I O LVDS or 2 5 V PIN_G9 115 HSMB_TX_n10 LVDS TX bit 10n or CMOS I O LVDS or 2 5 ...

Page 34: ...RX_n16 LVDS RX bit 16n or CMOS I O LVDS or 2 5 V PIN_W7 155 HSMB_CLKOUT_p2 LVDS TX or CMOS I O or differential clock input output LVDS or 2 5 V PIN_W12 156 HSMB_CLKIN_p2 LVDS RX or CMOS I O or differential clock input LVDS or 2 5 V PIN_W6 157 HSMB_CLKOUT_n2 LVDS TX or CMOS I O or differential clock input output LVDS or 2 5 V PIN_W11 158 HSMB_CLKIN_n2 LVDS RX or CMOS I O or differential clock input...

Page 35: ...TAG data input 2 5 V 39 HSMA_OUT0 CMOS I O LVDS or 2 5 V PIN_AF29 40 HSMA_CLKIN0 Dedicated clock input LVDS or 2 5 V PIN_AC34 41 HSMA_D0 LVDS TX or CMOS I O LVDS or 2 5 V PIN_AC26 42 HSMA_D1 LVDS RX or CMOS I O LVDS or 2 5 V PIN_AC31 43 HSMA_D2 LVDS TX or CMOS I O LVDS or 2 5 V PIN_AD26 44 HSMA_D3 LVDS RX or CMOS I O LVDS or 2 5 V PIN_AC32 47 HSMA_TX_p0 LVDS TX bit 0 or CMOS I O LVDS or 2 5 V PIN_...

Page 36: ... 98 HSMA_CLKIN_n1 LVDS RX or CMOS I O or differential clock input LVDS or 2 5 V PIN_AA35 101 HSMA_TX_p8 LVDS TX bit 8 or CMOS I O LVDS or 2 5 V PIN_AC28 102 HSMA_RX_p8 LVDS RX bit 8 or CMOS I O LVDS or 2 5 V PIN_AP32 103 HSMA_TX_n8 LVDS TX bit 8n or CMOS I O LVDS or 2 5 V PIN_AC29 104 HSMA_RX_n8 LVDS RX bit 8n or CMOS I O LVDS or 2 5 V PIN_AR32 107 HSMA_TX_p9 LVDS TX bit 9 or CMOS I O LVDS or 2 5 ...

Page 37: ...DS or 2 5 V PIN_AT34 151 HSMA_TX_n16 LVDS TX bit 16n or CMOS I O LVDS or 2 5 V PIN_AL30 152 HSMA_RX_n16 LVDS RX bit 16n or CMOS I O LVDS or 2 5 V PIN_AR34 155 HSMA_CLKOUT_p2 LVDS TX or CMOS I O or differential clock input output LVDS or 2 5 V PIN_AG34 156 HSMA_CLKIN_p2 LVDS RX or CMOS I O or differential clock input LVDS or 2 5 V PIN_AF34 157 HSMA_CLKOUT_n2 LVDS TX or CMOS I O or differential cloc...

Page 38: ...e 20 2018 Figure 2 18 Pin distribution of the GPIO expansion headers Finally Figure 2 19 shows the connections between the GPIO expansion headers and Stratix IV GX Figure 2 19 Connection between the GPIO expansion headers and Stratix IV GX ...

Page 39: ...or LVDS PIN_AE5 GPIO0_D3 GPIO Expansion 0 IO 3 3 0 V PIN_AR8 GPIO0_D4 GPIO Expansion 0 IO 4 3 0 V PIN_AN9 GPIO0_D5 GPIO Expansion 0 IO 5 3 0 V PIN_AP9 GPIO0_D6 GPIO Expansion 0 IO 6 3 0 V PIN_AV5 GPIO0_D7 GPIO Expansion 0 IO 7 3 0 V PIN_AW6 GPIO0_D8 GPIO Expansion 0 IO 8 3 0 V PIN_AV7 GPIO0_D9 GPIO Expansion 0 IO 9 3 0 V PIN_AW7 GPIO0_D10 GPIO Expansion 0 IO 10 3 0 V PIN_AT5 GPIO0_D11 GPIO Expansi...

Page 40: ...GPIO1_D3 GPIO Expansion 1 IO 3 3 0 V PIN_AV10 GPIO1_D4 GPIO Expansion 1 IO 4 3 0 V PIN_AV8 GPIO1_D5 GPIO Expansion 1 IO 5 3 0 V PIN_AW10 GPIO1_D6 GPIO Expansion 1 IO 6 3 0 V PIN_AU10 GPIO1_D7 GPIO Expansion 1 IO 7 3 0 V PIN_AU8 GPIO1_D8 GPIO Expansion 1 IO 8 3 0 V PIN_AP8 GPIO1_D9 GPIO Expansion 1 IO 9 3 0 V PIN_AT10 GPIO1_D10 GPIO Expansion 1 IO 10 3 0 V PIN_AU6 GPIO1_D11 GPIO Expansion 1 IO 11 3...

Page 41: ...pansion 0 IO 0 Clock In 3 0 V or LVDS PIN_AF6 GPIO0_D1 GPIO Expansion 0 IO 1 3 0 V PIN_AU9 GPIO0_D2 GPIO Expansion 0 IO 2 Clock In 3 0 V or LVDS PIN_AE5 GPIO0_D3 GPIO Expansion 0 IO 3 3 0 V PIN_AR8 GPIO0_D4 GPIO Expansion 0 IO 4 3 0 V PIN_AN9 GPIO0_D5 GPIO Expansion 0 IO 5 3 0 V PIN_AP9 GPIO0_D6 GPIO Expansion 0 IO 6 3 0 V PIN_AV5 2 2 7 7 D DD DR R2 2 S SO O D DI IM MM M Two 200 pin DDR2 SO DIMM s...

Page 42: ...IN_AW34 M1_DDR2_DQ0 DDR Data 0 SSTL 18 Class I PIN_AV32 M1_DDR2_DQ5 DDR Data 5 SSTL 18 Class I PIN_AW33 M1_DDR2_DQ1 DDR Data 1 SSTL 18 Class I PIN_AV31 M1_DDR2_DM0 DDR2 Data Mask 0 SSTL 18 Class I PIN_AW31 M1_DDR2_DQS_n0 DDR2 Data Strobe n 0 Differential 1 8 V SSTL Class I PIN_AW30 M1_DDR2_DQS_p0 DDR2 Data Strobe p 0 Differential 1 8 V SSTL Class I PIN_AV29 M1_DDR2_DQ6 DDR Data 6 SSTL 18 Class I P...

Page 43: ...DQ20 DDR Data 20 SSTL 18 Class I PIN_AM23 M1_DDR2_DQ17 DDR Data 17 SSTL 18 Class I PIN_AP23 M1_DDR2_DQ21 DDR Data 21 SSTL 18 Class I PIN_AR23 M1_DDR2_DQS_n2 DDR2 Data Strobe n 2 Differential 1 8 V SSTL Class I PIN_AU24 M1_DDR2_DQS_p2 DDR2 Data Strobe p 2 Differential 1 8 V SSTL Class I PIN_AT24 M1_DDR2_DM2 DDR2 Data Mask 2 SSTL 18 Class I PIN_AU23 M1_DDR2_DQ18 DDR Data 18 SSTL 18 Class I PIN_AL22 ...

Page 44: ...J26 M1_DDR2_BA1 DDR2 Bank Address 1 SSTL 18 Class I PIN_AD25 M1_DDR2_BA0 DDR2 Bank Address 0 SSTL 18 Class I PIN_AH26 M1_DDR2_RAS_n DDR2 Row Address Strobe SSTL 18 Class I PIN_AE21 M1_DDR2_WE_n DDR2 Write Enable SSTL 18 Class I PIN_AK25 M1_DDR2_CS_n0 DDR2 Chip Select 0 SSTL 18 Class I PIN_AG21 M1_DDR2_CAS_n DDR2 Column Address Strobe SSTL 18 Class I PIN_AJ25 M1_DDR2_ODT0 DDR2 On Die Termination 0 ...

Page 45: ...for DDR2 Differential 1 8 V SSTL Class I PIN_AF20 M1_DDR2_DQS_n6 DDR2 Data Strobe n 6 Differential 1 8 V SSTL Class I PIN_AW13 M1_DDR2_DQS_p6 DDR2 Data Strobe n 6 Differential 1 8 V SSTL Class I PIN_AV13 M1_DDR2_DM6 DDR2 Data Mask 6 SSTL 18 Class I PIN_AU14 M1_DDR2_DQ50 DDR Data 50 SSTL 18 Class I PIN_AT14 M1_DDR2_DQ54 DDR Data 54 SSTL 18 Class I PIN_AU11 M1_DDR2_DQ51 DDR Data 51 SSTL 18 Class I P...

Page 46: ...lass I PIN_D13 M2_DDR2_DQ2 DDR Data 2 SSTL 18 Class I PIN_E14 M2_DDR2_DQ3 DDR Data 3 SSTL 18 Class I PIN_F14 M2_DDR2_DQ12 DDR Data 12 SSTL 18 Class I PIN_P16 M2_DDR2_DQ13 DDR Data 13 SSTL 18 Class I PIN_N16 M2_DDR2_DQ8 DDR Data 8 SSTL 18 Class I PIN_P17 M2_DDR2_DQ9 DDR Data 9 SSTL 18 Class I PIN_N17 M2_DDR2_DM1 DDR2 Data Mask 1 SSTL 18 Class I PIN_M17 M2_DDR2_DQS_n1 DDR2 Data Strobe n 1 Differenti...

Page 47: ...lass I PIN_G19 M2_DDR2_DQ31 DDR Data 31 SSTL 18 Class I PIN_G20 M2_DDR2_CKE0 Clock Enable pin 0 for DDR2 SSTL 18 Class I PIN_D11 M2_DDR2_CKE1 Clock Enable pin 1 for DDR2 SSTL 18 Class I PIN_K12 M2_DDR2_A15 DDR2 Address 15 SSTL 18 Class I PIN_M13 M2_DDR2_BA2 DDR2 Bank Address 2 SSTL 18 Class I PIN_B10 M2_DDR2_A14 DDR2 Address 14 SSTL 18 Class I PIN_K14 M2_DDR2_A12 DDR2 Address 12 SSTL 18 Class I PI...

Page 48: ...SSTL 18 Class I PIN_K24 M2_DDR2_DQ39 DDR Data 39 SSTL 18 Class I PIN_J24 M2_DDR2_DQ35 DDR Data 35 SSTL 18 Class I PIN_J25 M2_DDR2_DQ44 DDR Data 44 SSTL 18 Class I PIN_G24 M2_DDR2_DQ40 DDR Data 40 SSTL 18 Class I PIN_G25 M2_DDR2_DQ45 DDR Data 45 SSTL 18 Class I PIN_F24 M2_DDR2_DQ41 DDR Data 41 SSTL 18 Class I PIN_C25 M2_DDR2_DQS_n5 DDR2 Data Strobe n 5 Differential 1 8 V SSTL Class I PIN_E25 M2_DDR...

Page 49: ... 62 SSTL 18 Class I PIN_B29 M2_DDR2_DQ63 DDR Data 63 SSTL 18 Class I PIN_B31 M2_DDR2_SDA DDR2 I2C Data 1 8 V PIN_J15 M2_DDR2_SCL DDR2 I2C Clock 1 8 V PIN_K15 M2_DDR2_SA0 DDR2 Presence detect address input 0 1 8 V PIN_A18 M2_DDR2_SA1 DDR2 Presence detect address input 1 1 8 V PIN_B19 2 2 8 8 U US SB B O OT TG G The DE4 board provides both USB host and device interfaces using Philips ISP1761 single ...

Page 50: ...strations provide software drivers for the Nios II processor Table 2 17 The default host or peripheral setting for port 1 of the ISP1761 SW4 Setting Connectors ON Port 1 set to host OFF Port 1 set to device Table 2 18 USB 2 0 OTG Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description I O Standard Stratix IV GX Pin Number OTG_A1 OTG Address 1 1 8 V PIN_K26 OTG_A2 OTG...

Page 51: ...OTG_D9 OTG Data 9 1 8 V PIN_AG18 OTG_D10 OTG Data 10 1 8 V PIN_AG19 OTG_D11 OTG Data 11 1 8 V PIN_AM19 OTG_D12 OTG Data 12 1 8 V PIN_AN19 OTG_D13 OTG Data 13 1 8 V PIN_AV16 OTG_D14 OTG Data 14 1 8 V PIN_AT17 OTG_D15 OTG Data 15 1 8 V PIN_AV17 OTG_D16 OTG Data 16 1 8 V PIN_AU17 OTG_D17 OTG Data 17 1 8 V PIN_AW18 OTG_D18 OTG Data 18 1 8 V PIN_AT18 OTG_D19 OTG Data 19 1 8 V PIN_AU18 OTG_D20 OTG Data ...

Page 52: ...est acknowledgement 1 8 V PIN_AH20 USB_12MHZ OTG CLK input PSW1 Power Switch for port 1 DM1 Downstream data minus port 1 DP1 Downstream data plus port 1 USB_ID ID input to detect the default PSW2 Power Switch for port 2 DM2 Downstream data minus port 2 DP2 Downstream data plus port 2 PSW3 Power Switch for port 3 DM3 Downstream data minus port 3 DP3 Downstream data plus port 3 2 2 9 9 S SD D C Ca a...

Page 53: ...8 V PIN_AU20 E_SD_CMD Command for SD 1 8 V PIN_AV20 2 2 1 10 0 C Cl lo oc ck k C Ci ir rc cu ui it tr ry y Stratix IV GX FPGA Clock Inputs and Outputs The DE4 development board contains three types of clock inputs which include 16 global clock inputs pins external PLL clock inputs and transceiver reference clock inputs The clock input sources of the Stratix IV GX FPGA originate from two on board o...

Page 54: ...DE4 User Manual 54 www terasic com June 20 2018 ...

Page 55: ...In addition there are a total of 8 PLLs available for the Stratix IV GX device Table 2 21 Dedicated Clock Input Pins Dedicated Clock Input Pins HSMA_CLKIN_p1 differential HSMA_CLKIN_n1 differential HSMA_CLKIN0 OSC_50_B2 OSC_50_B5 OSC_50_B6 HSMB_CLKIN0 The dedicated clock input pins from the clock input multiplexer allow users to use any of these clocks as a source clock to drive the Stratix IV PLL...

Page 56: ...e connector The clock frequency for the programmable clock generators can be specified by using the DE4 control panel DE4 system builder or the external clock generator demo provided Note that signals PLL_CLKIN and SATA_REFCLK share the same clock generator which would lead to the same output frequency for both signals The associated pin assignments for clock buffer and SMA connectors to FPGA I O ...

Page 57: ... slot Utilizing built in transceivers on a Stratix IV GX device it is able to provide a fully integrated PCI Express compliant solution for multi lane x1 x4 and x8 applications With the PCI Express hard IP block incorporated in the Stratix IV GX device it will allow users to implement simple and fast protocol as well as saving logic resources for logic application Figure 2 24 presents the pin conn...

Page 58: ...1 4 V PCML PIN_AT37 PCIE_TX_p1_NET Add in card transmit bus 1 4 V PCML PIN_AP36 PCIE_TX_n1_NET Add in card transmit bus 1 4 V PCML PIN_AP37 PCIE_TX_p2_NET Add in card transmit bus 1 4 V PCML PIN_AH36 PCIE_TX_n2_NET Add in card transmit bus 1 4 V PCML PIN_AH37 PCIE_TX_p3_NET Add in card transmit bus 1 4 V PCML PIN_AF36 PCIE_TX_n3_NET Add in card transmit bus 1 4 V PCML PIN_AF37 PCIE_TX_p4_NET Add i...

Page 59: ... card receive bus 1 4 V PCML PIN_R39 PCIE_REFCLK_p Motherboard reference clock HCSL PIN_AN38 PCIE_REFCLK_n Motherboard reference clock HCSL PIN_AN39 PCIE_PREST_n Reset 2 5 V PIN_V30 PCIE_SMBCLK SMB clock 2 5 V PIN_R31 PCIE_SMBDAT SMB data 2 5 V PIN_W33 PCIE_WAKE_n Wake signal 2 5 V PIN_U35 PCIE_PRSNT1n Hot plug detect PCIE_PRSNT2n_x1 Hot plug detect x1 PCIe slot enabled using SW9 dip switch PCIE_P...

Page 60: ... transceiver devices The device is an auto negotiating Ethernet PHY with a default SGMII MAC interface The Marvell device is power by 2 5V and 1 1V power rails and also requiring a 25MHz reference clock driven from a dedicated 25MHz oscillator The transmitter and receiver signals of the Marvell device are connected directly to the LVDS I Os of the Stratix IV GX device with speeds at 1 2Gbps The in...

Page 61: ...ause 0 Default Register 4 11 10 to 00 ANEG 3 0 Auto negotiation configuration for copper modes 1110 Auto neg advertise all capabilities prefer master ENA_XC Enable Crossover 0 Disable DIS_125 Disable 125MHz clock 1 Disable 125CLK HWCFG 3 0 Hardware Configuration Mode 0100 SGMII without clock with SGMII Auto Neg to copper DIS_FC Disable fiber copper interface 1 Disable DIS_SLEEP Energy detect 1 Dis...

Page 62: ... PIN_R32 ETH_TX_n1 TX data LVDS PIN_R33 ETH_RX_p1 RX data LVDS PIN_N33 ETH_RX_n1 RX data LVDS PIN_N34 ETH_MDC1 Management bus control 2 5 V PIN_J6 ETH_MDIO1 Management bus data 2 5 V PIN_J5 ETH_INT_n1 Management bus interrupt 2 5 V PIN_AG30 ETH_RST_n Device reset 2 5 V PIN_V29 Ethernet 2 ETH_TX_p2 TX data LVDS PIN_M32 ETH_TX_n2 TX data LVDS PIN_L32 ETH_RX_p2 RX data LVDS PIN_K34 ETH_RX_n2 RX data ...

Page 63: ... in storage appliances The Stratix IV GX device can bridge different protocols such as bridging simple bus I Os like PCI Express PCIe to SATA or network interfaces such as Gigabit Ethernet GbE to SATA The SATA interface supports SATA 3 0 standard with connection speed of 6 Gbps based on Stratix IV GX device with integrated transceivers compliant to SATA electrical standards The four Serial ATA SAT...

Page 64: ...nnected directly to the Stratix IV GX transceiver channels to provide SATA IO connectivity to both host and target devices To verify the functionality of the SATA host device ports a connection can be established between the two ports by using a SATA cable as Figure 2 28 depicts the associated signals connected Table 2 27 lists the SATA pin assignments signal names and functions ...

Page 65: ... DC blocking capacitor 1 4 V PCML PIN_AT3 SATA_DEVICE_TX_p0 Differential transmit data output before DC blocking capacitor 1 4 V PCML PIN_AT4 SATA_DEVICE_RX_p1 Differential receive data input after DC blocking capacitor 1 4 V PCML PIN_AJ2 SATA_DEVICE_RX_n1 Differential receive data input after DC blocking capacitor 1 4 V PCML PIN_AJ1 SATA_DEVICE_TX_n1 Differential transmit data output before DC bl...

Page 66: ...on how to use the transceiver refer to the datasheet which is available on the manufacturer s website or in the Datasheet RS232 folder on the DE4 System CD ROM Table 2 28 lists the RS 232 pin assignments signal names and functions Table 2 28 RS 232 Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description I O Standard Stratix IV GX Pin Number UART_TXD Receiver Output 2...

Page 67: ...N_G22 FSM_A2 Address bus 2 5 V PIN_G23 FSM_A3 Address bus 2 5 V PIN_A25 FSM_A4 Address bus 2 5 V PIN_H22 FSM_A5 Address bus 2 5 V PIN_H23 FSM_A6 Address bus 2 5 V PIN_J22 FSM_A7 Address bus 2 5 V PIN_K22 FSM_A8 Address bus 2 5 V PIN_M21 FSM_A9 Address bus 2 5 V PIN_J23 FSM_A10 Address bus 2 5 V PIN_F34 FSM_A11 Address bus 2 5 V PIN_G35 FSM_A12 Address bus 2 5 V PIN_E34 FSM_A13 Address bus 2 5 V PI...

Page 68: ...t 2 2 1 16 6 S SS SR RA AM M M Me em mo or ry y The IS61NVP102418 Synchronous Static Random Access Memory SSRAM device featured on the DE4 development board is part of the shared FMS Bus which connects to flash memory SSRAM and the MAX II CPLD EEPM2210 System Controller This device is a Zero bus turnaround ZBT 2MB SRAM device with a 16 bit data bus providing no bus latency synchronous burst SRAM w...

Page 69: ...M_D0 Data bus 2 5 V PIN_K29 FSM_D1 Data bus 2 5 V PIN_J30 FSM_D2 Data bus 2 5 V PIN_K30 FSM_D3 Data bus 2 5 V PIN_L29 FSM_D4 Data bus 2 5 V PIN_K31 FSM_D5 Data bus 2 5 V PIN_E32 FSM_D6 Data bus 2 5 V PIN_F32 FSM_D7 Data bus 2 5 V PIN_H32 FSM_D8 Data bus 2 5 V PIN_B32 FSM_D9 Data bus 2 5 V PIN_C32 FSM_D10 Data bus 2 5 V PIN_C35 FSM_D11 Data bus 2 5 V PIN_D35 FSM_D12 Data bus 2 5 V PIN_M22 FSM_D13 D...

Page 70: ... en ns so or r The DE4 is quipped with a temperature sensor MAX1619 which provides temperature sensing and over temperature alert These functions are accomplished by connecting the temperature sensor to the internal temperature sensing diode of the Stratix IV GX device The temperature status and alarm threshold registers of the temperature sensor can be programmed by a two wire SMBus which is conn...

Page 71: ...rs connect the PCIe external power connector to the DE4 when either the HSMC or GPIO interface is occupied by a daughter card The DC voltage is stepped down to various power rails used by the components on the board and installed into the HSMC connectors Power Switch The slide switch SW5 is the board power switch for the DC power input When the slide switch is in the ON position the board is power...

Page 72: ...gnal Name Voltage Description 0 GPIO_VCCIOPD 3 0 V Bank 5A 5C IO Pre Driver 1 HSMA_VCCIO 2 5 V Bank 2A 2C IO power HSMC port A 2 HSMB_VCCIO 2 5 V Bank 6A 6C IO power HSMC port B 3 VCC1P8 1 8 V Bank 3A 3B 3C 4A 4B 4C IO power 4 VCC1P8 1 8 V Bank 7A 7B 7C 8A 8B 8C IO power 5 VCC0P9 0 9 V FPGA core and periphery power 6 VCCHIP 0 9 V PCI Express hard IP block 7 VCCA_PLL 2 5 V PLL analog power 8 VCCD_P...

Page 73: ...DE4 User Manual 73 www terasic com June 20 2018 11 VCC3P3_HSMC 3 3 V HSMC power HSMC ports A and B ...

Page 74: ...the program simply copy the whole folder to your host computer and launch the control panel by double clicking the DE4_ControlPanel exe Note Please make sure Quartus II and USB Blaster Driver are installed before launching DE4 Control Panel In addition before the DE4 control panel is launched it is imperative the fan is installed on the Stratix IV GX device to prevent excessive high temperature on...

Page 75: ... is programmed to the DE4 board the FPGA device information will be displayed on the window Note the Control Panel will occupy the USB port users will not be able to download any configuration file into the FPGA before you exit the Control Panel program The Control Panel is now ready as shown in Figure 3 2 Figure 3 1 Download sof files to the DE4 board ...

Page 76: ... Panel is ready If the connection between DE4 board and USB Blaster is not established or the DE4 board is not powered on before running the DE4_ControlPanel exe the Control Panel will fail to detect the FPGA and a warning message window will pop up as shown in Figure 3 3 ...

Page 77: ...re 3 4 The Control Codes which performs the control functions is implemented in the FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical users interface is used to issue commands to the control codes It handles all requests and performs data transfer between the computer and the DE4 board ...

Page 78: ...status read write from various memory types in addition to testing various components of the DE4 board 3 3 2 2 C Co on nt tr ro ol ll li in ng g t th he e L LE ED Ds s a an nd d 7 7 S Se eg gm me en nt t D Di is sp pl la ay ys s One of the functions of the Control Panel is to set up the status of the LEDs and 7 segment displays The tab window shown in Figure 3 5 indicates where you can directly tu...

Page 79: ...0 2018 individually by selecting them and clicking Light All or Unlight All Figure 3 5 Controlling LEDs Figure 3 6 shows the interface of the 7 SEG and how to select desired patterns The status of the 7 SEG patterns will be updated immediately ...

Page 80: ...SEG display 3 3 3 3 S SW WI IT TC CH H B BU UT TT TO ON N Choose the Button tab as shown in Figure 3 7 This function is designed to monitor status of switches and buttons from a graphic interface in real time It can be used to verify the functionality of switches and buttons ...

Page 81: ... the DE4 Control Panel We will describe how the DDR2 SO DIMM is accessed Click on the Memory tab to reach the tab window shown in Figure 3 8 A 16 bit value can be written into the DDR2 SO DIMM memory by three steps namely specifying the address of the desired location entering the hexadecimal data to be written and pressing the Write button Contents of the location can be read by pressing the Read...

Page 82: ...the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Sequential Read function is used to read the contents of the serial configuration device and place them into a file as follows Specify the starting address in the Address box Specify the number of bytes to be copied into a file in the Length box If the entire ...

Page 83: ...DE4 User Manual 83 www terasic com June 20 2018 Figure 3 8 Access DDR2 SO DIMM memory ...

Page 84: ...2 2 0 0 O OT TG G Choose the USB tab to reach the window in Figure 3 10 This function is designed to monitor the status of USB Host Hub in real time Plug a USB device to any USB port of FPGA board and both the device type and speed will be displayed on the control window Figure 3 10 shows a USB storage device plugged into port 3 ...

Page 85: ...This function is designed to read the identification and specification of SD Card 4 bit SD MODE is used to access the SD Card This function can be used to verify the functionality of SD CARD interface To gather the information simply insert a SD Card to the FPGA board and press the Read button The SD CARD identification and specification will be displayed on the control window ...

Page 86: ...ensor through Control Panel The temperatures of Stratix IV GX and DE4 board are shown on the right hand side of the Control Panel When the temperature of Stratix IV GX exceeds the maximum setting of Over Temperature or Alert a warning message will be shown on the Control Panel Click Read button to get current settings for Over temperature and Alert Users can enter the maximum and minimum temperatu...

Page 87: ...signed to monitor the power consumption in real time of various blocks on the DE4 board Using the 12 power supply rails on the DE4 we are able to sense the on board voltage and current for transceiver power Stratix IV GX power and the I O power Choose the Power tab to reach the window shown in Figure 3 13 which depicts all associated power banks of the DE4 board ...

Page 88: ...PLL on the DE4 There are 3 programmable clocks for the DE4 board that generates reference clocks for the following signals HSMA_REFCLK HSMB_REFCLK and PLL_CLKIN SATA_REFCLK The clock frequency can be adjusted to 62 5 75 100 125 150 156 25 187 5 200 250 312 5 and 625MHz Choose the PLL tab to reach the window shown in Figure 3 14 To set the desire clock frequency for the associated clock signal clic...

Page 89: ... 3 1 10 0 S SA AT TA A Choose the SATA tab to reach the window shown in Figure 3 15 This function is designed to verify the functionality of the transceiver signals found on the SATA interface using a loopback approach Before running the Loopback verification SATA test follow the Loopback Installation and click on Verify ...

Page 90: ...and B using a loopback approach Before running the loopback verification HSMC test select the desire HSMC connector to be tested on Follow the instruction noted under Loopback Installation section and click on Verify Please note to turn off the DE4 board before the HSMC loopback adapter is installed to prevent any damage to the DE4 board Note the Control Panel HSMC loopback test does not tests the...

Page 91: ...ion test performed under Control Panel 3 3 1 12 2 F Fa an n Choose the Fan tab to reach the window shown in Figure 3 17 This function is designed to verify the functionality of the fan components and signals Please make sure the Fan is installed on the DE4 before running this function ...

Page 92: ...DE4 User Manual 92 www terasic com June 20 2018 Figure 3 17 Fan Control of the DE4 ...

Page 93: ...ed Quartus II project files include Quartus II Project File qpf Quartus II Setting File qsf Top Level Design File v External PLL Contorller v Synopsis Design Constraints file sdc Pin Assignment Document htm The DE4 System Builder not only can generate the files above but can also provide error checking rules to handle situation that are prone to errors The common mistakes that users encounter are ...

Page 94: ...ct according to their design requirements When users complete the settings the DE4 System Builder will generate two major files which include top level design file v and the Quartus II setting file qsf The top level design file contains top level verilog wrapper for users to add their own design logic The Quartus II setting file contains information such as FPGA device type top level pin assignmen...

Page 95: ...ection provides the detail procedures on how the DE4 System Builder is used Install and launch the DE4 System Builder The DE4 System Builder is located in the directory Tools DE4_SystemBuilder in the DE4 System CD Users can copy the whole folder to a host computer without installing the utility Before using the DE4 System Builder execute the DE4_SystemBuilder exe on the host computer ...

Page 96: ...and Input Project Name Select the target board type and input project name as show in Figure 4 3 Board Type Select the appropriate FPGA device according to the DE4 board which includes the EP4SGX230 and EP4SGX530 devices Project Name Specify the project name as it is automatically assigned to the name of the top level design entity ...

Page 97: ...arking a check or removing the check in the field provided If the component is enabled the DE4 System Builder will automatically generate the associated pin assignments including the pin name pin location pin direction and I O standards Note The pin assignments for some components for e g DDR2 and SATA require associated controller codes in the Quartus project otherwise Quartus will result in comp...

Page 98: ...LLs users can select the desired frequency on the Programmable PLL group as show in Figure 4 5 As the Quartus project is created System Builder automatically generates the associated PLL configuration code according to users desired frequency in verilog which facilitates users implementation as no additional control code is required to configure the PLLs Note If users need to dynamically change th...

Page 99: ...er card you wish to add to your design under the appropriate GPIO header where the daughter card is connected to The system builder will automatically generate the associated pin assignment including the pin name pin location pin direction and IO standard If a customized daughter board is used users can select GPIO Default followed by changing the pin name pin direction and IO standard according t...

Page 100: ...ature which denotes the pin name of the daughter card assigned in your design Users may leave this field empty Note If the same GPIO expansion card is selected under GPIO 0 and GPIO 1 a prefix name is required to avoid pin name duplication as shown in Figure 4 7 otherwise System Builder will prompt an error message ...

Page 101: ...ate HSMC connector where the daughter card is connected to The System Builder will automatically generate the associated pin assignment including pin name pin location pin direction and IO standard If a customized daughter board is used users can select HSMC Default followed by changing the pin name pin direction and IO standard according to the specification of the customized daughter board If tr...

Page 102: ... that denotes the pin name of the daughter card assigned in your design Users may leave this field empty Note if the same HSMC daughter card is selected in both HSMC A and HSMC B expansion a prefix name is required to avoid pin name duplication as shown in Figure 4 9 otherwise System Builder will prompt an error message ...

Page 103: ...Board Project Setting Management The DE4 System Builder also provides functions to restore default setting loading a setting and saving users board configuration file shown in Figure 4 10 Users can save the current board configuration information into a cfg file and load it to the DE4 System Builder ...

Page 104: ...he Table 4 1 in the directory specified by the user Table 4 1 The files generated by DE4 System Builder No Filename Description 1 Project name v Top level verilog file for Quartus II 2 EXT_PLL_CTRL v External PLL configuration controller IP 3 Project name qpf Quartus II Project File 4 Project name qsf Quartus II Setting File 5 Project name sdc Synopsis Design Constraints file for Quartus II 6 Proj...

Page 105: ...below ext_pll_ctrl ext_pll_ctrl_Inst osc_50 OSC_50_BANK2 50MHZ rstn rstn device 1 HSMA_REFCLK clk1_set_wr clk1_set_wr clk1_set_rd device 2 HSMB_REFCLK clk2_set_wr clk2_set_wr clk2_set_rd device 3 PLL_CLKIN SATA_REFCLK clk3_set_wr clk3_set_wr clk3_set_rd setting trigger conf_wr conf_wr 1T 50MHz conf_rd 1T 50MHz status conf_ready conf_ready 2 wire interface max_sclk MAX_I2C_SCLK max_sdat MAX_I2C_SDA...

Page 106: ...s of the DE4_demonstrations de4_ Stratix_device folder 5 5 1 1 U US SB B H Ho os st t USB Universal Serial Bus is a well known communication standard used in many peripherals The DE4 board provides a complete USB solution for both host and device applications In this demonstration USB host functions are implemented for USB mass storage and Human interface devices HIDs including a USB Mouse The dri...

Page 107: ...nterrupts of the USB chip A PIO pin named usb_reset_n is connected to the USB for performing hardware reset of the USB chip The NIOS II program is stored in the On Chip Memory Figure 5 1 Hardware block diagram of the USB Host demonstration Nios II Software Architecture Figure 5 2 shows the architectural layers of a NIOS II software stack of this demonstration ...

Page 108: ...The ISP 1761 HAL block implements functions to access internal registers and memories of the USB chip ISP 1761 and high full low speed transfer functions for isochronous interrupt control and bulk transfers USB Host Controller The USB host controller block implements control functions for ISP1761 host controller USB Protocol The USB protocol block implements USB protocol including USB Hub protocol...

Page 109: ...in Figure 5 3 The standard output of this program is JTAG UART In the demo batch file the output message will be display in nios2 terminal When the program detects an USB mass storage device it will list the files in root directory If a file named test txt is found the program will dump the file contents When an HID USB Mouse is detected the program will poll the mouse status continuously and disp...

Page 110: ...DE4 User Manual 110 www terasic com June 20 2018 Figure 5 3 Software workflow of the USB Host demonstration ...

Page 111: ...oject directory DE4_USB FPGA Bit Stream DE4_USB sof NIOS II Workspace DE4_USB Software Project_Usb_Host The NIOS II source code list is shown in Figure 5 4 Users can modify terasic_debug h to configure the debug message Note the debug message may affect the USB performance and possibly cause malfunction to the demonstration ...

Page 112: ...er ISP1761 HAL Hardware Abstration Layer Host Controller USB Protocol Main Figure 5 4 Source code list of the USB Host demonstration Nios II IDE Project Compilation Before you attempt to compile the reference design under Nios II IDE make sure the project is cleaned first from the Project menu of Nios followed by Clean ...

Page 113: ... the three USB ports will be light after USB ports are configured completed For USB mass storage demonstration copy test files to the root directory of USB Disk Plug USB mass storage device or HID USB Mouse into the USB ports in DE4 as shown in Figure 5 5 The device information will be displayed in nios2 terminal as shown in Figure 5 6 Reference ISP1761 Hi Speed Universal Bus On The Go controller ...

Page 114: ...ual 114 www terasic com June 20 2018 Universal Serial Bus Device Class Definition for Human Interface Devices HID Version 1 11 June 27 2001 Figure 5 5 Plug USB Devices into DE4 Figure 5 6 Display device information ...

Page 115: ...uter The NIOS II processor communicates with host computer through USB Bulk Transfer with user defined command sets The USB device driver is implemented in NIOS C code From the host computer side a test program is used to communicate with DE4 The test program can configure LED status and poll button status through the USB connection Nios II Software Architecture The hardware system block diagram o...

Page 116: ...B Protocol The USB protocol block implements USB protocol including USB Hub protocol USB Bulk Driver The USB bulk driver implements a device driver to provide two bulk end points namely Bulk In and Bulk Out Main the main block is implemented to communicate with a host computer It calls bulk read functions to receive commands from the host computer and calls bulk write function to return data to th...

Page 117: ...on Source Code Quartus Project directory DE4_USB FPGA Bit Stream DE4_USB sof NIOS II Workspace DE4_USB Software Project_Usb_Device The NIOS II source code list is shown in Figure 5 9 Users can modify terasic_debug h to configure the debug message Note that any debug message may affect the USB performance or even cause malfunction in this demonstration ...

Page 118: ...le the reference design under Nios II IDE make sure the project is cleaned first from the Project menu of Nios followed by Clean Demonstration Batch File Demo Batch File Folder DE4_USB demo_batch usb_device The demo batch file includes the following files Batch File test bat test_bashrc FPGA Configure File DE4_USB sof NIOS II Program usb_device elf USB Driver for Windows XP terasic_usb sys and ter...

Page 119: ... USB port of the host computer is connected to the mini AB port of the DE4 board a dialog will pop up to request a USB driver to be installed The required driver is available in the demo batch folder DE4_USB demo_batch usb_device Launch Terasic_UsbControl exe under the batch file folder DE4_USB demo_batch usb_device Click Connect in DE4_UsbControl window After connection established the button sta...

Page 120: ...reate a simple socket server generated in Nios II using the Gigabit Ethernet devices equipped on the DE4 board As indicated in the block diagram in Figure 5 11 the Nios II processor is used to communicate with the client via Marvell 88E1111 Ethernet Transceiver Figure 5 11 Block diagram of the Ethernet demonstration Part of Nios II NicheStack TCP IP Network Stack is a software suite of networking ...

Page 121: ...tains an Ethernet interface or media access control MAC How the Ethernet demonstration is built In this following section we describe how to build the demonstration through the SOPC builder The SOPC system includes the CPU processor On Chip memory JTAG UART system ID timer Triple Speed Ethernet Scatter Gather DMA Controllers and peripherals which are linked together contained in the Nios II hardwa...

Page 122: ...ock frequency is 100 MHz and the desired MDC clock frequency is 2 5 MHz a host clock divisor of 40 should be used Once the Triple Speed Ethernet IP configuration has been set and necessary hardware connections has been made click on Generate to build the interconnect logic automatically In this following section we will describe the steps to create the Simple Socket Server using Nios II We create ...

Page 123: ... default the MAC interface for the Ethernet device is set to SGMII In this demonstration we are using SGMII MAC interface which can be configured through the management interface of the 88E1111 Ethernet device Once the link is established an IP address is assigned to the Ethernet device along with the port number Through TCP and port number the demonstration uses Telnet client to establish connect...

Page 124: ...thernet and other hardware components to functions The HAL API block provides the interface for the software device drivers while the MicroC OS II provdes communication services to the NichStack and the Simple Socket Server The NicheStack TCP IP stack software block provides networking services to the application where it contains tasks for Simple Socket Server and also LED management Figure 5 15 ...

Page 125: ...lder DE4_Simple_Socket_Server de4_ Stratix device _ethernet_test_batch demo_batch_ Ethernet port The demo batch file folders include the following files Batch File de4_net bat de4_net_bashrc open_telnet bat FPGA Configuration File DE4_Ethernet sof NIOS II Program simple_socket_server elf Demonstration Setup Make sure Quartus II and NIOS II are installed Power on DE4 Connect USB cable to DE4 The PC...

Page 126: ... Simple socket server To establish connection start the telnet client session by executing open_telnet bat file and include the IP address assigned by the DHCP server provided IP along with the port number as shown below in Figure 5 17 Figure 5 17 Telnet Client ...

Page 127: ...hardware and software needed for SD card access In this demonstration we will show how to browse files stored in the root directory of a SD card and how to read the file contents of a specific file The SD card is required to be formatted as FAT File System in advance Long file name is supported in this demonstration Figure 5 18 shows the hardware system block diagram of this demonstration The syst...

Page 128: ...ng filename is supported By calling the exported FAT functions users can browse files under the root directory of the SD card Furthermore users can open a specified file and read the contents of the file The main block implements main control of this demonstration When the program is executed it detects whether a SD card is inserted If a SD card is found it will check whether the SD card is format...

Page 129: ...SDCARD sof NIOS II Workspace DE4_SDCARD Software Nios II IDE Project Compilation Before you attempt to compile the reference design under Nios II IDE make sure the project is cleaned first from the Project menu of Nios followed by Clean Demonstration Batch File Demo Batch File Folder DE4_SDCARD Demo_Batch The demo batch file includes following files Batch File test bat test_bashrc FPGA Configure F...

Page 130: ...nder the batch file folder DE4_SDCARD demo_batch After NIOS II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal Copy test files text txt created by the user to the root directory of the SD Card Insert the SD card into the SD Card socket of DE4 as shown in Figure 5 20 Press Button3 of the DE4 board to start reading SD Card The program will display...

Page 131: ...e Controller IP is used to create a DDR2 SDRAM controller and how NIOS processor is used to read and write the SDRAM for hardware verification The DDR2 SDRAM controller handles the complex aspects of using DDR2 SDRAM by initializing the memory devices managing SDRAM banks and keeping the devices refreshed at appropriate intervals The required DDR2 SDRAM SODIMM module should be at least 1G Bytes DD...

Page 132: ...controlled by a NIOS program First the NIOS program writes test patterns into the whole 1GBytes SDRAM Then it calls NIOS system function alt_dache_flush_all to make sure all data has been written to SDRAM Finally it reads data from SDRAM for data verification The program will show progress in JTAG Terminal when writing reading data to from the SDRAM When verification process is completed the resul...

Page 133: ...sign Tools Quartus II NIOS II IDE Demonstration Source Code Project directory DE4_DDR2 Bit stream used DE4_DDR2 sof NIOS II Workspace DE4_DDR2 Software Nios II IDE Project Compilation Before you attempt to compile the reference design under Nios II IDE make sure the project is cleaned first from the Project menu of Nios followed by Clean Demonstration Batch File Demo Batch File Folder DE4_DDR2 dem...

Page 134: ...r if necessary Execute the demo batch file test bat under the batch file folder DE4_DDR2 demo_batch dim1 or DE4_DDR2 demo_batch dim2 After NIOS II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal Press Button3 Button0 of the DE4 board to start SDRAM verify process Press Button0 for continued test and Ctrl C to terminate the test The program will ...

Page 135: ...us connected to the MAX II EPM2210 device This can reduce the Stratix IV GX I O usage while enabling greater functionality on the FPGA device The MAX II EPM2210 device is capable of storing the last entered clock settings at which in the event the board restarts the last known clock settings are fully restored In this demonstration we illustrate how to utilize the clock generators IP to define the...

Page 136: ...he same clock frequency applied to the PLL_CLKIN signal At this stage any arbitrary changes to the PLL_CLKIN is not allowed as users can only change the PLL_CLKIN clock frequency if the SATA interface is not in use The I O standard for the three clock generators is set as LVDS which is non configurable An overall block diagram of the external clock generator is shown below in Figure 5 25 ...

Page 137: ...The EXT_PLL_CTRL IP Port Description This section describes the operation for the EXT_PLL_CTRL instruction hardware port Figure 5 26 shows the EXT_PLL_CTRL instruction block diagram connected to the MAX II EPM2210 device The EXT_PLL_CTRL controller module is defined by a host device the Stratix IV GX ...

Page 138: ...L_CTRL Instruction Hardware Ports Table 5 1 EXT_PLL_CTRL instruction ports Port Name Direction Description osc_50 input System Clock 50MHz rstn input Synchronous Reset 0 Module Reset 1 Normal clk1_set_wr clk2_set_wr clk3_set_wr input Setting Output Frequency Value clk1_set_rd clk2_set_rd clk3_set_rd output Read Back Output Frequency Value conf_wr input Start to Transfer Serial Data postive edge co...

Page 139: ...4 b1000 187 4 b1001 200 4 b1010 250 4 b1011 312 5 4 b1100 625 others x Setting Unchanged The EXT_PLL_CTRL IP Timing Diagram In this reference design the output frequency is set to 62 5 75 and 100 MHz with the following timing diagrams illustrated below When the EXT_PLL_CTRL IP receives the conf_wr signal the user needs to define clk1_set_wr clk2_set_wr and clk3_set_wr to set the External Clock Gen...

Page 140: ...te the conf_ready signal returns back to original state at high level Figure 5 27 Write timing waveform Read Timing Waveform As Button1 PB2 is pressed the conf_rd signal is on the rising edge the user settings are read back immediately once the conf_ready signal is on the falling edge as shown in Figure 5 28 As the transfer is complete the conf_ready returns back to original state at high level ...

Page 141: ...urce Code Project directory DE4_EXT_PLL Bit stream used DE4_EXT_PLL sof Demonstration Batch File Demo Batch File Folder DE4_EXT_PLL demo_batch The demo batch file folders include the following files Batch File test bat FPGA Configuration File DE4_EXT_PLL sof Demonstration Setup Make sure Quartus II is installed on your PC ...

Page 142: ...th sense resistors to measure the small voltage drop across the resistors The ADCs is connected to the FPGA via serial peripheral interface SPI bus This demonstration uses an embedded NIOS II processor to read the voltage drop value from the ADC through the SPI interface Based on the voltage drop values and sense resistors the program can calculate the associated current and power consumption The ...

Page 143: ...s its internal oscillator and the digital filter first null is located at 60Hz The clock source in SPI transition is configured as External Serial Clock Operation mode by keeping the SCK pin to low at the falling edge of CS pin ADC SPI Transmission Figure 5 30 shows the data timing for SPI transmission The SDI signal is used to serialize data from the FPGA to ADC and the SDO signal is used to seri...

Page 144: ...he FPGA retrieves the conversion result from the serialized data through the SDO pin Note the conversion data is for the target channel specified by previous configuration When ADC is powered on the default selection used for the first conversion is IN CH0 and IN CH1 Address 00000 Design Tools Quartus II NIOS II IDE Demonstration Source Code Project directory DE4_PowerMeasure Bit stream used DE4_P...

Page 145: ...easure elf Demonstration Setup Make sure Quartus II and NIOS II are installed on your PC Power on the DE4 board Connect USB Blaster to the DE4 board and install USB Blaster driver if necessary Execute the demo batch file test bat under the batch file folder DE4_PowerMeasure demo_batch After NIOS II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal...

Page 146: ... includes controlling the LED lights 7 segment display and fan control As Part of the Nios II NicheStack TCP IP Network Stack is a software suite of networking protocols designed to provide an optimal solution for designing network connected embedded devices with the Nios II processor Before you begin to study this demo we assume that you already have a basic knowledge of PHY and MAC In this case ...

Page 147: ...ding to the users the MDIO module that controls the PHY Management Module is included associated with the MAC block as shown Figure 5 33 The host Clock divisor is to divide the MAC control register interface clock to produce the MDC clock output on the MDIO interface The MAC control register interface clock frequency is 100 MHz and the desired MDC clock frequency is 2 5 MHz so a host clock divisor...

Page 148: ...148 www terasic com June 20 2018 Figure 5 33 MAC Options Configuration From the PCS SGMII Options section enable SGMII bridge logic to add SGMII clock and rate adaptation logic to the PCS block as shown in Figure 5 34 ...

Page 149: ...igure 5 34 PCS SGMII Options Configuration Once the Triple Speed Ethernet IP configuration has been completed and the necessary hardware connections have been made click on Generate to build the interconnect logic automatically as shown in Figure 5 35 ...

Page 150: ...DE4 User Manual 150 www terasic com June 20 2018 Figure 5 35 SOPC builder ...

Page 151: ...the Nios II processor and the necessary hardware to be implemented into the DE4 host board The software device drivers contain the necessary device drivers needed for the Ethernet and other hardware components to work The HAL API block provides the interface for the software device drivers while the Micro C OS II provides communication services to the NicheStack and Web Server The NicheStack TCP I...

Page 152: ...cast their transmission parameters speed and duplex mode After the auto negotiation process has finished it will establish the link Thirdly the Web Server program will prepare the transmitting and receiving path for the link If the path is created successfully it will call the get_ip_addr function to set up the IP address for the network interface After the IP address is successfully distributed T...

Page 153: ...n ns st tr ru uc ct ti io on ns s The Following steps describe how to setup a Web Server demonstration on the ETHERNET0 in SGMII mode Project directory DE4_board_update_portal Nios II Project workspace de4_board_update_portal software Web_Server Bit stream used DE4_board_update_portal sof Web site content zip file ro_zipfs zip de4_board_update_portal software Web_Server web_server_syslib ro_zipfs ...

Page 154: ... your web browser Use Internet Explorer 7 0 or later Input the IP into your browser You will see the brand new DE4 web page on your computer illustrated in Figure 5 39 Nios II IDE Project Compilation Before you attempt to compile the reference design under Nios II IDE make sure the project is cleaned first from the Project menu of Nios followed by Clean Figure 5 39 DE4 Webserver IE Window ...

Page 155: ...ror condition If there are zero errors LED 3 0 are illuminated By default the test is run at 6 Gbps Demonstration Source Code Quartus Project directory DE4_SATA_LOOPBACK_TEST FPGA Bit stream DE4_SATA_LOOPBACK_TEST sof Demonstration Setup Check that Quartus II and NIOS II are installed on your PC Make sure a SATA cable provided in the DE4 package is connected between SATA host A and SATA device A S...

Page 156: ...ay to implement your own design utilizing the transceiver signals situated on the HSMC interface This design also helps you verify the transceiver signals functionality for ports A and B of the HSMC interface A total of 8 transceiver pairs on the HSMC port B are tested while a total of 4 transceiver pairs are tested on HSMC port A H HS SM MC C P Po or rt t A A L Lo oo op pb ba ac ck k T Te es st t...

Page 157: ... the HSMC loopback daughter card onto the HSMC port A Power on the DE4 board Connect USB Blaster to the DE4 board and install USB Blaster driver if necessary Program the DE4 using the DE4_HSMA_LOOPBACK_TEST sof through Quaruts II programmer Press RESET pushbutton 0 of the DE4 board to initiate the verify process LED 3 0 will flash once indicating the loopback test passed Figure 5 41 HSMC port A lo...

Page 158: ...nect USB Blaster to the DE4 board and install USB Blaster driver if necessary Program the DE4 using the DE4_HSMB_LOOPBACK_TEST sof through Quaruts II programmer Press RESET pushbutton 0 of the DE4 board to initiate the verify process LED 7 0 will flash once to indicate the loopback test passed 5 5 1 11 1 P PC CI Ie e D De em mo on ns st tr ra at ti io on n For PCIe demonstrations please go to down...

Page 159: ...Dist Hsinchu City Taiwan 30070 Email support terasic com Web www terasic com DE4 Web de4 terasic com R Re ev vi is si io on n H Hi is st to or ry y Date Version Changes 2010 7 First publication 2010 8 V1 1 PCIe Driver Installation Modified 2012 3 V1 2 PCIe Driver support 64 bit Windows 2015 01 V1 3 Udpate FPGA embeded ram size 2017 03 V1 4 Modify PCIE demo 2018 06 V1 5 Remove PCIE chapter PCIe dem...

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