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Samsung S3C2451X, User Manual

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Preliminary

S3C2451X RISC MICROPROCESSOR

 

 

 NAND FLASH CONTROLLER 

 

 

7

-13 

Preliminary product information describe products that are in development,

 

for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.

7.13.2 NAND FLASH CONFIGURATION REGISTER 

Register 

Address 

R/W 

Description 

Reset Value

NFCONF 

0x4E000000

R/W 

NAND Flash Configuration register 

0xX000100X

 

NFCONF 

Bit 

Description 

Initial State 

Reserved [31] 

Reserved 

0 

Reserved [30] 

Should be 0 

0 

Reserved [29:26] 

Reserved 

0000 

MsgLength [25] 

Message (Data) length for 4/8 bit ECC 

0: 512-byte                               1: 24-byte 

0 

ECCType [24:23] 

This bit indicates what kind of ECC should be used. 

00: 1-bit ECC   

10: 4-bit ECC 

01 : 8-bit ECC 

Note. Don’t confuse the value of 4-bit ECC and 8-bit 
ECC.  

H/W Set 

(CfgBootEcc) 

Reserved [22:15] 

Reserved 

000000000 

TACLS [14:12] 

CLE & ALE duration setting value (0~7) 

Duration =  HCLK x TACLS 

001 

Reserved [11] 

Reserved 

0 

TWRPH0 [10:8] 

TWRPH0 duration setting value (0~7) 

Duration =  HCLK x ( 1 ) 

000 

Reserved [7] 

Reserved 

0 

TWRPH1 [6:4] 

TWRPH1 duration setting value (0~7) 

Duration =  HCLK x ( 1 ) 

000 

PageSize [3] 

This bit indicates the page size of NAND Flash Memory  

When PageSize_Ext is 1, the value of PageSize means 
following: 

0: 512 Bytes/page, 

1: 2048 Bytes/page 

When PageSize_Ext is 0, the value of PageSize means 
following: 

0: 2048 Bytes/page, 

1: 4096 Bytes/page

 

H/W Set 

(CfgAdvFlash) 

PageSize_Ext 

[2] 

This bit indicated what kind of  NAND Flash memory is used. 

0: Large Size NAND Flash  

1: Small Size NAND Flash 

This bit is determined by OM[2] pin status on reset and 

wake-up time from sleep mode. 

1 

Summary of Contents for S3C2451X

Page 1: ... l i m i n a r y USER S MANUAL S3C2451X RISC Microprocessor June 11 2008 Preliminary REV 0 10 Confidential Proprietary of Samsung Electronics Co Ltd Copyright 2008 Samsung Electronics Inc All Rights Reserved ...

Page 2: ...sung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such uninten...

Page 3: ...NUAL_PRELIMINARY_REV 0 10 iii Revision History Revision No Description of Change Refer to Author s Date 0 00 Initial Release Preliminary AP app part May 26 2008 0 10 Overview DRAMC IOport TSADC Electrical Data updated AP app part June 11 2008 ...

Page 4: ...P r e l i m i n a r y iv S3C2451X_USER S MANUAL_REV 0 10 NOTES ...

Page 5: ... 16KB data caches each with an 8 word line length By providing a complete set of common system peripherals the S3C2451X minimizes overall system costs and eliminates the need to configure additional components The integrated on chip functions that are described in this document include Around 400MHz 1 3V 533MHz TBDV Core 1 8V 2 5V 3 0V 3 3V ROM SRAM 1 8V 2 5V mSDR mDDR DDR2 SDRAM 1 8V 2 5V 3 3V ex...

Page 6: ...s for ROM SRAM and others NAND CF etc Two memory banks for Synchronous DRAM Complete Programmable access cycles for all memory banks Supports external wait signals to expand the bus cycle Supports self refresh mode in SDRAM for power down Supports various types of ROM for booting NOR NAND Flash EEPROM OneNAND and others NAND Flash Boot Loader Supports booting from NAND flash memory Only 8bit boot ...

Page 7: ...orts 24 external interrupt ports 174 Multiplexed input output ports DMA Controller 8 ch DMA controller Supports memory to memory IO to memory memory to IO and IO to IO transfers Burst transfer mode to enhance the transfer rate LCD Controller Supports 1 2 4 or 8 bpp bit per pixel palette color displays for color Supports 16 24 bpp non palette true color displays for color Supports maximum 16M color...

Page 8: ...2ch 32bit 16depth Tx FIFO 32bit 16depth Rx FIFO Serial 8 16 24 bit per channel data transfers Supports IIS format and MSB justified data format AC97 Audio Interface 1port AC97 for audio interface with DMA based operation 16 bit Stereo Audio PCM Audio interface Mono 16bit PCM 2 ports audio interface Master mode only this block always sources the main shift clock Input 16bit 32depth and output 16bit...

Page 9: ...eliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice BLOCK DIAGRAM Figure 1 1 S3C2451X Block Diagram ...

Page 10: ... information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice PIN ASSIGNMENTS Figure 1 2 S3C2451X Pin Assignments 380 FBGA 0 65mm pitch Top view ...

Page 11: ...G6 43 VSS A20 80 RGB_VD13 GPD5 U2 7 nWAIT C1 44 CAMDATA3 GPJ3 L9 81 RGB_VD14 GPD6 T3 8 FCLE GPA17 B2 45 CAMDATA4 GPJ4 K2 82 RGB_VD15 GPD7 V1 9 FALE GPA18 D2 46 CAMDATA5 GPJ5 L8 83 RGB_VD16 GPD8 R4 10 nFWE GPA19 H7 47 CAMDATA6 GPJ6 K1 84 RGB_VD17 GPD9 V2 11 nFRE GPA20 D1 48 CAMDATA7 GPJ7 L6 85 RGB_VD18 GPD10 P6 12 nFCE GPA22 D4 49 CAMPCLKOUT GPJ11 L1 86 RGB_VD19 GPD11 W1 13 FRnB GPM1 E1 50 CAMRESET...

Page 12: ...GPB5 AA2 27 RDATA6 H4 64 GPC7 N9 101 nXBREQ RTCK GPB6 T7 28 RDATA5 J9 65 RGB_VD0 GPC8 N3 102 nXDACK1 I2CSDA1 GPB7 Y3 29 RDATA4 G2 66 RGB_VD1 GPC9 M7 103 nXDREQ1 I2CSCL1 GPB8 W4 30 RDATA3 H3 67 RGB_VD2 GPC10 P2 104 nXDACK0 I2SSDO_1 GPB9 AA3 31 RDATA2 G1 68 RGB_VD3 GPC11 P4 105 VDDiarm V5 32 RDATA1 K6 69 RGB_VD4 GPC12 R1 106 VSS D19 33 RDATA0 H2 70 RGB_VD5 GPC13 N8 107 nXDREQ0 I2SSDO_2 GPB10 W5 34 C...

Page 13: ...6 I2S1_SDI PCM1_S DI T13 118 EINT17 GPG9 Y7 143 TXD2 GPH4 T11 168 SD1_DAT 7 GPL7 I2S1_SDO PCM1_ SDO W14 119 VDD_OP2 V7 144 RXD2 GPH5 AA11 169 SD0_CLK GPE5 V15 120 VSS D7 145 TXD3 GPH6 nRTS2 R11 170 SD0_CMD GPE6 AA15 121 VDDiarm V8 146 RXD3 GPH7 nCTS2 Y11 171 SD0_DAT 0 GPE7 R13 122 VSS D9 147 SS 1 GPL14 N12 172 SD0_DAT 1 GPE8 Y15 123 EINT18 CAM_FIEL D_A GPG10 R9 148 SS 0 GPL13 V11 173 SD0_DAT 2 GPE...

Page 14: ...that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 135 I2SLRCK GPE0 AC_nRESET PCM 0_FSYNC R10 160 VSS P19 185 AIN5 R14 136 I2SSCLK GPE1 AC_SYNC PCM0_ SCLK V10 161 SD1_DAT 0 GPL0 R12 186 AIN4 AA19 ...

Page 15: ...75 SDATA11 F16 194 Xtirtc W19 235 EINT12 GPG4 L16 276 SDATA10 D18 195 Xtortc AA20 236 EINT13 GPG5 M21 277 SDATA9 F15 196 OM 4 V19 237 EINT14 GPG6 L15 278 SDATA8 C19 197 OM 3 R15 238 EINT15 GPG7 K16 279 SDATA7 B18 198 OM 2 W20 239 VDD_USBOSC L18 280 SDATA6 D17 199 OM 1 R16 240 VSS33C L19 281 SDATA5 G14 200 OM 0 W21 241 XO_UDEV L20 282 SDATA4 B19 201 VDDi J3 242 XI_UDEV L21 283 SDATA3 F14 202 VSS F1...

Page 16: ...15 215 BATT_FLT T21 256 SDATA26 GPK10 G20 297 nSWE A15 216 NRESET N16 257 VDDi K14 298 SCLK D14 217 VDD_OP1 P18 258 VSS K4 299 VDDi L2 218 VSS F3 259 SDATA25 GPK9 J15 300 VSS M19 219 VDDalive N18 260 SDATA24 GPK8 F21 301 nSCLK D13 220 VSS G18 261 SDATA23 GPK7 H18 302 SCKE A14 221 TDO N14 262 SDATA22 GPK6 F20 303 nSRAS H13 222 TMS R20 263 SDATA21 GPK5 G19 304 nSCAS B13 223 TDI M16 264 SDATA20 GPK4 ...

Page 17: ... W8 315 SADDR8 H12 346 VSS N19 377 VSS W9 316 SADDR9 A11 347 RADDR9 B6 378 VSSA_ADC Y21 317 SADDR10 B11 348 RADDR8 C6 379 VSSA_ADC Y17 318 SADDR11 F11 349 RADDR7 A5 380 VDDA_ADC V17 319 SADDR12 J12 350 RADDR6 A4 381 320 SADDR13 D11 351 RADDR5 H8 382 321 SADDR14 G11 352 RADDR4 D6 383 322 SADDR15 C11 353 RADDR3 B5 384 323 FSOURCE A10 354 RADDR2 C5 385 324 VGATE B10 355 RADDR1 F8 386 325 nWE_CF GPA27...

Page 18: ... in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 336 RADDR18 GPA3 C8 367 VDDi W13 398 337 RADDR17 GPA2 J10 368 VSS P3 399 338 RADDR16 GPA1 A7 369 VSS T18 400 339 RADDR15 F9 370 VSS U3 340 RADDR14 B7 371 VSS U4 ...

Page 19: ...vhbsudtbrt 9 FALE GPA18 FALE O L pvhbsudtbrt 10 nFWE GPA19 nFWE O H pvhbsudtbrt 11 nFRE GPA20 nFRE O H pvhbsudtbrt 12 nFCE GPA22 nFCE O H pvhbsudtbrt 13 FRnB GPM1 FRnB I pvhbsudtbrt 14 VDDi VDDi P vddivh_alv 15 VSS VSS P vssipvh_alv 16 VDD_SRAM VDD_SRAM P vddtvh_alv 17 VSS VSS P vsstvh_alv 18 RDATA15 RDATA15 Hi z pvhbsudtbrt 19 RDATA14 RDATA14 Hi z pvhbsudtbrt 20 RDATA13 RDATA13 Hi z pvhbsudtbrt 2...

Page 20: ...J4 I pvhbsudtart 46 CAMDATA5 GPJ5 GPJ5 I pvhbsudtart 47 CAMDATA6 GPJ6 GPJ6 I pvhbsudtart 48 CAMDATA7 GPJ7 GPJ7 I pvhbsudtart 49 CAMPCLKOUT GPJ11 GPJ11 I pvhbsudtart 50 CAMRESET GPJ12 GPJ12 I pvhbsudtart 51 VDDi VDDi P vddivh_alv 52 VSS VSS P vssipvh_alv 53 VDDiarm VDDiarm P vddicvlh_alv 54 VSS VSS P vssicvlh_alv 55 RGB_LEND GPC0 GPC0 I pvhbsudtart 56 VDDiarm VDDiarm P vddicvlh_alv 57 VSS VSS P vss...

Page 21: ...5 I pvhbsudtart 81 RGB_VD14 GPD6 GPD6 I pvhbsudtart 82 RGB_VD15 GPD7 GPD7 I pvhbsudtart 83 RGB_VD16 GPD8 GPD8 I pvhbsudtart 84 RGB_VD17 GPD9 GPD9 I pvhbsudtart 85 RGB_VD18 GPD10 GPD10 I pvhbsudtart 86 RGB_VD19 GPD11 GPD11 I pvhbsudtart 87 VDDiarm VDDiarm P vddicvlh_alv 88 VSS VSS P vssicvlh_alv 89 VDD_LCD VDD_LCD P vddtvh_alv 90 VSS VSS P vsstvh_alv 91 RGB_VD20 GPD12 GPD12 I pvhbsudtart 92 RGB_VD2...

Page 22: ... nCTS1 GPH10 GPH10 I pvhbsudtart 114 nRTS1 GPH11 GPH11 I pvhbsudtart 115 TXD1 GPH2 GPH2 I pvhbsudtart 116 RXD1 GPH3 GPH3 I pvhbsudtart 117 EINT16 GPG8 GPG8 I pvhbsudtart 118 EINT17 GPG9 GPG9 I pvhbsudtart 119 VDD_OP2 VDD_OP2 P vddtvh_alv 120 VSS VSS P vsstvh_alv 121 VDDiarm VDDiarm P vddicvlh_alv 122 VSS VSS P vssicvlh_alv 123 EINT18 GPG10 CAM_FIE LD_A GPG10 I pvhbsudtart 124 EINT19 nIREQ_CF GPG1 ...

Page 23: ...ICLK0 GPE13 GPE13 I pvhbsudtart 143 TXD2 GPH4 GPH4 I pvhbsudtart 144 RXD2 GPH5 GPH5 I pvhbsudtart 145 TXD3 GPH6 nRTS2 GPH6 I pvhbsudtart 146 RXD3 GPH7 nCTS2 GPH7 I pvhbsudtart 147 SS 1 GPL14 GPL14 I pvhbsudtart 148 SS 0 GPL13 GPL13 I pvhbsudtart 149 SPIMISO1 GPL12 GPL12 I pvhbsudtart 150 SPIMOSI1 GPL11 GPL11 I pvhbsudtart 151 SPICLK1 GPL10 GPL10 I pvhbsudtart 152 SD1_nWP GPJ15 GPJ15 I pvhbsudtart ...

Page 24: ... 0 GPE7 GPE7 I pvhbsudtart 172 SD0_DAT 1 GPE8 GPE8 I pvhbsudtart 173 SD0_DAT 2 GPE9 GPE9 I pvhbsudtart 174 SD0_DAT 3 GPE10 GPE10 I pvhbsudtart 175 VSSA_MPLL VSSA_MPLL P vsstvlh_alv 176 VDDA_MPLL VDDA_MPLL P vddtvlh_alv 177 VSSA_EPLL VSSA_EPLL P vsstvlh_alv 178 UPLLCAP UPLLCAP AI pvhbr 179 VDDA_EPLL VDDA_EPLL P vddtvlh_alv 180 VSSA_ADC VSSA_ADC P 181 AIN9 XP AIN9 AI vsstvh_alv 182 AIN8 XM AIN8 AI p...

Page 25: ...2 GPF2 GPF2 I pvhbsudtart_alv 209 EINT3 GPF3 GPF3 I pvhbsudtart_alv 210 EINT4 GPF4 GPF4 I pvhbsudtart_alv 211 EINT5 GPF5 GPF5 I pvhbsudtart_alv 212 EINT6 GPF6 GPF6 I pvhbsudtart_alv 213 EINT7 GPF7 GPF7 I pvhbsudtart_alv 214 PWR_EN PWR_EN O L O H pvhbsudtart_alv 215 BATT_FLT BATT_FLT I pvhbsudtart 216 nRESET nRESET I pvhbsudtart 217 VDD_OP1 VDD_OP1 P vddtvh_alv 218 VSS VSS P vsstvh_alv 219 VDDalive...

Page 26: ..._usb_alv 245 VSS33T VSS33T P vsstvh_alv 246 DM_UDEV DM_UDEV Hi z pvhtbr 247 REXT REXT pvhbr 248 DP_UDEV DP_UDEV Hi z pvhtbr 249 VDD33 VDD33 P vddtvh_alv 250 VDD33 VDD33 P vddtvh_alv 251 SDATA31 GPK15 SDATA31 Hi z pvmbsudtbrt 252 SDATA30 GPK14 SDATA30 Hi z pvmbsudtbrt 253 SDATA29 GPK13 SDATA29 Hi z pvmbsudtbrt 254 SDATA28 GPK12 SDATA28 Hi z pvmbsudtbrt 255 SDATA27 GPK11 SDATA27 Hi z pvmbsudtbrt 256...

Page 27: ... z pvmbsudtbrt 280 SDATA6 SDATA6 Hi z pvmbsudtbrt 281 SDATA5 SDATA5 Hi z pvmbsudtbrt 282 SDATA4 SDATA4 Hi z pvmbsudtbrt 283 SDATA3 SDATA3 Hi z pvmbsudtbrt 284 SDATA2 SDATA2 Hi z pvmbsudtbrt 285 SDATA1 SDATA1 Hi z pvmbsudtbrt 286 SDATA0 SDATA0 Hi z pvmbsudtbrt 287 VDD_SDRAM VDD_SDRAM P vddtvm_alv 288 VSS VSS P vsstvm_alv 289 DQS1 DQS1 O L Hi z pvmbsudtbrt 290 DQS0 DQS0 O L Hi z pvmbsudtbrt 291 DQM3...

Page 28: ...R9 O L pvmbsudtbrt 317 SADDR10 SADDR10 O L pvmbsudtbrt 318 SADDR11 SADDR11 O L pvmbsudtbrt 319 SADDR12 SADDR12 O L pvmbsudtbrt 320 SADDR13 SADDR13 O L pvmbsudtbrt 321 SADDR14 SADDR14 O L pvmbsudtbrt 322 SADDR15 SADDR15 O L pvmbsudtbrt 323 FSOURCE FSOUARCE P pvhtbr00_efuse 324 VGATE VGATE P pvhtbr00_efuse 325 nWE_CF GPA27 nWE_CF O H pvhbsudtbrt 326 nOE_CF GPA11 nOE_CF O H pvhbsudtbrt 327 VDDi VDDi ...

Page 29: ...RADDR9 RADDR9 O L pvhbsudtbrt 348 RADDR8 RADDR8 O L pvhbsudtbrt 349 RADDR7 RADDR7 O L pvhbsudtbrt 350 RADDR6 RADDR6 O L pvhbsudtbrt 351 RADDR5 RADDR5 O L pvhbsudtbrt 352 RADDR4 RADDR4 O L pvhbsudtbrt 353 RADDR3 RADDR3 O L pvhbsudtbrt 354 RADDR2 RADDR2 O L pvhbsudtbrt 355 RADDR1 RADDR1 O L pvhbsudtbrt 356 RADDR0 GPA0 RADDR0 O L pvhbsudtbrt 357 nRBE1 nRBE1 O H pvhbsudtbrt 358 nRBE0 nRBE0 O H pvhbsud...

Page 30: ...ate nRESET I O Type 377 VSS VSS P 378 VSSA_ADC VSSA_ADC P 379 VSSA_ADC VSSA_ADC P 380 VDDA_ADC VDDA_ADC P NOTES 1 The BUS REQ shows the pin state at the external bus which is used by the other bus master 2 mark indicates the unchanged pin state at Bus Request mode 3 Hi z or Pre means Hi z or early state and it is determined by the setting of MISCCR register 4 AI AO means analog input analog output...

Page 31: ...V Schmit Y Y Y 2 6 5 2 7 8 10 5mA pvhbsudtart_alv Bi 1 8 2 5 3 3V Schmit N Y Y 2 6 5 2 7 8 10 5mA pvhbsudtbrt Bi 1 8 2 5 3 3V Schmit Y Y Y 3 3 6 6 9 9 13 2mA pvhckdsrt I 1 8 2 5 3 3V Schmit N N pvhsosca OSC 1 8 2 5 3 3V Schmit N N X1 2 5 3 3 X2 1 8 pvhsoscbrt OSC 1 8 2 5 3 3V schmit Y N N X1 X2 X3 X4 Pvhtbr Bi 1 8 2 5 3 3V analog pvhtbr00_efuse Bi 1 8 2 5 3 3V analog pvmbsudtbrt Bi 1 8 2 5V schmit...

Page 32: ... into a known reset state For a reset nRESET must be held to L level for at least 4 OSCin after the processor power has been stabilized nRSTOUT O For external device reset control nRSTOUT nRESET nWDTRST SW_RESET SW_RESET nRSTCON of GPIO MISCCR PWREN O core power on off control signal nBATT_FLT I Probe for battery state Does not wake up at Sleep mode in case of low battery state If it isn t used it...

Page 33: ...DRAM chip select DQM 3 0 O SDRAM data mask DQS 1 0 O mDDR DDR2 Data Strobe SCLK O SDRAM clock nSCLK O mDDR DDR2 Conversion clock SCKE O SDRAM clock enable NAND Flash FCLE O Command latch enable FALE O Address latch enable nFCE O Nand flash chip enable nFRE O Nand flash read enable nFWE O Nand flash write enable FRnB I Nand flash ready busy SMC OneNAND RSMCLK I O SMC Clock RSMVAD O SMC Address Vali...

Page 34: ...TA 7 0 I Camera interface data CAM_FIELD_A I Interlace field only used in interlace mode Interrupt Control Unit EINT 23 0 I External interrupt request External I F nXDREQ 1 0 I External DMA request nXDACK 1 0 O External DMA acknowledge nXBREQ I nXBREQ Bus Hold Request allows another bus master to request control of the local bus nXBACK active indicates that bus control has been granted nXBACK O nX...

Page 35: ...O IIS bus serial data output Rear Left Right IIS Bus I2S1_LRCK IO IIS bus channel select clock I2S1_SCLK IO IIS bus serial clock I2S1_CDCLK IO CODEC system clock I2S1_SDI I IIS bus serial data input I2S1_SDO O IIS bus serial data output AC 97 AC_nRESET IO AC 97 Master H W Reset AC_SYNC IO 12 288MHz serial data clock AC_BIT_CLK0 O 48kHz fixed rate sample sync AC_SDI0 I Serial time division multiple...

Page 36: ...ve transmit data SD1_CMD IO SD1 receive response transmit command SD1_CLK O SD1 clock SD1_nWP O SD1 Write Protect SD1_nCD O SD1 Card Detect SD1_nLED O SD1 LED SD0_DAT 3 0 IO SD0 receive transmit data SD0_CMD IO SD0 receive response transmit command SD0_CLK O SD0 clock General Port GPn 147 0 IO General input output ports which are multiplexed with other function pins some ports are output only TIMM...

Page 37: ... SDRAM I O Power 1 8V 2 5V VDD_SRAM P S3C2451X ROM SRAM I O Power VDD_OP1 P S3C2451X System I O Power 1 2 5 3 3V VDD_OP2 P S3C2451X System I O Power 2 1 8 3 3V VDD_OP3 P S3C2451X System I O Power 3 1 8 3 3V VDD_CAM P S3C2451X Camera I O Power 1 8 3 3V VDD_LCD P S3C2451X LCD I O Power 2 5 3 3V VDD_SD P S3C2451X SD MMC I O Power 1 8 3 3V VDD_RTC P RTC VDD 3 0V Input range 2 5 3 6V This pin must be c...

Page 38: ...OSC 0 1 addr 4 EXT 0 OSC 0 1 1 page 4K addr 5 EXT 0 OSC 0 1 addr 4 EXT 0 OSC 0 1 1 1 N A N D Large Block page 2K addr 5 EXT NAND 0 OSC 0 1 iROM EXT iROM 0 0 1 1 Reserved Reserved 0 OSC 0 1 addr 3 EXT 0 OSC 0 1 1 1 1 N A N D Small Block page 512 addr 4 EXT NAND 0 Reserved Reserved 0 1 JTAG JTAG 0 OSC 0 1 1 OneNAND Muxed 16 bit EXT OneNAND Muxed 0 OSC 0 1 8 bit EXT 0 OSC 1 0 1 1 1 OneNAND ROM ROM On...

Page 39: ...IAL REGISTERS Memory Map SRAM 64KB SDRAM nSCS1 SDRAM nSCS0 SROM nRCS5 SROM nRCS4 SROM nRCS3 SROM nRCS2 SROM nRCS1 SROM nRCS0 Using OneNAND for boot ROM SRAM 8KB SDRAM nSCS1 SDRAM nSCS0 SROM nRCS5 SROM nRCS4 ROM nRCS3 SROM nRCS2 SROM nRCS1 Internal iROM Using iROM for boot ROM MPORT1 MPORT0 SDRAM nSCS1 SDRAM nSCS0 SROM nRCS5 SROM nRCS4 SROM nRCS3 SROM nRCS2 SROM nRCS1 SRAM 8KB Using Nand flash for ...

Page 40: ..._0100 PCM1 0x4D00_0000 Reserved 0x5C00_0000 PCM0 0x4C80_0000 LCD 0x5B00_0000 AC97 0x4C00_0000 SYSCON 0x5A00_0000 Reserved 0x4B80_0000 CF Card 0x5900_0000 HS SPI1 0x4B00_0700 DMA7 0x5800_0000 TSADC 0x4B00_0600 DMA6 0x5700_0000 RTC 0x4B00_0500 DMA5 0x5600_0000 IO Port 0x4B00_0400 DMA4 0x5500_0100 IIS1 0x4B00_0300 DMA3 0x5500_0000 IIS0 0x4B00_0200 DMA2 0x5400_0100 IIC1 0x4B00_0100 DMA1 0x5400_0000 II...

Page 41: ... W Bank2 idle cycle control register SMBIDCYR3 0x4F000060 0x0000000F W R W Bank3 idle cycle control register SMBIDCYR4 0x4F000080 0x0000000F W R W Bank4 idle cycle control register SMBIDCYR5 0x4F0000A0 0x0000000F W R W Bank5 idle cycle control register SMBWSTRDR0 0x4F000004 0x0000001F W R W Bank0 read wait state control register SMBWSTRDR1 0x4F000024 0x0000001F W R W Bank1 read wait state control ...

Page 42: ...R W Bank4 write enable assertion delay control register SMBWSTWENR5 0x4F0000B0 0x00000002 W R W Bank5 write enable assertion delay control register SMBCR0 0x4F000014 W R W Bank0 control register SMBCR1 0x4F000034 0x00303000 W R W Bank1 control register SMBCR2 0x4F000054 0x00303010 W R W Bank2 control register SMBCR3 0x4F000074 0x00303000 W R W Bank3 control register SMBCR4 0x4F000094 0x00303010 W ...

Page 43: ...00001C 0x00000000 W R W Interrupt sub mask PRIORITY_MODE1 0X4A000030 0x00000000 W R W Priority mode register PRIORITY_UPDATE 1 0X4A000034 0xFFFFFFFF W R W Priority update register SRCPND2 0X4A000040 0x00000000 W R W Interrupt request status 2 INTMOD2 0X4A000044 0x00000000 W R W Interrupt mode control 2 INTMSK2 0X4A000048 0xFFFFFFFF W R W Interrupt mask control 2 INTPND2 0X4A000050 0x00000000 W R W...

Page 44: ...944 0x00000000 ATA start address of source buffer ATA_SBUF_SIZE 0x4B801948 0x00000000 ATA size of source buffer ATA_SBUF_ START 0x4B801944 0x00000000 ATA start address of source buffer ATA_SBUF_SIZE 0x4B801948 0x00000000 ATA size of source buffer ATA_CADR_TBUF 0x4B80194C 0x00000000 ATA current write address of track buffer ATA_CADR_SBUF 0x4B801950 0x00000000 ATA current read address of source buff...

Page 45: ...HcControlCurrent ED 0x49000024 R W HcBulkHeadED 0x49000028 R W HcBulkCurrentED 0x4900002C R W HcDoneHead 0x49000030 R W Frame counter group HcRmInterval 0x49000034 R W HcFmRemaining 0x49000038 R W HcFmNumber 0x4900003C R W HcPeriodicStart 0x49000040 R W HcLSThreshold 0x49000044 R W HcRhDescriptorA 0x49000048 R W Root hub group HcRhDescriptorB 0x4900004C R W HcRhStatus 0x49000050 R W HcRhPortStatus...

Page 46: ...l source control DIDST2 0x4B000208 R W DMA 2 initial destination DIDSTC2 0x4B00020C R W DMA 2 initial destination control DCON2 0x4B000210 R W DMA 2 control DSTAT2 0x4B000214 R DMA 2 count DCSRC2 0x4B000218 R DMA 2 current source DCDST2 0x4B00021C R DMA 2 current destination DMASKTRIG2 0x4B000220 R W DMA 2 mask trigger DMAREQSEL2 0x4B000224 R W DMA2 Request Selection Register DISRC3 0x4B000300 W R...

Page 47: ...n DMASKTRIG5 0x4B000520 R W DMA 5 mask trigger DMAREQSEL5 0x4B000524 R W DMA5 Request Selection Register DISRC6 0x4B000600 W R W DMA 6 initial source DISRCC6 0x4B000604 R W DMA 6 initial source control DIDST6 0x4B000608 R W DMA 6 initial destination DIDSTC6 0x4B00060C R W DMA 6 initial destination control DCON6 0x4B000610 R W DMA 6 control DSTAT6 0x4B000614 R DMA 6 count DCSRC6 0x4B000618 R DMA 6 ...

Page 48: ...e control register SWRST 0x4C00_0044 0x0000_0000 Software reset control register BUSPRI0 0x4C00_0050 0x0000_0000 Bus priority control register 0 PWRCFG 0x4C00_0060 0x0000_0000 Power management configuration register RSTCON 0x4C00_0064 0x0006_0101 R Reset control register RSTSTAT 0x4C00_0068 0x0000_0001 R W Reset status register WKUPSTAT 0x4C00_006C 0x0000_0000 Wake up status register INFORM0 0x4C0...

Page 49: ...er start address register VIDW00ADD1B0 0x4C80_007C 0x0000_0000 W R W Window 0 s buffer end address register buffer 0 VIDW00ADD1B1 0x4C80_0080 0x0000_0000 W R W Window 0 s buffer end address register buffer 1 VIDW01ADD1 0x4C80_0084 0x0000_0000 W R W Window 1 s buffer end address register VIDW00ADD2B0 0x4C80_0094 0x0000_0000 W R W Window 0 s buffer size register buffer 0 VIDW00ADD2B1 0x4C80_0098 0x0...

Page 50: ...ddress WIN1 Palette RAM 0x4C80_0800 0x4C80_0BFC Undefined W R W Window 0 s palette entry 0 255 address NAND Flash NFCONF 0x4E000000 0x 000100 W R W Configuration register NFCONT 0x4E000004 0x000100C6 W R W Control register NFCMMD 0x4E000008 0x00000000 W R W Command register NFADDR 0x4E00000C 0x00000000 W R W Address register NFDATA 0x4E000010 B W R W Data register NFMECCD0 0x4E000014 0x00000000 W ...

Page 51: ...gister CIGCTRL 0x4D80_0008 Global control register CIDOWSFT2 0x4D80_0014 Window option register 2 CICOYSA1 0x4D80_0018 Y 1st frame start address for codec DMA CICOYSA2 0x4D80_001C Y 2nd frame start address for codec DMA CICOYSA3 0x4D80_0020 Y 3rd frame start address for codec DMA CICOYSA4 0x4D80_0024 Y 4th frame start address for codec DMA CICOCBSA1 0x4D80_0028 Cb 1st frame start address for codec...

Page 52: ...84 Preview pre scaler ratio control CIPRSCPREDST 0x4D80_0088 Preview pre scaler destination format CIPRSCCTRL 0x4D80_008C Preview main scaler control CIPRTAREA 0x4D80_0090 Preview scaler target area CIPRSTATUS 0x4D80_0098 Preview path status CIIMGCPT 0x4D80_00A0 Image capture enable command CICOCPTSEQ 0x4D80_00A4 Codec dma capture sequence related CICOSCOS 0x4D80_00A8 Codec scan line offset relate...

Page 53: ...CON1 0x50004004 UART 1 control UFCON1 0x50004008 UART 1 FIFO control UMCON1 0x5000400C UART 1 modem control UTRSTAT1 0x50004010 R UART 1 Tx Rx status UERSTAT1 0x50004014 UART 1 Rx error status UFSTAT1 0x50004018 UART 1 FIFO status UMSTAT1 0x5000401C UART 1 modem status UTXH1 0x50004020 B W UART 1 transmission hold URXH1 0x50004024 R UART 1 receive buffer UBRDIV1 0x50004028 W R W UART 1 baud rate d...

Page 54: ...imer compare buffer 0 TCNTO0 0x51000014 0x0 W R Timer count observation 0 TCNTB1 0x51000018 0x0 W R W Timer count buffer 1 TCMPB1 0x5100001C 0x0 W R W Timer compare buffer 1 TCNTO1 0x51000020 0x0 W R Timer count observation 1 TCNTB2 0x51000024 0x0 W R W Timer count buffer 2 TCMPB2 0x51000028 0x0 W R W Timer compare buffer 2 TCNTO2 0x5100002C 0x0 W R Timer count observation 2 TCNTB3 0x51000030 0x0 ...

Page 55: ...100 0x0 R W Burst FIFO DMA Control FSTAT 0x4980_0104 0x0 R Burst FIFO status ESR 0x4980_002C 0x0 R W Endpoints Status Register ECR 0x4980_0030 0x0 R W Endpoints Control Register BRCR 0x4980_0034 0x0 R Byte Read Count Register BWCR 0x4980_0038 0x0 R W Byte Write Count Register MPR 0x4980_003C 0x0 R W Max Packet Register DCR 0x4980_0040 0x0 R W DMA Control Register DTCR 0x4980_0044 0x0 R W DMA Trans...

Page 56: ...TXD 0x55000010 0x0 W I2S interface transmit data register I2SRXD 0x55000014 0x0 R I2S interface receive data register IIS IISCON 0x55000100 0x600 W R W IIS control IISMOD 0x55000104 0x0 IIS mode I2SFIC 0x55000108 0x0 I2S interface FIFO control register I2SPSR 0x5500010C 0x0 I2S interface clock divider control register I2STXD 0x55000110 0x0 W I2S interface transmit data register I2SRXD 0x55000114 0...

Page 57: ...0x560000D8 0x55555555 W R W Pull up down control J GPJSEL 0x560000dc 0x0 W R W Selects the function of port J GPKCON 0x560000E0 0xAAAAAAAA W R W Port K control GPKDAT 0x560000E4 0x0 W R W Port K data GPKUDP 0x560000E8 0x55555555 W R W Pull up down control K GPLCON 0x560000F0 0x0 W R W Port L control GPLDAT 0x560000F4 0x0 W R W Port L data GPLUDP 0x560000F8 0x15555555 W R W Pull up down control L G...

Page 58: ...e count register 0 TICNT1 0x57000048 0x0 B R W Tick time count register 1 TICNT2 0x5700004C 0x0 W R W Tick time count register 2 RTCALM 0x57000050 0x0 B R W RTC alarm control ALMSEC 0x57000054 0x0 B R W Alarm second ALMMIN 0x57000058 0x00 B R W Alarm minute ALMHOUR 0x5700005C 0x0 B R W Alarm hour ALMDATE 0x57000060 0x01 B R W Alarm day ALMMON 0x57000064 0x01 B R W Alarm month ALMYEAR 0x57000068 0x...

Page 59: ...CFG 0x59000000 0x40 R W SPI configuration register Clk_CFG 0x59000004 0x0 R W Clock configuration register MODE_CFG 0x59000008 0x0 R W SPI FIFO control register Slave_slection_reg 0x5900000C 0x1 R W Slave selection signal SPI_INT_EN 0x59000010 0x0 R W SPI Interrupt Enable register SPI_STATUS 0x59000014 0x0 R SPI status register SPI_TX_DATA 0x59000018 0x0 W SPI TX DATA register SPI_RX_DATA 0x590000...

Page 60: ...NTSTS 0x4AC00032 0x00000000 HW ROC RW1C Error Interrupt Status Register NORINTSTSEN 0x4AC00034 0x00000000 HW R W Normal Interrupt Status Enable Register ERRINTSTSEN 0x4AC00036 0x00000000 HW R W Error Interrupt Status Enable Register NORINTSIGEN 0x4AC00038 0x00000000 HW R W Normal Interrupt Signal Enable Register ERRINTSIGEN 0x4AC0003A 0x00000000 HW R W Error Interrupt Signal Enable Register ACMD12...

Page 61: ...00000 B R W Present State Register BLKGAP 0x4A80002A 0x00000000 B R W Block Gap Control Register WAKCON 0x4A80002B 0x00000000 B R W Wakeup Control Register CLKCON 0x4A80002C 0x00000000 HW R W Command Register TIMEOUTCON 0x4A80002E 0x00000000 B R W Timeout Control Register SWRST 0x4A80002F 0x00000000 B R W Software Reset Register NORINTSTS 0x4A800030 0x00000000 HW ROC RW1C Normal Interrupt Status R...

Page 62: ...nnel FIFO address register AC_MICADDR 0x5B000014 0x0 R AC97 mic in channel FIFO address register AC_PCMDATA 0x5B000018 0x0 R W AC97 PCM out in channel FIFO data register AC_MICDATA 0x5B00001C 0x0 R AC97 MIC in channel FIFO data register PCM Audio Interface PCM_CTL0 0x5C000000 0x0 W R W PCM0 Main Control PCM_CTL1 0x5C000100 0x0 R W PCM1 Main Control PCM_CLKCTL0 0x5C000004 0x0 R W PCM0 Clock and Shi...

Page 63: ...Color Expansion Host to Screen Font Start CMD5_REG 0x4D408114 W Command register for Color Expansion Host to Screen Font Continue CMD6_REG 0x4D408118 W Reserved CMD7_REG 0x4D40811C W Command register for Color Expansion Memory to Screen SRC_ RES_REG 0x4D408200 0x0000_0000 R W Source Image Resolution SRC_HORI_RES_R EG 0x4D408204 0x0000_0000 R W Source Image Horizontal Resolution SRC_VERT_RES_R EG 0...

Page 64: ...Origin Coordinates ROT_OC_X_REG 0x4D408344 0x0000_0000 R W X coordinate of Rotation Origin Coordinates ROT_OC_Y_REG 0x4D408348 0x0000_0000 R W Y coorindate of Rotation Origin Coordinates ROTATE_REG 0x4D40834C 0x0000_0001 R W Rotation Mode register X_INCR_REG 0x4D408400 0x0000_0000 R W X Increment register Y_INCR_REG 0x4D408404 0x0000_0000 R W Y Increment register ROP_REG 0x4D408410 0x0000_0000 R W...

Page 65: ...ata and associated errata are not yet available Specifications and information herein are subject to change without notice Register Name Address Reset Value Acc Unit Read Write Function SRC_BASE_ADDR_ REG 0x4D408730 0x0000_0000 R W Source Image Base Address register DEST_BASE_ADDR _REG 0x4D408734 0x0000_0000 R W Dest Image Base Address register in most cases frame buffer address ...

Page 66: ...ian mode 2 The special registers have to be accessed for each recommended access unit 3 All registers except ADC registers RTC registers and UART registers must be read write in word unit 32 bit 4 Make sure that the ADC registers RTC registers and UART registers be read write by the specified access unit and the specified address 5 W 32 bit register which must be accessed by LDR STR or int type po...

Page 67: ...e other blocks Typically the operating frequency of the ARM core is 533MHz while the AHB blocks and the APB blocks operate on 133MHz and 66MHz respectively Thus the power control of the ARM core is major issue to reduce the overall power dissipation in S3C2451X and IDLE mode is supported for this purpose In IDLE mode the ARM core is not operated until the external interrupts or internal interrupts...

Page 68: ...stem controller must be alive when the external power supply is disabled The ALIVE part is supplied by an auxiliary power source and waits until external internal interrupts However the OFF part is disabled when the power down mode is SLEEP The clock generator makes all internal clocks which include ARMCLK for the ARM core HCLK for the AHB blocks PCLK for the APB block and other special clocks The...

Page 69: ...ile the reset is progressed When the unmaskable nRESET pin is asserted as low the internal hardware reset signal is generated Upon assertion of nRESET S3C2451x enters reset state regardless of the previous state To enter hardware reset state nRESET must be held long enough to allow internal stabilization and propagation of the reset state Caution An external power source regulator for S3C2451x mus...

Page 70: ...n software fails to prevent the watchdog timer from timing out During the watchdog reset the following actions occur All units except some blocks listed in table 2 1 go into their pre defined reset state All pins get their reset state and BATT_FLT pin is ignored The nRSTOUT pin is asserted during watchdog reset Watchdog reset can be activated in normal and idle mode because watchdog timer can expi...

Page 71: ...nowledge to system controller after completed bus transactions 4 System controller request memory controller to enter into self refresh mode 5 System controller wait for self refresh acknowledge from memory controller 6 Internal reset signals and nRSTOUT are asserted and reset counter is activated 7 Reset counter is expired then internal reset signals and nRSTOUT are deasserted WAKEUP RESET When S...

Page 72: ...ut If you change or select EPLL input clock when either XTI or EXTCLK is running disabled clock should be have logic LOW XTI clock source can be reference of PLL after oscillated at PAD User can configure stabilization time by setting OSCSET register and ON OFF when power down mode by setting PWRCFG register The clock generator consists of two PLLs Phase Locked Loop which generate the high frequen...

Page 73: ...hange without notice Table 2 3 Clock source selection for the EPLL CLKSRC 8 register CLKSRC 7 register OM 0 EPLL Reference Clock 0 X 0 XTI 0 X 1 EXTCLK 1 0 X XTI 1 1 X EXTCLK Table 2 4 PLL Clock Generator condition MPLLCAP N A Loop filter capacitance CLF EPLLCAP Typical 1 8nF 5 Fin MPLL 10 30 MHz EPLL 10 40 MHz Fout MPLL 40 1600 MHz EPLL 20 600 MHz External capacitance used for X tal CEXT 15 pF Fe...

Page 74: ...peration of the PLL that includes the phase difference detector charge pump VCO Voltage controlled oscillator and loop filter Refer to MPLLCON and EPLLCON registers to change PLL output frequency Fout Off chip loop filter Fin Pre Divider Main Divider PFD Charge Pump VCO Post Scaler Figure 2 5 PLL Phase Locked Loop Block Diagram CHANGE PLL SETTINGS IN NORMAL OPERATION During the operation of S3C245...

Page 75: ...peripherals such as the memory controller the interrupt controller LCD controller the DMA USB host block System Controller Power down controller and etc The PCLK is used for internal APB bus and peripherals such as WDT IIS I2C PWM timer ADC UART GPIO RTC and SPI etc DDRCLK is the data strobe clock for mDDR DDR2 memories CAMclk is used for camera interface block HCLKCON and PCLKCON registers are us...

Page 76: ...PREDIV HCLKDIV and PCLKDIV bits of CLKDIV0 control register ARMCLK has to faster or equal with HCLK and synchronous The table 2 5 shows that DDRCLK PCLK ARMCLK divide ratio with regard HCLK ratio The fraction in the cell is ratio to MSysClk and the value in the round bracket means maximum frequency value Table 2 5 Clock division ratio of MPLL region MSysClk 800MHz HCLK 133MHz DDRCLK 266MHz PCLK SS...

Page 77: ...hout notice EXAMPLES FOR CONFIGURING CLOCK REGITER TO PRODUCE SPECIFIC FREQUENCY OF AMBA CLOCKS When PLL output frequency 533MHz Target frqeuency ARMCLK 533MHz HCLK 133MHz PCLK 66MHz DDRCLK 266MHz SSMCCLK 66MHz Register value ARMDIV 4 b0000 PREDIV 2 b01 HCLKDIV 2 b01 PCLKDIV 1 b1 HALKHCLK 1 b1 When PLL output frequency 800MHz Target frqeuency ARMCLK 400MHz HCLK 133MHz PCLK 66MHz DDRCLK 266MHz SSMC...

Page 78: ...various peripherals Each divider value is configured in CLKDIV1 register and all clocks are enabled or disabled by accessing SCLKCON register According to USB host interface If you want to get the clock with exact 50 duty cycle then make EPLL generate 96MHz and divide the clock EPLL will be turned off during STOP and SLEEP mode automatically Also EPLL will be generated clock to ESYSCLK after exiti...

Page 79: ...wer consumption in S3C2451X These schemes are related to PLL clock control logic ARMCLK HCLK PCLK and wake up signal S3C2451X has four power down modes The following section describes each power management mode Related registers are PWRMODE PWRCFG and WKUPSTAT POWER MODE STATE DIAGRAM Figure 2 10 shows that Power Saving mode state and Entering or Exiting condition In general the entering condition...

Page 80: ... logic only detects the low to high triggering of the STOP Mode bit In Deep STOP mode ARM core s power is off by using internal power gating By this way the static current will be reduced remarkably compared with STOP mode To enter the Deep STOP mode PWRMODE 18 register should be configured before entering STOP mode After waking up from Deep STOP mode System controller resets ARM core only To exit...

Page 81: ...E 15 0 register to let system enter into the SLEEP Mode 2 System controller requests bus controller to finish bus transactions of ARM Core 3 System controller disable ARM clock after getting ARM Down acknowledge 4 System controller requests bus controller to finish current transactions 5 Bus controller send acknowledge to system controller after completed bus transactions 6 System controller reque...

Page 82: ...ary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice a Figure 2 11 Entering STOP mode and exiting STOP mode wake up ...

Page 83: ...t for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Wake up event ARM Down Req Ack ARMCLK SYSCLK DRAM Self Refresh Req Ack PWR_EN SLEEP mode is initiated CKE DRAM BUS Down Req Ack Figure 2 12 Entering SLEEP mode and exiting SLEEP mode wake up ...

Page 84: ...On Reset state except for the contents of the external DRAM is preserved In contrast S3C2451X automatically recovers the previous working state after wake up from the STOP Mode The following table shows the states of PLLs and internal clocks after wake ups from the power saving modes Table 2 7 The status of PLL and ARMCLK after wake up Mode before wake up PLL on off after wake up SYSCLK after wake...

Page 85: ...apopting power saving scheme on your system In dealing with sleep mode It is good for you to know following two restrictions To enter sleep mode by BATT_FLT you have to configure BATF_CFG bits of PWRCFG register Not to exit from sleep mode when BATT_FLT is LOW you have to configure SLEEP_CFG bit of PWRCFG register Table 2 8 Power saving mode entering exiting condition Power down mode Enter Exit Cl...

Page 86: ...CLKDIV0 0x4C00_0024 R W Clock divider ratio control register0 X 0x0000_000C CLKDIV1 0x4C00_0028 R W Clock divider ratio control register1 X 0x0000_0000 CLKDIV2 0x4C00_002C R W Clock divider ratio control register2 X 0x0000_0000 HCLKCON 0x4C00_0030 R W HCLK enable register X 0xFFFF_FFFF PCLKCON 0x4C00_0034 R W PCLK enable register X 0xFFFF_FFFF SCLKCON 0x4C00_0038 R W Special clock enable register ...

Page 87: ...10 R W MPLL configuration register 0x0185_40C0 EPLLCON 0x4C00_0018 R W EPLL configuration register 0x0120_0102 EPLLCON_K 0x4C00_001C R W EPLL configuration register for K value 0x0000_0000 Conventional PLL requires stabilization duration after the PLL is ON The duration can be varied according to the device variation Thus software must adjust these fields with appropriate values in the LOCKCON0 1 ...

Page 88: ...L 0x6 RESERVED 4 3 0x0 SDIV 2 0 Post divider value of MPLL 0x0 The output frequencies of MPLL can be calculated using the following equations FOUT m x FIN p x 2S should be 40 1600MHz Fvco m x FIN p should be 800 1600MHz where m MDIV p PDIV s SDIV Fin 10 30Mhz Don t set the value PDIV 5 0 or MDIV 9 0 to all zeros 6 b00 0000 10 b00 0000 0000 NOTE Although there is the equation for choosing PLL value...

Page 89: ... SDIV 2 0 EPLL post scaler value 0x2 EPLLCON_K Bit Description Initial Value RESERVED 31 16 0 KDIV 15 0 EPLL fractional modulator 0x0000 The output frequencies of EPLL can be calculated using the following equations FOUT m k 216 FIN p 2 s should be 20 600MHz Fvco m x FIN p where m MDIV p PDIV s SDIV k KDIV Fin 10 40MHz Don t set the value PDIV 5 0 or MDIV 7 0 to all zeros 6 b00 0000 8 b0000 0000 N...

Page 90: ...rs and MUXs to generate appropriate clocks These clocks are controlled by the clock control registers as described in here Register Address R W Description Reset Value CLKSRC 0x4C00_0020 R W Clock source control register 0x0000_0000 CLKDIV0 0x4C00_0024 R W Clock divider ratio control register0 0x0000_000C CLKDIV1 0x4C00_0028 R W Clock divider ratio control register1 0x0000_0000 CLKDIV2 0x4C00_002C...

Page 91: ...d 1 EXTCLK 0 SELHSMMC0 16 HSMMC0 clock 0 EPLL divided 1 EXTCLK 0 SELI2S 15 14 I2S clock source selection 00 divided clock of EPLL 01 external I2S clock 1X EpllRefClk 0x0 SELI2S_1 13 12 I2S_1 clock source selection 00 divided clock of EPLL 01 external I2S clock 1X EpllRefClk 0x0 RESERVED 11 9 0 SELESRC 8 7 Selection EPLL reference clock 10 XTAL 11 EXTCLK 0x identical to that of MPLL reference clock...

Page 92: ... of ARMDIV field 0 RESERVED 12 0 ARMDIV 11 9 ARM clock divider ratio ARMDIV values are recommended as below 1 1 3 b000 1 2 3 b001 1 3 3 b010 1 4 3 b011 1 6 3 b101 1 8 3 b111 0x0 EXTDIV 8 6 External clock divider ratio ratio MPLL reference clock EXTDIV 2 1 0 PREDIV 5 4 Pre Divider for HCLK PREDIV value should be one of 0 1 2 3 Output frequency of PREDIVIDER should be less than 266MHz 0 HALFHCLK 3 H...

Page 93: ...SPDIV 1 0x0 I2SDIV_0 15 12 I2S0 clock divider ratio ratio I2SDIV_0 1 0x0 UARTDIV 11 8 UART clock divider ratio ratio UARTDIV 1 0x0 HSMMCDIV_1 7 6 HSMMC_1 clock divider ratio ratio HSMMCDIV_1 1 0x0 USBHOSTDIV 5 4 Usb Host clock divider ratio ratio USBHOSTDIV 1 0x0 RESERVED 3 0 0 CLKDIV2 configures the clock ratio related on EPLL or MPLL CLKDIV2 Bit Description Initial Value RESERVED 31 26 0 SPIDIV1...

Page 94: ...EV 12 Enable HCLK into the USB device 1 USBHOST 11 Enable HCLK into the USB HOST 1 RESERVED 10 1 DISPCON 9 Enable HCLK into the display controller 1 CAMIF 8 Enable HCLK into the camera interface 1 DMA0 7 7 0 Enable HCLK into DMA channel 0 7 0xFF PCLKCON Bit Description Initial Value RESERVED 31 20 0xFFF PCM 19 Enable PCLK into the PCM 1 RESERVED 18 1 I2S_1 17 Enable PCLK into the I2S_1 1 I2C_1 16 ...

Page 95: ...ERVED 31 21 0x7FF SPICLK_MPLL1 20 Enable SPICLK1 MPLL 1 SPICLK_MPLL0 19 Enable SPICLK0 MPLL 1 PCM1_EXT 18 Enable PCM1 External Clock 1 PCM0_EXT 17 Enable PCM0 External Clock 1 DDRCLK Hx2CLK 16 Enable DDRCLK 1 SSMCCLK HX1_2CLK 15 Enable SSMCCLK 1 SPICLK_0 14 Enable HS SPI_0 EPLL clock 1 HSMMCCLK_EXT 13 Enable HSMMC_EXT clock for HSMMC0 1 EXTCLK Reference clock of MPLL 0 HSMMCCLK_1 12 Enable HSMMC1_...

Page 96: ...4C00_0040 R W Power mode control register 0x0000_0000 PWRCFG 0x4C00_0060 R W Power management configuration register 0x0000_0000 S3C2451X consists of three power down modes which are IDLE STOP and SLEEP The mode transition from the NORMAL mode occurs when the appropriate value is written into PWRMODE register If software tries to write illegal value i e tries to set multiple power modes concurrent...

Page 97: ...e wakeup sources If not system continuously remain it s sleep state 1 enable wakeup sources regardless of BATT_FLT in sleep mode 0 RESERVED 14 10 0x00 NFRESET_CFG 9 Reset configuration when internal resets is generated 0 reset NAND flash controller 1 do not reset NAND flash controller 0 RTC_CFG 8 Configure RTC alarm interrupt wakeup mask 0 wake up signal event is generated when RTC alarm occurs 1 ...

Page 98: ...rt 0x0000_0000 RSTCON register controls the duration of the system reset signal RSTCON Bit Description Initial Value RESERVED 31 19 0x0000 RESERVED 18 17 Should be set 0x3 0x3 PWROFF_SLP 16 Power Control on pad retention cell I O Retention cell I O s power will be off when sleep mode but when wakeup process starts User should write 1 to produce power on retention I O see below detailed description...

Page 99: ... value data assigned to specific PAD go out through level shifter and latch Otherwise If SLP_IN signal has HIGH value output of level shifter cannot pass therefore retention PAD produces latched data only When the system enters into a sleep mode SLP_IN value has HIGH value as a result of PWROFF s HIGH state Futhermore PWROFF_SLP register bit is automatically set to 1 b1 When the system wakeup from...

Page 100: ... cleared by the other reset If each bit has 1 value resets or wakeup events are occurred The reset priority is as follows nRESET WDTRST SLEEP DEEP STOP SW Reset RSTSTAT Bit Description Initial Value RESERVED 31 6 0x0000_000 SWRST 5 Reset by software see SWRST register 0 DEEP STOP 4 Wakeup from DEEP STOP ARM Reset only 0 SLEEP 3 Wakeup from RTC_TICK RTC_ALARM EINT and battery fault from power down ...

Page 101: ...field of BUSPRI0 register has three possible choices as follows 1 2 b00 the fixed type 2 2 b01 the last granted maser has the lowest priority 3 2 b10 the rotated type 4 2 b11 undefined BUSPRI0 Bit Description Initial Value RESERVED 31 16 0x0000 TYPE_S 15 14 Priority type for AHB System bus 0x0 RESERVED 13 12 0x0 ORDER_S 11 8 Fixed priority order for AHB S bus Value Priority Value Priority 4 h0 0 1...

Page 102: ...3 b001 1 2 3 4 5 6 0 7 3 b101 5 6 0 1 2 3 4 7 3 b010 2 3 4 5 6 0 1 7 3 b110 6 0 1 2 3 4 5 7 3 b011 3 4 5 6 0 1 2 7 3 b111 undefined 0x0 INFORMATION REGISTER 0 1 2 3 Register Address R W Description Reset Value INFORM0 0x4C00_0070 R W SLEEP mode information register 0 0x0000_0000 INFORM1 0x4C00_0074 R W SLEEP mode information register 1 0x0000_0000 INFORM2 0x4C00_0078 R W SLEEP mode information reg...

Page 103: ...ress R W Description Reset Value PHYCTRL 0x4C00_0080 R W USB2 0 PHY Control Register 0x0000_0000 PHYCTRL Bit Description Initial State RESERVED 31 5 0 CLK_SEL 4 3 Reference Clock Frequency Select 00 48MHz 01 Reserved 10 12MHz 11 24MHz 2 b00 EXT_CLK 2 Clock Select for XO Block 0 Crystal 1 Oscillator 0 INT_PLL_SEL 1 Host 1 1 uses Internal PLL Clock 48MHz 0 System PLL Clock USBHOSTCLK should be 48MHz...

Page 104: ...gnal is a strapping option that must be tied to a valid static value at all times Because the signal is a strapping option this pin is non critical for STA and any other timings or loading limits for the pin are specified in the lib timing model included in the product deliverables NOTE If common_on_n is set low clk_ref_ohci and clk12m_ohci are also available even in Suspend mode The common_on_n s...

Page 105: ...s 1 reset 0 USB CLOCK CONTROL REGISTER UCLKCON Register Address R W Description Reset Value UCLKCON 0x4C00_008C R W USB Clock Control Register 0x0000_0000 MSINTEN Bit Description Initial State DETECT_VBUS 31 VBUS Detect This VBUS indicator signal indicates that the VBUS signal on the USB cable is active For the serial interface this signal controls the pull up resistance on the D line in Device mo...

Page 106: ...MICROPROCESSOR 2 40 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NOTES ...

Page 107: ...ed for achieving high system performance by accessing various kinds of memory SDRAM SRAM Flash Memory ROM etc from different AHB bus one is for system and the other is for image at the same time S3C2451 have two MATRIX cores because it has two memory ports and each MATRIX can select the priority between rotation type and fixed type User can select which one is excellent for improving system perfor...

Page 108: ...set Value BPRIORITY0 0X4E800000 R W Matrix Core 0 priority control register 0x0000_0004 BPRIORITY0 Bit Description Initial State PRI_TYP 2 Priority type 0 Fixed Type 1 Rotation Type 1 FIX_PRI_TYP 0 Priority for the fixed priority type 0 AHB_S AHB_I 1 AHB_I AHB_S 0 MATRIX CORE 1 PRIORITY REGISTER BPRIORITY1 Register Address R W Description Reset Value BPRIORITY1 0X4E800004 R W Matrix Core 1 priorit...

Page 109: ...EBICON Register Address R W Description Reset Value EBICON 0X4E800008 R W EBI control register 0x0000_0004 EBICON Bit Description Initial State BANK3_CFG 10 Bank3 Configuration 0 SROM 1 CF 0 BANK2_CFG 9 Bank2 Configuration 0 SROM 1 CF 0 BANK1_CFG 8 Bank1 Configuration 0 SROM 1 NAND 0 PRI_TYP 2 Priority type 0 Fixed Type 1 Rotation Type 1 FIX_PRI_TYP 1 0 Priority for the fixed priority type 0 SSMC ...

Page 110: ...ICROPROCESSOR 3 4 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NOTES ...

Page 111: ...y mode BUS PRIORITY MAP The S3C2451 holds 16 masters on the AHB_S System Bus 9 masters on the AHB_I Image Bus and 9masters on the APB Bus The following list shows the priorities among these bus masters after a reset Priority AHB_S BUS MASTERS Comment 0 CF 1 HS MMC1 2 DMA0 3 DMA1 4 DMA2 5 DMA3 6 DMA4 7 DMA5 8 DMA6 9 DMA7 10 UHOST 11 UDEVICE20 12 HS MMC0 10 Reserved 11 Reserved 13 ARM926EJ DBUS 14 A...

Page 112: ...rved 1 TFTW1 LCD 2 TFTW2 LCD 3 CAMIF_PREVIEW 4 CAMIF_CODEC 5 CAMIF_PIP 6 2D 7 AHB2AHB 8 Default 1 Fix Type all priority can be changed according to register value stored in The System Controller 2 Rotation Type all masters priority can be rotatable according to register value stored in The System Controller except for Default Master Priority APB BUS MASTERS Comment 0 AHB2APB 1 DMA0 2 DMA1 3 DMA2 4...

Page 113: ... to bank5 that you can configure independently Each memory bank supports SRAM ROM Flash EPROM Burst SRAM ROM and flash OneNAND You can configure each memory bank to use 8 or 16 bit external memory data paths You can configure the SMC to support either little endian or big endian operation For example each memory bank can be configured to support nonburst read and write accesses to high speed CMOS ...

Page 114: ...vices Supports 8 and 16 bit data bus Address space Up to 64MB per Bank Fixed memory bank start address External wait to extend the bus cycle Support byte half word and word access for external memory Programmable wait states up to 31 Programmable bus turnaround cycles up to 15 Programmable output enable and write enable delays up to 15 Configurable size at reset for boot memory bank using external...

Page 115: ... notice BLOCK DIAGRAM Pad Interface SMC Core TIC Data bus Interface SMC Memory Control Signals Data and Address Bus AHB Slave Interface AHB Slave Interface Figure 5 1 SMC Block Diagram AHB Slave Interface for Register Access AHB Slave Interface for Memory Access Transfer State Machine Control Signals Control Signals Synchronizer Module nWAIT SMCANCELWAIT Pad Interface Block Control Signals AHB I F...

Page 116: ... the transfer two for the standard read and additional two because of the programmed wait states added The PSMAVD signal might be required for synchronous static memory devieces when you use it in asynchronous mode You can disable this using the AddrValidReadEn bit in the SMBCRx register This bit defaults to being set enable to enable a system to boot from synchronous memory You can then clear it ...

Page 117: ...ct information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice SMCLK ADDR DATA R nCS nWAIT A D A nOE Figure 5 5 Read Timing Diagram DRnCS 1 DRnOWE 1 ...

Page 118: ...al reads WSTBRD following the first read WSTRD The chip select and output enable lines are held during the burst and only the address changes between subsequent accesses At the end of the burst the chip select and output enable lines are deasserted together Asynchronous page mode read operation is supported This is enabled by setting the BMRead bit and by setting the burst length using BurstLenRea...

Page 119: ...nchronous reads is the same as for asynchronous reads Synchronous burst read transfers are performed differently to asynchronous burst reads because of the internal address incrementing performed by synchronous burst devices The PADDR outputs are held with the initial address value and the PSMAVD output is asserted during the transfer to indicate that the address is valid Four eight or continuous ...

Page 120: ...able is always deasserted half a cycle before the chip select at the end of the transfer nSMBLS has the same timing as nSMWEN for writes to 8 bit devices that use the byte lane selects instead of the write enables The WSTWEN programmed value must be equal to or less than the WSTWR programmed value otherwise an invalid access sequence is generated The access is timed by the WSTWR value and not by t...

Page 121: ... development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice SMCLK ADDR DATA W D A nCS nWE A nWAIT Figure 5 9 Write Timing Diagram DRnCS 1 DRnOWE 0 SMCLK ADDR DATA W D A nCS nWE A nWAIT Figure 5 10 Write Timing Diagram DRnCS 1 DRnOWE 1 ...

Page 122: ...ng the SyncWriteDev bit in the SMBCRx register You must also set the AddrValidWriteEn bit for synchronous write The signal PnWE is only active for one cycle This is active at the start of the transfer unless it is delayed using the control bits WSTWEN to delay it Synchronous burst writes are supported by the SMC There is no write buffer so you must delay the AHB transfer to enable the data to be o...

Page 123: ...en external bus transfers as follows read to read to different memory banks read to write to the same memory banks read to write to different memory banks Figure 5 12 shows a zero wait asynchronous read followed by two zero wait asynchronous writes with two turnaround cycles added The standard minimum of two AHB wait states are added to the read transfer one is added to the first write as for any ...

Page 124: ...iminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Scenario Examples ADDR CS 3 cycle CS OE 4 cycle CS WE 5 cycle ...

Page 125: ...hich full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice SRAM Memory Interface Examples Figure 5 13 Memory Interface with 8 bit SRAM 2MB Figure 5 14 Memory Interface with 16 bit SRAM 4MB SRAM ROM S3C2451 8bit data bus A0 RADDR0 Addr connection 16bit data bus A0 RADDR0 ...

Page 126: ...111 at reset This field controls the number of bus turnaround cycles added between read and write accesses to prevent bus contention on the external memory data bus Turnaround time IDCY x SMCLK period 0xF BANK READ WAIT STATE CONTROL REGISTERS 0 5 Register Address R W Description Reset Value SMBWSTRDR0 0x4F000004 R W Bank0 read wait state control register 0x1F SMBWSTRDR1 0x4F000024 R W Bank1 read ...

Page 127: ...ate Defaults to 11111 at reset For SRAM the WSTWR field controls the number of wait states for write accesses and the external wait assertion timing for writes Wait state time WSTWR x SMCLK period WSTWR does not apply to read only devices such as ROM 0x1F BANK OUTPUT ENABLE ASSERTION DELAY CONTROL REGISTERS 0 5 Register Address R W Description Reset Value SMBWSTOENR0 0x4F00000C R W Bank0 output en...

Page 128: ...gister 0x2 SMBWSTWENR2 0x4F000050 R W Bank2 write enable assertion delay control register 0x2 SMBWSTWENR3 0x4F000070 R W Bank3 write enable assertion delay control register 0x2 SMBWSTWENR4 0x4F000090 R W Bank4 write enable assertion delay control register 0x2 SMBWSTWENR5 0x4F0000B 0 R W Bank5 write enable assertion delay control register 0x2 Bit Description Initial State 31 4 Read undefined Write ...

Page 129: ... Signal always HIGH 1 Signal active for asynchronous and synchronous write accesses default 0x1 BurstLenWrite 19 18 Burst transfer length Sets the number of sequential transfers that the burst device supports for a write 00 4 transfer burst default 01 Reserved 10 Reserved 11 Reserved 0x0 SyncWriteDev 17 0 Asynchronous device default 1 Synchronous device 0x0 BMWrite 16 Burst mode write 0 Nonburst w...

Page 130: ...different values at reset for each bank For SMBCR0 reset value is set according to OM See table 1 4 See note in p5 17 Reserved 3 Reserved 0x0 WaitEn 2 External memory controller wait signal enable 0 The SMC is not controlled by the external wait signal default at reset 1 The SMC looks for the external wait input signal nWAIT 0x0 WaitPol 1 Polarity of the external wait input for activation 0 The nW...

Page 131: ...TYPE 5 0 DEMUXED OneNAND 1 MUXED OneNAND 0x0 BANK4TYPE 4 0 DEMUXED OneNAND 1 MUXED OneNAND 0x0 BANK3TYPE 3 0 DEMUXED OneNAND 1 MUXED OneNAND 0x0 BANK2TYPE 2 0 DEMUXED OneNAND 1 MUXED OneNAND 0x0 BANK1TYPE 1 0 DEMUXED OneNAND 1 MUXED OneNAND 0x0 0 Reserved 0x0 Note Type of bank0 OneNAND is determined by OM 4 2 signals See table 1 4 SMC STATUS REGISTER Register Address R W Description Reset Value SM...

Page 132: ...ster 0x3 Bit Description Initial State 31 2 Read undefined Write as zero 0x0 MemClkRatio 1 Defines the ratio of SMCLK to HCLK 0 SMCLK HCLK 1 SMCLK HCLK 2 0x1 SMClockEn 0 SMCLK enable 0 Clock only active during memory accesses 1 Clock always running Clock stopping saves power by stopping SMCLK when it is not required If clock stopping is enabled before the memory access the SMC stops SMCLK on the f...

Page 133: ...or example one bank for mobile SDRAM and one bank for mobile DDR Mobile DRAM controller has the following features Support little endian Mobile DDR SDRAM and Mobile SDRAM Supports 32 bit for SDRAM and 16 bit data bus interface for mDDR and DDR2 Address space up to 128Mbyte Supports 2 banks 2 nCS chip selection 16 bit Refresh Timer Self Refresh Mode support controlled by power management Programmab...

Page 134: ... products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Block Diagram Follow figure 6 1 shows the block diagram of Mobile DRAM Controller Figure 6 1 Mobile DRAM Controller Block Diagram ...

Page 135: ...ically issues a MRS command to the DRAM 8 Program the normal operational value auto refresh ducy cycle into the refresh timer 9 Program the INIT 1 0 of Control Register1 to 11b This automatically issues a EMRS command to the Mobile DRAM It s only needed for Mobile DRAM 10 Program the INIT 1 0 to 00b The controller enters the normal mode 11 The external DRAM is now ready for normal operation DDR2 I...

Page 136: ...d information herein are subject to change without notice 8 Issue a PALL pre charge all command Program the INIT 1 0 to 01b This automatically issues a PALL pre charge all cammand to the DRAM 9 Issue 2 or more auto refresh commands 10 Issue a MRS command with LOW to A8 to initialize device operation Program the INIT 1 0 to 10b BANKCON3 8 0b 11 Wait 200 clock after step 7 execute OCD Calibration 12...

Page 137: ...ks D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 BA0 BA1 LDQM UDQM A14 A15 DQM0 DQM1 SCKE SCLK SCKE SCLK nSCS0 nSRASn SCASn WE nSCS nSRAS nSCAS nWE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 ...

Page 138: ...e subject to change without notice Mobile DDR and DDR2 Memory Interface Examples A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM UDQM DQS0 DQS1 DQM0 DQM1 DQS0 DQS1 SCKE SCLK SCLKn CKE CK nCK nSCS0 nSRASn SCASn WE nSCS n...

Page 139: ...various DRAM memories like SDR mobile DDR and DDR2 tARFC and tRP are programmable so you can also control the tRAS period by using these parameters And the delay from RAS to CAS is determined by tRCD And CL CAS Latency is also programmable The timing diagram of CL CAS Latency is like figure 6 4 Figure 6 4 CL CAS Latency timing diagram DRAMC also needs tARFC timing parameter to control of the timin...

Page 140: ...SSOR 6 8 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 6 5 tARFC timing diagram ...

Page 141: ... 14 The bit width of RAS row address of bank 1 00 11 bit 01 12 bit 10 13 bit 11 14 bit 00b Reserved 13 Reserved 0b CASBW0 12 11 The bit width of CAS column address of bank 0 00 8 bit 01 9 bit 10 10 bit 11 11 bit 00b Reserved 10 Reserved 0b CASBW1 9 8 The bit width of CAS column address of bank 1 00 8 bit 01 9 bit 10 10 bit 11 11 bit 00b ADDRCFG0 7 6 Memory address configuration of 00 BA RAS CAS 01...

Page 142: ...on Should be set 3 100b Reserved 27 26 Should be 1 01b Reserved 25 8 Should be 1 0 BStop 7 Read Burst stop control 0 not support Read Burst Stop 1 support Read Burst Stop Note This function is only valid in mDDR interface 0b WBUF 6 Write buffer control 0 Disable 1 Enable note Disabling the write buffer will flush any stored values to the external DRAM memory 1b AP 5 Auto pre charge control 0 Enabl...

Page 143: ...001 10 clock1010 11 clock1011 12 clock 1100 13 clock1101 14 clock1110 15 clock1111 16 clock 1001b tARFC 19 16 Self refresh or Auto refresh to next command cycle time 0000 1 clock 0001 2 clock 0010 3 clock 0011 4 clock 0100 5 clock 0101 6 clock 0110 7 clock 0111 8 clock 1000 9 clock 1001 10 clock1010 11 clock1011 12 clock 1100 13 clock1101 14 clock1110 15 clock1111 16 clock 1001b Reserved 15 6 Rese...

Page 144: ...k address for EMRS 10b Reserved 29 23 Should be 0 0000000b DS 22 21 DS Driver Strength for EMRS 00b Reserved 20 19 Should be 0 00b PASR 18 16 PASR Partial Array Self Refresh for EMRS 000b BA 15 14 Bank address for MRS 0b Reserved 15 7 Should be 0 000000000b CAS Latency 6 4 CAS Latency for MRS 00 Reserved 01 1 clock 10 2 clock 11 3 clock 000b Burst Type 3 DRAM Burst Type Read Only Only support sequ...

Page 145: ...19 Refer to DDR2 spec 000b Rtt 22 18 00 ODT disable 01 75ohm 10 150ohm 11 50ohm 00b D I C 17 0 Full strength 1 Reduced strength 0b DLL enable 16 0 Enable 1 Disable 0b Reserved 15 13 Should be 0 000b Active Power down exit time 12 0 Fast exit 1 Slow exit 0b WR 11 9 Write recovery for auto pre charge 000b DLL Reset 8 0 No 1 Yes 0b TM 7 0 Normal 1 Test 0b CAS Latency 6 4 CAS Latency for MRS 00 Reserv...

Page 146: ...to change without notice 3 DDR2 memory EMRS 2 31 16 PnBANKCON Bit Description Initial State BA 31 30 Bank address for EMRS 10b Reserved 29 24 Should be 0 000000b SRF 23 High Temperature Self Refresh Rate Enable 0 Disable 1 Enable 0b Reserved 22 20 Should be 0 000b DCC 19 0 Disable 1 Enable 0b PASR 18 16 PASR Partial Array Self Refresh for EMRS 2 000b 4 DDR2 memory EMRS 3 31 16 PnBANKCON Bit Descri...

Page 147: ...x 66 x 106 1029 0x0020 MOBILE DRAM WRITE BUFFER TIME OUT REGISTER A write to a enabling write buffer loads the value in the timeout register into timeout down counter of the buffer When the timeout counter reached 0 the contents of write buffer is flushed to the external DRAM The down counter is clocked HCLK Writing a value of 0 in the TIMEOUT register disables the write buffer timeout function Re...

Page 148: ...SC MICROPROCESSOR 6 16 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NOTES ...

Page 149: ...d the GPC5 6 7 configuration should be set to use IROM boot and select proper nand device type Nand Boot written below is boot device in IROM boot Refer to IROM application Note for more information S3C2451 supports nand boot by using IROM boot mode 7 2 FEATURES NAND flash controller features include 1 Auto boot by The boot code is transferred into 8 KB Steppingstone after reset After the boot cod...

Page 150: ... LOADER FUNCTION Stepping Stone 64KB Buffer NAND FLASH Controller NAND FLASH Memory Special Function Registers REGISTERS AUTO BOOT CORE ACCESS Boot Code USER ACCESS Figure 7 2 NAND Flash Controller Boot Loader Block Diagram During reset the IROM gets the information about the adopted NAND flash memory by using the pin status of GPC5 6 7 refer to PIN CONFIGURATION In case of POR Power On Reset or s...

Page 151: ...age Address Cycle GPC7 2 GPC6 1 GPC5 0 MMC MoviNAND iNand 0 0 0 Reserved 0 0 1 3 0 1 0 512 4 0 1 1 4 1 0 0 2048 5 1 0 1 Nand 4096 5 1 1 0 Above configuration is applicable when NAND Flash is used as booting memory in IROM boot mode If NAND Flash is not used as boot memory the configuration can be changed by setting NFCON SFR NFCONF 0x4E000000 PageSize PageSize_Ext and AddrCycle are fields in NFCON...

Page 152: ...o the command register NFCMMD the NAND Flash Memory command cycle 2 Writing to the address register NFADDR the NAND Flash Memory address cycle 3 Writing to the data register NFDATA write data to the NAND Flash Memory write cycle 4 Reading from the data register NFDATA read data from the NAND Flash Memory read cycle 5 Reading main ECC registers and Spare ECC registers NFMECCD0 1 NFSECCD read data f...

Page 153: ...ity code generation Both 4bit and 8bit ECC modules can be used for only 512 bytes ECC parity code generation 4 bit and 8bit ECC modules generate the parity codes for each 512 byte However 1 bit ECC modules generate parity code per byte lane separately 7 10 1 ECC module features ECC generation is controlled by the ECC Lock MainECCLock SpareECCLock bit of the Control register When ECCLock is Low ECC...

Page 154: ...alid error status values NOTE NFSECCD is for the ECC value in spare area Usually the user will write the ECC value generated from main data area to Spare area which value will be the same as NFMECC0 1 7 10 3 4 BIT ECC PROGRAMMING GUIDE ENCODING 1 To use 4 bit ECC in software mode set the MsgLength to 0 512 byte message length and set the ECCType to 1 enable 4 bit ECC ECC module generates ECC parit...

Page 155: ...FCONT 5 bit as 1 and have to clear the MainECCLock NFCONT 7 bit to 0 Unlock before read data MainECCLock NFCONT 7 bit controls whether ECC Parity code is generated or not 7 Whenever data is read the 4 bit ECC module generates ECC parity code internally 8 After you complete read 24 byte you have to read parity codes 4 bit ECC module needs parity codes to detect whether error bits are or not So you ...

Page 156: ...uld be cleared before InitMECC 2 Whenever data is read the MLC ECC module generates ECC parity code internally 3 After you complete the reading of 512 byte data not including spare area data you must set the MainECCLock NFCONT 7 bit to 1 Lock and have to read parity codes 8bit ECC module needs parity codes to detect whether error bits exists or not So you have to read the ECC parity code of 512 by...

Page 157: ...fications and information herein are subject to change without notice cycles to find any error During this time you can continue reading main data from external NAND flash memory ECCDecDone NFSTAT 6 can be used to check whether ECC decoding is completed or not 9 When ECCDecDone NFSTAT 6 is set 1 NF8ECCERR0 indicates whether error bit exist or not If any error exists you can fix it by referencing N...

Page 158: ...ange without notice 7 11 Memory mapping NAND boot and Other boot SRAM 8KB SDRAM nSCS1 SDRAM nSCS0 SROM nRCS5 SROM nRCS4 SROM nRCS3 SROM nRCS2 SROM nRCS1 SROM nRCS0 Using OneNAND for boot ROM SRAM 8KB SDRAM nSCS1 SDRAM nSCS0 SROM nRCS5 SROM nRCS4 ROM nRCS3 SROM nRCS2 SROM nRCS1 Internal iROM Using iROM for boot ROM MPORT1 MPORT0 0x1800_0000 0x0000_0000 0x0800_0000 0x1000_0000 0x2000_0000 0x2800_000...

Page 159: ...re not yet available Specifications and information herein are subject to change without notice 7 12 NAND FLASH MEMORY CONFIGURATION Figure 7 6 A 8 bit NAND Flash Memory Interface Block Diagram NOTE NAND CONTROLLER can support to control two nand flash memories NAND CS Other BOOT nFCE NAND CONTROLLER CS0 Configurable nRCS 1 NAND CONTROLLER CS1 Configurable If you want NAND BOOT by IROM nFCE must b...

Page 160: ...se 0x24 R W 0x0000_0000 NFEBLK Programmable end block address register Base 0x28 R W 0x0080_001D NFSTAT NAND status registet Base 0x2C R 0xXXXX_XXXX NFECCERR0 ECC error status0 register Base 0x30 R 0x0000_0000 NFECCERR1 ECC error status1 register Base 0x34 R 0xXXXX_XXXX NFMECC0 Generated ECC status0 register Base 0x38 R 0xXXXX_XXXX NFMECC1 Generated ECC status1 register Base 0x3C R 0xXXXX_XXXX NFS...

Page 161: ...be used 00 1 bit ECC 10 4 bit ECC 01 8 bit ECC Note Don t confuse the value of 4 bit ECC and 8 bit ECC H W Set CfgBootEcc Reserved 22 15 Reserved 000000000 TACLS 14 12 CLE ALE duration setting value 0 7 Duration HCLK x TACLS 001 Reserved 11 Reserved 0 TWRPH0 10 8 TWRPH0 duration setting value 0 7 Duration HCLK x TWRPH0 1 000 Reserved 7 Reserved 0 TWRPH1 6 4 TWRPH1 duration setting value 0 7 Durati...

Page 162: ...r of Address cycle of NAND Flash memory When Page Size is 512 Bytes 0 3 address cycle 1 4 address cycle When page size is 2K or 4K 0 4 address cycle 1 5 address cycle This bit is determined by OM 1 pin on reset and wake up time from sleep mode This bit can be changed by software later H W Set CfgAddrCycle BusWidth 0 This bit indicates the I O bus width of NAND Flash Memory The value of BusWidth me...

Page 163: ...leared by software When it is set to 1 the area setting in NFSBLK 0x4E000020 to NFEBLK 0x4E000024 is unlocked and except this area write or erase command will be invalid and only read command is valid When you try to write or erase locked area the illegal access will be occurred NFSTAT 5 bit will be set If the NFSBLK and NFEBLK are same entire area will be locked 0 Soft Lock 16 Soft Lock configura...

Page 164: ...ck 7 Lock Main area ECC generation 0 Unlock Main area ECC 1 Lock Main area ECC Main area ECC status register is NFMECC0 1 0x4E000034 38 1 SpareECCLock 6 Lock Spare area ECC generation 0 Unlock Spare ECC 1 Lock Spare ECC Spare area ECC status register is NFSECC 0x4E00003C 1 InitMECC 5 1 Initialize main area ECC decoder encoder write only 0 InitSECC 4 1 Initialize spare area ECC decoder encoder writ...

Page 165: ...er 0x00 NFCMMD Bit Description Initial State Reserved 31 8 Reserved 0x00 NFCMMD 7 0 NAND Flash memory command value 0x00 7 13 5 ADDRESS REGISTER Register Address R W Description Reset Value NFADDR 0x4E00000C R W NAND Flash address set register 0x0000XX00 REG_ADDR Bit Description Initial State Reserved 31 8 Reserved 0x00 NFADDR 7 0 NAND Flash memory address value 0x00 7 13 6 DATA REGISTER Register ...

Page 166: ...ODULE FEATURES 0x00000000 NFMECCD0 Bit Description Initial State Reserved 31 24 Not used 0x00 ECCData1 23 16 ECC1 for I O 7 0 0x00 Reserved 15 8 Not used 0x00 ECCData0 7 0 ECC0 for I O 7 0 0x00 NOTE Only word access is valid NFMECCD1 Bit Description Initial State Reserved 31 24 Not used 0x00 ECCData3 23 16 ECC3 for I O 7 0 0x00 Reserved 15 8 Not used 0x00 ECCData2 7 0 ECC2 for I O 7 0 0x00 7 13 8 ...

Page 167: ... start and end address When the Soft lock or Lock tight is enabled and the Start and End address has same value Entire area of NAND flash will be locked 0x000000 NFSBLK Bit Description Initial State Reserved 31 24 Reserved 0x00 SBLK_ADDR2 23 16 The 3rd block address of the block erase operation 0x00 SBLK_ADDR1 15 8 The 2nd block address of the block erase operation 0x00 SBLK_ADDR0 7 0 The 1st bloc...

Page 168: ...s and information herein are subject to change without notice The NFSLK and NFEBLK can be changed while Soft lock bit NFCONT 16 is enabled But cannot be changed when Lock tight bit NFCONT 17 is set when Lock tight 1 or SoftLock 1 NAND flash memory Locked area Read only Prorammable Readable Area Locked area Read only NFSBLK Address High Low NFEBLK 1 NFEBLK NFSBLK Locked Area Read only When NFSBLK N...

Page 169: ...et and issue interrupt if enabled The NFMLCBITPT NFMLCL0 and NFMLCEL1 have valid values To clear this write 1 1 4 bit ECC or 8 bit ECC decoding is completed 0 IllegalAccess 5 Once Soft Lock or Lock tight is enabled The illegal access program erase to the memory makes this bit set 0 illegal access is not detected 1 illegal access is detected 0 RnB_TransDetect 4 When RnB low to high transition is oc...

Page 170: ...Description Initial State Reserved 31 25 Reserved 0x00 SErrorDataNo 24 21 In spare area Indicates which number data is error 0011 SErrorBitNo 20 18 In spare area Indicates which bit is error 111 MErrorDataNo 17 7 In main data area Indicates which number data is error 0x7FF MErrorBitNo 6 4 In main data area Indicates which bit is error 111 SpareError 3 2 Indicates whether spare area bit fail error ...

Page 171: ...4 bit MECC Error 28 26 4 bit ECC decoding result 000 No error 001 1 bit error 010 2 bit error 011 3 bit error 100 4 bit error 101 Uncorrectable 11x reserved Note If it happens that there are more errors than 4 bits 4 bit ECC module does not ensure right detection 000 2nd Bit Error Location 25 16 Error byte location of 2nd bit error 0x00 Reserved 15 10 Reserved 1st Bit Error Location 9 0 Error byte...

Page 172: ...a 7 0 0xXX NFMECC1 Bit Description Initial State Reserved 31 0 Reserved 0x00000000 NOTE The NAND flash controller generate NFMECC when read or write main area data while the MainECCLock NFCONT 7 bit is 0 Unlock When ECCType is 4 bit ECC NFMECC0 Bit Description Initial State 4th Parity 31 24 4th Check Parity generated from main area 0x00 3rd Parity 23 16 3rd Check Parity generated from main area 0x...

Page 173: ...served 31 16 Reserved 0xXXXX SECC0_1 15 8 Spare area ECC1 Status for I O 7 0 0xXX SECC0_0 7 0 Spare area ECC0 Status for I O 7 0 0xXX NOTE The NAND flash controller generate NFSECC when read or write spare area data while the SpareECCLock NFCONT 6 bit is 0 Unlock 7 13 14 4 BIT ECC ERROR PATTEN REGISTER Register Address R W Description Reset Value NFMLCBITPT 0x4E000040 R NAND Flash 4 bit ECC Error ...

Page 174: ...sy b 0 MLC8ECCReady 30 ECC Ready bit b 1 MLC8FreePage 29 Inidicates the page data read from NAND flash has all FF value b 0 MLC8ECCError 28 25 8 bit ECC decoding result 0000 No error 0001 1 bit error 0010 2 bit error 0011 3 bit error 0100 4 bit error 0101 5 bit error 0110 6 bit error 0111 7 bit error 1000 8 bit error 1001 Uncorrectable 1010 1111 reserved b 0000 MLC8ErrLocation2 24 15 Error byte lo...

Page 175: ...ta are not yet available Specifications and information herein are subject to change without notice MLCErrLocation8 31 22 Error byte location of 8th bit error 0x000 Reserved 21 Reserved b 0 MLCErrLocation7 20 11 Error byte location of 7th bit error 0x000 Reserved 10 Reserved b 0 MLCErrLocation6 9 0 Error byte location of 6th bit error 0x000 Note These values are updated when ECCDecodeDone NFSTAT 6...

Page 176: ...k Parity generated from main area 512 byte 0xXX 1st Parity 7 0 1st Check Parity generated from main area 512 byte 0xXX NFM8ECC1 Bit Description Initial State 8th Parity 31 24 8th Check Parity generated from main area 512 byte 0xXX 7th Parity 23 16 7th Check Parity generated from main area 512 byte 0xXX 6th Parity 15 8 6th Check Parity generated from main area 512 byte 0xXX 5th Parity 7 0 5th Check...

Page 177: ...rn register0 for data 7 0 0x0000_0000 NFMLC8BITPT1 0x4E00_0064 R NAND Flash 8 bit ECC Error Pattern register1 for data 7 0 0x0000_0000 NFMLC8BITPT0 Bit Description Initial State 4th Error bit pattern 31 24 4th Error bit pattern 0x00 3rd Error bit pattern 23 16 3rd Error bit pattern 0x00 2nd Error bit pattern 15 8 2nd Error bit pattern 0x00 1st Error bit pattern 7 0 1st Error bit pattern 0x00 NFMLC...

Page 178: ...C MICROPROCESSOR 7 30 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NOTES ...

Page 179: ... enable bit mode select True IDE or PC card bit The PC card controller features The PC card controller has 2 half word 16bits write buffers 4 half word 16bits read buffers The PC card controller has 5 word sized 32bits Special Function Registers 3 timing configuration registers Attribute memory Common memory I O interface 1 status control configuration register 1 interrupt source mask register Tim...

Page 180: ... enable strobe PC card mode lower byte enable strobe True IDE mode chip selection nCS0 nCE2_CF nRCS 3 1 O Card enable strobe PC card mode higher byte enable strobe True IDE mode chip selection nCS1 nREG_CF EINT 21 1 O Register in CF card strobe PC card mode It is used for accessing register in CF card True IDE mode DMA Acknowledge nOE_CF nOE_CF 1 O Output enable strobe PC card mode output enable s...

Page 181: ...able Specifications and information herein are subject to change without notice BLOCK DIAGRAM Top Level Block Diagram A top level block diagram of the overall CF controller is shown below in Figure 8 1 CF card Output pad enble IDE mode Card power enable AHB master IF AHB slave IF HADDR CF controller AHB Back born Top level SFR PC card controller ATA controller Address decoder Figure 8 1 CF Control...

Page 182: ...ject to change without notice PC Card Controller Block Diagram A top level block diagram of the PC card controller is shown below in Figure 8 2 PC card controller Block HRDATA HWDATA ADDR nWE nOE nIOWR nIORD nREG WDATA 11 16 nCE1 nCE2 nWAIT nCD Write_dir 32 32 RDATA AHB ADDR AHB Control signal Main Controller Data Buffer Controller 16 Top Controller Special Function Register Address decoder Addres...

Page 183: ...hange without notice ATA Controller Block Diagram A top level block diagram of the ATA controller is shown below in Figure 8 3 ATA interface control interrupt Data control Data control PIO data 16 16 ATA write data ATA read data AHB slave IF AHB master IF ATA interface ATA controller Block CRC Transfer control Interrupt source Control Status Register Configuration Register AHB Slave interface 16 F...

Page 184: ...on data and associated errata are not yet available Specifications and information herein are subject to change without notice TIMING DIAGRAM PC Card Mode SET UP IDLE COMMAND HOLD IDLE nCE1 nCE2 IORD IOWR nOE nWE Figure 8 4 PC Card State Definition Area Attribute memory I O interface Common memory min Max nS Set up 30 70 30 Command 150 165 150 Hold 30 20 20 S C H 300 290 ...

Page 185: ...ect to change without notice True IDE Mode PIO Mode PIO Mode Waveform t2 t1 teoc t1 CS0 CS1 DA 2 0 DIOR DIOW WR DD 15 0 or DD 7 0 RD DD 15 0 or DD 7 0 Figure 8 5 PIO Mode Waveform Timing Parameter In PIO Mode Table 8 1 Timing Parameter Each PIO Mode PIO mode PIO 0 PIO 1 PIO 2 PIO 3 PIO 4 T1 70 50 30 30 25 T2 16bit 165 125 100 80 70 T2 Register 8 bit 290 290 290 80 70 TEOC 20 15 10 10 10 T1 T2 TEOC...

Page 186: ...thout notice SPECIAL FUNCTION REGISTERS Memory Map Memory Map Diagram HSEL_SLV_Base 0x4B80_0000 HSEL_SLV_Base 0 x 1000 SFR_Base HSEL_SLV_Base 0 x 1800 SFR_Base 0 x 0188 SFR Area Common Memory Area I O Area Attribute Memory Area Reserved Area ATA controlller SFRs Reserved Area PC card controller SFRs Reserved Area MUX_REG HSEL_SLV_Base 0 x 0800 HSEL_SLV_Base 0 x 0000 SFR_Base 0 x 0100 SFR_Base 0 x ...

Page 187: ...CARD_COMM 0x4B801830 PC card common memory area operation timing config regiseter 0x00031909 Reserved 0x00FC Reserved area ATA_BASE 0x4B801900 ATA controller base address ATA_CONTROL 0x4B801900 ATA enable and clock down status 0x00000002 ATA_STATUS 0x4B801904 ATA status 0x00000000 ATA_COMMAND 0x4B801908 ATA command 0x00000000 ATA_SWRST 0x4B80190C ATA software reset 0x00000000 ATA_IRQ 0x4B801910 AT...

Page 188: ... ATA PIO device Feature Error register 0x00000000 ATA_PIO_SCR 0x4B80195C ATA PIO sector count register 0x00000000 ATA_PIO_LLR 0x4B801960 ATA PIO device LBA low register 0x00000000 ATA_PIO_LMR 0x4B801964 ATA PIO device LBA middle register 0x00000000 ATA_PIO_LHR 0x4B801968 ATA PIO device LBA high register 0x00000000 ATA_PIO_DVR 0x4B80196C ATA PIO device register 0x00000000 ATA_PIO_CSD 0x4B801970 ATA...

Page 189: ...REGISTER DESCRIPTIONS MUX_REG REGISTER Register Address R W Description Reset Value MUX_REG 0x4B801800 R W MUX_REG is used to set the internal mode output port enable card power enable 0x0000_0006 MUX_REG Bit Description R W Reset Value Reserved 31 3 Reserved bits R 0x0 OUTPUT_EN 2 Output port enable 0 output port enable 1 output port disable R W 0x1 CARDPWR_EN 1 Card power supply enable 0 card po...

Page 190: ...et in PC card mode 0 no reset 1 reset R W 0x0 INT_SEL 12 Card interrupt request type select 0 edge triggering 1 level triggering R W 0x0 nWAIT_EN 11 nWAIT from CF card enable 0 disable always ready 1 enable R W 0x1 DEVICE_ATT 10 Device type is 16bits or 8bits Attribute memory area 0 8 bit device 1 16 bit device R W 0x1 DEVICE_ COMM 9 Device type is 16bits or 8bits Common memory area 0 8 bit device...

Page 191: ...register 0x0000_0600 PCCARD_INT Bits Description R W Reset Value Reserved 31 11 Reserved bits R 0x0 INTMSK_ ERR_N 10 Interrupt mask bit of no card error 0 unmask 1 mask R W 0x1 INTMSK_IREQ 9 Interrupt mask bit of CF card interrupt request 0 unmask 1 mask R W 0x1 INTMSK_CD 8 Interrupt mask bit of CF card detect 0 unmask 1 mask R W 0x0 Reserved 7 3 Reserved bits R 0x0 INTSRC_ ERR_N 2 When host acces...

Page 192: ...R W 0x03 Reserved 15 Reserved bits R 0x0 CMND_ATTR 14 8 Command state timing of attribute memory area Command time HCLK time CMND_ATTR 1 R W 0x19 Reserved 7 Reserved bits R 0x0 SETUP_ATTR 6 0 Setup state timing of attribute memory area Setup time HCLK time SETUP_ATTR 1 R W 0x09 PCCARD_I O REGISTER Register Address R W Description Reset Value PCCARD_I O 0x4B80182C R W PCCARD_I O is used to set the ...

Page 193: ...iption Reset Value PCCARD_ COMM 0x4B801830 R W PCCARD_COMM is used to set the card access timing 0x0003_1909 PCCARD_COMM Bits Description R W Reset Value Reserved 31 23 Reserved bits R 0x0 HOLD_COMM 22 16 Hold state timing of common memory area Hold time HCLK time HOLD_COMM 1 R W 0x03 Reserved 15 Reserved bits R 0x0 CMND_COMM 14 8 Command state timing of common memory area Command time HCLK time C...

Page 194: ...r clock down This bit is asserted in idle state when ATA_CONTROL bit 0 is zero 0 not ready for clock down 1 ready for clock down R 0x1 ata_enable 0 ATA enable 0 ATA is disabled and preparation for clock down maybe in progress 1 ATA is enabled R W 0x0 ATA_STATUS REGISTER Register Address R W Description Reset Value ATA_STATUS 0x4B801904 R ATA Status register 0x0000_0000 ATA_STATUS Bits Description ...

Page 195: ...able in idle state 10 command abort 11 command continue Only available in transfer pause After CPU commands ABORT make a software reset by ATA_SWRST to clear the leftover values of internal registers R W 0x0 The STOP command is a thing which use when CPU wants to pause upon data transfer When the CPU wants to judge the transmission data is valid or not while transfer transmits for a moment To send...

Page 196: ... reset for all ATA host module After software reset to continue transfer user must configure all registers of host controller and device registers R W 0x0 ATA_IRQ REGISTER Register Address R W Description Reset Value ATA_IRQ 0x4B801910 R W ATA IRQ register 0x0000_0000 ATA_IRQ Bits Description R W Reset Value Reserved 31 5 Reserved bits R 0x0 sbuf_empty_int 4 When source buffer is empty CPU can cle...

Page 197: ... Description Reset Value ATA_IRQ_MASK 0x4B801914 R W ATA IRQ MASK register 0x0000_001F ATA_IRQ_MASK Bits Description R W Reset Value Reserved 31 5 Reserved bits R 0x0 mask_sbut_ empty_int 4 Interrupt mask bit of source buffer empty 0 unmask 1 mask R W 0x1 mask_tbuf_ full_int 3 Interrupt mask bit of target buffer full 0 unmask 1 mask R W 0x1 mask_atadev_ irq_int 2 Interrupt mask bit of ATA device i...

Page 198: ...ce buffer repeatedly To avoid this after 1st source buffer is empty the sbuf_empty_mode bit automatically goes to HIGH even though the default is 0 So user must make a command CONTINUE And then user don t want that the CPU dose not interfere the change of the next source buffer address set 0 at the bit 8 before after the next base address and size R W 0x0 tbuf_full_mode 7 Determines whether to con...

Page 199: ...ittle or big in 16bit data 0 little endian data 15 8 data 7 0 1 big endian data 7 0 data 15 8 R W 0x0 atadev_irq_al 5 Device interrupt signal level 0 active high 1 active low R W 0x0 dma_dir 4 DMA transfer direction 0 Host read data from device 1 Host write data to device R W 0x0 ata_class 3 2 ATA transfer class select 0 transfer class is PIO 1 transfer class is PIO DMA 2 3 reserved R W 0x0 ata_io...

Page 200: ..._t2 11 4 PIO timing parameter t2 DIOR Wn pulse width It shall not have zero value t2 HCLK time pio_t2 1 R W 0x23 pio_t1 3 0 PIO timing parameter t1 address valid to DIOR Wn t1 HCLK time pio_t1 1 R W 0x8 ATA_XFR_NUM REGISTER Register Address R W Description Reset Value ATA_XFR_NUM 0x4B801934 R W ATA Data Transfer Number register 0x0000_0000 ATA_XFR_NUM Bits Description R W Reset Value xfr_num 31 1 ...

Page 201: ...dress of track buffer 0x0000_0000 ATA_TBUF_ START Bits Description R W Reset Value track_buffer_ start 31 2 Start address of track buffer 4byte unit R W 0x00000000 Reserved 1 0 Reserved bits R 0x0 ATA_TBUF_SIZE REGISTER Register Address R W Description Reset Value ATA_TBUF_ SIZE 0x4B801940 R W Size of track buffer 0x0000_0000 ATA_TBUF_ SIZE Bits Description R W Reset Value track_buffer_ size 31 5 ...

Page 202: ...dress of source buffer 0x0000_0000 ATA_SBUF_ START Bits Description R W Reset Value src_buffer_start 31 2 Start address of source buffer 4byte unit R W 0x00000000 Reserved 1 0 Reserved bits R 0x0 ATA_SBUF_SIZE REGISTER Register Address R W Description Reset Value ATA_SBUF_ SIZE 0x4B801948 R W Size of source buffer 0x0000_0000 ATA_SBUF_ SIZE Bits Description R W Reset Value src_buffer_ size 31 5 Si...

Page 203: ..._adr 31 2 Current address of track buffer R W 0x00000000 Reserved 1 0 Reserved bits R 0x0 ATA_CADDR_SBUF REGISTER Register Address R W Description Reset Value ATA_CADDR_ SBUF 0x4B801950 R W Current address of source buffer 0x0000_0000 ATA_CADDR_ SBUF Bits Description R W Reset Value src_buf_cur_ adr 31 2 Current address of source buffer R W 0x00000000 Reserved 1 0 Reserved bits R 0x0 ATA_PIO_DTR R...

Page 204: ...ter W 0x00 NOTE pio_dev_fed can be read by accessing register ATA_PIO_RDATA ATA_PIO_SCR REGISTER Register Address R W Description Reset Value ATA_PIO_SCR 0x4B80195C W 8 bit PIO device sector count register 0x0000_0000 ATA_PIO_SCR Bits Description R W Reset Value Reserved 31 8 Reserved bits R 0x0 pio_dev_scr 7 0 8 bit PIO device sector count command block register W 0x00 NOTE pio_dev_scr can be rea...

Page 205: ...d block register W 0x00 NOTE pio_dev_lmr can be read by accessing register ATA_PIO_RDATA ATA_PIO_LMR REGISTER Register Address R W Description Reset Value ATA_PIO_LHR 0x4B801968 W 8 bit PIO device LBA high register 0x0000_0000 ATA_PIO_LHR Bits Description R W Reset Value Reserved 31 8 Reserved bits R 0x0 pio_dev_lhr 7 0 8 bit PIO LBA high command block register W 0x00 NOTE pio_dev_lhr can be read ...

Page 206: ...nd block register W 0x00 NOTE pio_dev_csd can be read by accessing register ATA_PIO_RDATA ATA_PIO_DAD REGISTER Register Address R W Description Reset Value ATA_PIO_DAD 0x4B801974 W 8 bit PIO device control alternate status register 0x0000_0000 ATA_PIO_DAD Bits Description R W Reset Value Reserved 31 8 Reserved bits R 0x0 pio_dev_dad 7 0 8 bit PIO device control alternate status control block regis...

Page 207: ... bits R 0x0 bus_state 2 0 18 16 3 b000 IDLE Another value is in operation R 0x00 Reserved 15 14 Reserved bits R 0x0 bus_fifo_rdpnt 13 8 bus fifo read pointer R 0x00 Reserved 7 6 Reserved bits R 0x0 bus_fifo_wrpnt 5 0 bus fifo write pointer R 0x00 ATA_FIFO_STATUS REGISTER Register Address R W Description Reset Value ATA_FIFO_ STATUS 0x4B801994 R ATA FIFO status register 0x0000_0000 ATA_FIFO_ STATUS...

Page 208: ...CROPROCESSOR 8 30 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NOTES ...

Page 209: ...al bus Each channel of DMA controller can perform data movements between devices in the system bus and or peripheral bus with no restrictions In other words each channel can handle the following four cases 1 both source and destination are in the system bus 2 source is in the system bus while destination is in the peripheral bus 3 source is in the peripheral bus while destination is in the system ...

Page 210: ... that if S W request mode is selected this DMA request sources have no meaning at all The 27 DMA sources for each channel are as follows Table 9 1 DMA request sources for each channel Bit Source Bit Source Bit Source Bit Source 0 SPI_0_TX 8 Reserved 16 Reserved 24 UART_2 1 1 SPI_0_RX 9 PWM Timer 17 nXDREQ0 25 UART_3 0 2 SPI_1_TX 10 Reserved 18 nXDREQ1 26 UART_3 1 3 SPI_1_RX 11 Reserved 19 UART_0 0...

Page 211: ...r burst are considered This operation is repeated until the counter CURR_TC becomes 0 in the whole service mode while performed only once in a single service mode The main FSM this FSM counts down the CURR_TC when the sub FSM finishes each of atomic operation In addition this main FSM asserts the INT REQ signal when CURR_TC becomes 0 and the interrupt setting of DCON 29 register is set to 1 In add...

Page 212: ... these protocols Basic DMA Timing The DMA service means paired Reads and Writes cycles during DMA operation which is one DMA operation The Figure 9 1 shows the basic Timing in the DMA operation of the S3C2451X The setup time and the delay time of XnXDREQ and XnXDACK are same in all the modes If the completion of XnXDREQ meets its setup time it is synchronized twice and then XnXDACK is asserted Aft...

Page 213: ...se two modes i e Demand and Handshake modes At the end of one transfer Single Burst transfer DMA checks the state of double synched XnXDREQ Demand mode If XnXDREQ remains asserted the next transfer starts immediately Otherwise it waits for XnXDREQ to be asserted Handshake mode If XnXDREQ is deasserted DMA deasserts XnXDACK in 2cycles Otherwise it waits until XnXDREQ is deasserted Caution XnXDREQ h...

Page 214: ... without notice Transfer Size There are two different transfer sizes single and Burst 4 DMA holds the bus firmly during the transfer of these chunk of data thus other bus masters can not get the bus Burst 4 Transfer Size 4 sequential Reads and 4 sequential Writes are performed in the Burst 4 Transfer NOTE Single Transfer size One read and one write are performed XSCLK XnXDREQ XnXDACK Read Read Rea...

Page 215: ...mode the operation continues while the XnXDREQ is asserted Demand mode and one pair of Read and Write Single transfer size is performed XnXDREQ XnXDACK XSCLK XnXDREQ XnXDACK Double synch Read Write Read Write Figure 9 4 Single service Demand Mode Single Transfer Size Single service Handshake Mode Single Transfer Size XnXDREQ XnXDACK XSCLK Read Write Read Write 2cycles Double synch Figure 9 5 Singl...

Page 216: ... DMA INITIAL SOURCE REGISTER DISRC Register Address R W Description Reset Value DISRC0 0x4B000000 R W DMA0 Initial Source Register 0x00000000 DISRC1 0x4B000100 R W DMA1 Initial Source Register 0x00000000 DISRC2 0x4B000200 R W DMA2 Initial Source Register 0x00000000 DISRC3 0x4B000300 R W DMA3 Initial Source Register 0x00000000 DISRC4 0x4B000400 R W DMA4 Initial Source Register 0x00000000 DISRC5 0x4...

Page 217: ...rol Register 0x00000000 DISRCC4 0x4B000404 R W DMA4 Initial Source Control Register 0x00000000 DISRCC5 0x4B000504 R W DMA5 Initial Source Control Register 0x00000000 DISRCC6 0x4B000604 R W DMA6 Initial Source Control Register 0x00000000 DISRCC7 0x4B000704 R W DMA7 Initial Source Control Register 0x00000000 DISRCn Bit Description Initial State LOC 1 Bit 1 is used to select the location of source 0 ...

Page 218: ...W DMA1 Initial Destination Register 0x00000000 DIDST2 0x4B000208 R W DMA2 Initial Destination Register 0x00000000 DIDST3 0x4B000308 R W DMA3 Initial Destination Register 0x00000000 DIDST4 0x4B000408 R W DMA4 Initial Destination Register 0x00000000 DIDST5 0x4B000508 R W DMA5 Initial Destination Register 0x00000000 DIDST6 0x4B000608 R W DMA6 Initial Destination Register 0x00000000 DIDST7 0x4B000708 ...

Page 219: ... 0x00000000 DIDSTC5 0x4B00050C R W DMA5 Initial Destination Control Register 0x00000000 DIDSTC6 0x4B00060C R W DMA6 Initial Destination Control Register 0x00000000 DIDSTC7 0x4B00070C R W DMA7 Initial Destination Control Register 0x00000000 DIDSTn Bit Description Initial State CHK_INT 2 Select interrupt occurrence time when auto reload is setting 0 interrupt will occur when TC reaches 0 1 interrupt...

Page 220: ...DMA controller waits for the de asserted DREQ before starting a new transfer If it sees the de asserted DREQ it de asserts DACK and waits for another asserted DREQ In contrast in the demand mode DMA controller does not wait until the DREQ is de asserted It just de asserts DACK and then starts another transfer if DREQ is asserted We recommend using handshake mode for external DMA request sources to...

Page 221: ...e bus to prevent starving of other bus masters 0 Reserved 26 25 Reserved for future use 00 PADDRFIX 24 APB Address fix control 0 increment 1 fix If you want to fix the APB address during burst operation set this bit to 1 0 Reserved 23 Reserved for future use 0 RELOAD 22 Set the reload on off option 0 auto reload is performed when a current value of transfer count becomes 0 i e all the required tra...

Page 222: ...0x4B000214 R DMA2 Count Register 000000h DSTAT3 0x4B000314 R DMA3 Count Register 000000h DSTAT4 0x4B000414 R DMA4 Count Register 000000h DSTAT5 0x4B000514 R DMA5 Count Register 000000h DSTAT6 0x4B000614 R DMA6 Count Register 000000h DSTAT7 0x4B000714 R DMA7 Count Register 000000h DSTATn Bit Description Initial State STAT 21 20 Status of this DMA controller 00 It indicates that DMA controller is re...

Page 223: ...ter 0x00000000 DCSRC6 0x4B000618 R DMA6 Current Source Register 0x00000000 DCSRC7 0x4B000718 R DMA7 Current Source Register 0x00000000 DCSRCn Bit Description Initial State CURR_SRC 30 0 Current source address for DMAn 0x00000000 CURRENT DESTINATION REGISTER DCDST Register Address R W Description Reset Value DCDST0 0x4B00001C R DMA0 Current Destination Register 0x00000000 DCDST1 0x4B00011C R DMA1 C...

Page 224: ...tion i e actual stop time can be detected by waiting until the channel on off bit DMASKTRIGn 1 is set to off This stop is actual stop 0 ON_OFF 1 DMA channel on off bit 0 DMA channel is turned off DMA request to this channel is ignored 1 DMA channel is turned on and the DMA request is handled This bit is automatically set to off if we set the DCONn 22 bit to no auto reload and or STOP bit of DMASKT...

Page 225: ...ister 000 DMAREQSEL4 0x4B000424 R W DMA4 Request Selection Register 000 DMAREQSEL5 0x4B000524 R W DMA5 Request Selection Register 000 DMAREQSEL6 0x4B000624 R W DMA6 Request Selection Register 000 DMAREQSEL7 0x4B000724 R W DMA7 Request Selection Register 000 DMAREQSELn Bit Description Initial State HWSRCSEL 5 1 Select DMA request source for each DMA Refer to the Table 11 1 on page 11 2 This bits co...

Page 226: ...ICROPROCESSOR 9 18 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NOTES ...

Page 227: ...er the UART IIC and others In these interrupt sources the UARTn and EINTn interrupts are OR ed to the interrupt controller When receiving multiple interrupt requests from internal peripherals and external interrupt request pins the interrupt controller requests FIQ or IRQ interrupt of the ARM926EJ core after the arbitration procedure The arbitration procedure depends on the hardware priority logic...

Page 228: ...e Specifications and information herein are subject to change without notice The interrupt controller has two groups of interrupt sources and first group has always higher priority than the other group Actually we made this interrupt controller using by two interrupt controllers The nRIQ of ARM926EJ is connected with AND of nIRQs of each interrupt controller The nFIQ is just same Figure 10 2 Inter...

Page 229: ...rce pending register SRCPND and interrupt pending register INTPND These pending registers indicate whether or not an interrupt request is pending When the interrupt sources request interrupt service the corresponding bits of SRCPND register are set to 1 and at the same time only one bit of the INTPND register is set to 1 automatically after arbitration procedure If interrupts are masked the corres...

Page 230: ... NONE Reserved ARB11 NONE Reserved ARB10 NONE Reserved ARB10 NONE Reserved ARB10 NONE Reserved ARB10 NONE Reserved ARB10 NONE Reserved ARB10 NONE Reserved ARB9 NONE Reserved ARB9 NONE Reserved ARB9 NONE Reserved ARB9 NONE Reserved ARB9 NONE Reserved ARB9 NONE Reserved ARB8 NONE Reserved ARB8 NONE Reserved ARB8 NONE Reserved ARB8 NONE Reserved ARB8 NONE Reserved ARB8 NONE Reserved ARB7 NONE Reserve...

Page 231: ...gh Speed SDMMC 0 interrupt ARB3 INT_SDI1 High Speed SDMMC 1 interrupt ARB3 INT_CFCON CFCON interrupt ARB3 INT_UART3 UART3 Interrupt ERR RXD and TXD ARB3 INT_DMA DMA channel 8 interrupt DMA0 DMA7 ARB3 INT_LCD LCD interrupt LCD Frame FIFO i80 interrupts ARB3 INT_UART2 UART2 Interrupt ERR RXD and TXD ARB2 INT_TIMER4 Timer4 interrupt ARB2 INT_TIMER3 Timer3 interrupt ARB2 INT_TIMER2 Timer2 interrupt AR...

Page 232: ...zation data and associated errata are not yet available Specifications and information herein are subject to change without notice INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters six first level arbiters and one second level arbiter as shown in Figure 10 2 below Figure 10 3 Priority Generating Block ...

Page 233: ...B_SEL bits are 10b the priority order is REQ0 REQ3 REQ4 REQ1 REQ2 and REQ5 If ARB_SEL bits are 11b the priority order is REQ0 REQ4 REQ1 REQ2 REQ3 and REQ5 Note that REQ0 of an arbiter always has the highest priority and REQ5 has the lowest one In addition by changing the ARB_SEL bits we can rotate the priority of REQ1 to REQ4 Here if ARB_MODE bit is set to 0 ARB_SEL bits are not automatically chan...

Page 234: ...request 0x00000000 INTMOD 1 0X4A000004 R W Interrupt mode regiseter for group 1 0 IRQ mode 1 FIQ mode 0x00000000 INTMSK1 0X4A000008 R W Determine which interrupt source of group 1is masked The masked interrupt source will not be serviced 0 Interrupt service is available 1 Interrupt service is masked 0xFFFFFFFF 0X4A00000C INTPND1 0X4A000010 R W Indicate the interrupt request status for group 1 0 Th...

Page 235: ...y set by the interrupt sources regardless of the masking bits in the INTMASK register In addition the SRCPND register is not affected by the priority logic of interrupt controller In the interrupt service routine for a specific interrupt source the corresponding bit of the SRCPND register has to be cleared to get the interrupt request from the same source correctly If you return from the ISR witho...

Page 236: ...Requested 0 INT_SPI0 22 0 Not requested 1 Requested 0 INT_SDI0 21 0 Not requested 1 Requested 0 INT_SDI1 20 0 Not requested 1 Requested 0 INT_CFCON 19 0 Not requested 1 Requested 0 INT_UART3 18 0 Not requested 1 Requested 0 INT_DMA 17 0 Not requested 1 Requested 0 INT_LCD 16 0 Not requested 1 Requested 0 INT_UART2 15 0 Not requested 1 Requested 0 INT_TIMER4 14 0 Not requested 1 Requested 0 INT_TIM...

Page 237: ...n herein are subject to change without notice SOURCE PENDING SRCPND 2 REGISTER FOR GROUP2 CONTINUED SRCPND 1 Bit Description Initial State INT_I2S1 7 0 Not requested 1 Requested 0 INT_I2S0 6 0 Not requested 1 Requested 0 INT_PCM1 5 0 Not requested 1 Requested 0 INT_PCM0 4 0 Not requested 1 Requested 0 Reserved 3 0 Not requested 1 Requested 0 Reserved 2 0 Not requested 1 Requested 0 INT_IIC1 1 0 No...

Page 238: ... W Interrupt mode regiseter for group 1 0 IRQ mode 1 FIQ mode 0x00000000 INTMOD 2 0X4A000044 R W Interrupt mode regiseter for group 2 0 IRQ mode 1 FIQ mode 0x00000000 NOTE If an interrupt mode is set to FIQ mode in the INTMOD register FIQ interrupt will not affect both INTPND and INTOFFSET registers In this case the two registers are valid only for IRQ mode interrupt source INTMOD1 Bit Description...

Page 239: ...herein are subject to change without notice nBATT_FLT 7 0 IRQ 1 FIQ 0 INT_CAM 6 0 IRQ 1 FIQ 0 EINT8_23 5 0 IRQ 1 FIQ 0 EINT4_7 4 0 IRQ 1 FIQ 0 EINT3 3 0 IRQ 1 FIQ 0 EINT2 2 0 IRQ 1 FIQ 0 EINT1 1 0 IRQ 1 FIQ 0 EINT0 0 0 IRQ 1 FIQ 0 INTMOD2 Bit Description Initial State INT_I2S1 7 0 IRQ 1 FIQ 0 INT_I2S0 6 0 IRQ 1 FIQ 0 INT_PCM1 5 0 IRQ 1 FIQ 0 INT_PCM0 4 0 IRQ 1 FIQ 0 Reserved 3 0 IRQ 1 FIQ 0 Reserv...

Page 240: ...ch interrupt source of group 2 is masked The masked interrupt source will not be serviced 0 Interrupt service is available 1 Interrupt service is masked 0xFFFFFFFF INTMSK1 Bit Description Initial State INT_ADC 31 0 Service available 1 Masked 1 INT_RTC 30 0 Service available 1 Masked 1 INT_SPI1 29 0 Service available 1 Masked 1 INT_UART0 28 0 Service available 1 Masked 1 INT_IIC0 27 0 Service avail...

Page 241: ...AM 6 0 Service available 1 Masked 1 EINT8_23 5 0 Service available 1 Masked 1 EINT4_7 4 0 Service available 1 Masked 1 EINT3 3 0 Service available 1 Masked 1 EINT2 2 0 Service available 1 Masked 1 EINT1 1 0 Service available 1 Masked 1 EINT0 0 0 Service available 1 Masked 1 INTMSK2 Bit Description Initial State INT_I2S1 7 0 Service available 1 Masked 1 INT_I2S0 6 0 Service available 1 Masked 1 INT...

Page 242: ...is register It clears only the bit positions of the INTPND register corresponding to those set to one in the data The bit positions corresponding to those that are set to 0 in the data remains as they are Register Address R W Description Reset Value INTPND1 0X4A000010 R W Indicate the interrupt request status for group 1 0 The interrupt has not been requested 1 The interrupt source has asserted th...

Page 243: ...t requested 1 Requested 0 INT_SDI0 21 0 Not requested 1 Requested 0 INT_SDI1 20 0 Not requested 1 Requested 0 INT_CFCON 19 0 Not requested 1 Requested 0 INT_UART3 18 0 Not requested 1 Requested 0 INT_DMA 17 0 Not requested 1 Requested 0 INT_LCD 16 0 Not requested 1 Requested 0 INT_UART2 15 0 Not requested 1 Requested 0 INT_TIMER4 14 0 Not requested 1 Requested 0 INT_TIMER3 13 0 Not requested 1 Req...

Page 244: ...ecifications and information herein are subject to change without notice INTPND2 Bit Description Initial State INT_I2S1 7 0 Not requested 1 Requested 0 INT_I2S0 6 0 Not requested 1 Requested 0 INT_PCM1 5 0 Not requested 1 Requested 0 INT_PCM0 4 0 Not requested 1 Requested 0 Reserved 3 0 Not requested 1 Requested 0 Reserved 2 0 Not requested 1 Requested 0 INT_IIC1 1 0 Not requested 1 Requested 0 IN...

Page 245: ...r group 1 0x00000000 INTOFFSET2 0X4A000054 R Indicate the IRQ interrupt request source for group 2 0x00000000 INT Source for group 1 The OFFSET Value INT Source for group 1 The OFFSET Value INT_ADC 31 INT_UART2 15 INT_RTC 30 INT_TIMER4 14 INT_SPI1 29 INT_TIMER3 13 INT_UART0 28 INT_TIMER2 12 INT_IIC0 27 INT_TIMER1 11 INT_USBH 26 INT_TIMER0 10 INT_USBD 25 INT_WDT AC97 9 INT_NAND 24 INT_TICK 8 INT_UA...

Page 246: ...errata are not yet available Specifications and information herein are subject to change without notice Reserved 23 INT_I2S1 7 Reserved 22 INT_I2S0 6 Reserved 21 INT_PCM1 5 Reserved 20 INT_PCM0 4 Reserved 19 Reserved 3 Reserved 18 Reserved 2 Reserved 17 INT_IIC1 1 Reserved 16 INT_2D 0 NOTE FIQ mode interrupt does not affect the INTOFFSET register as the register is available only for IRQ mode inte...

Page 247: ...ING SUBSRCPND REGISTER You can clear a specific bit of the SUBSRCPND register by writing a data to this register It clears only the bit positions of the SUBSRCPND register corresponding to those set to one in the data The bit positions corresponding to those that are set to 0 in the data remains as they are Register Address R W Description Reset Value SUBSRCPND 0X4A000018 R W Indicate the interrup...

Page 248: ...Not requested 1 Requested 0 SUBINT_DMA2 20 0 Not requested 1 Requested 0 SUBINT_DMA1 19 0 Not requested 1 Requested 0 SUBINT_DMA0 18 0 Not requested 1 Requested INT_DMA 0 SUBINT_LCD4 i80 I F 17 0 Not requested 1 Requested 0 SUBINT_LCD3 LCD Frame 16 0 Not requested 1 Requested 0 SUBINT_LCD2 LCD FIFO 15 0 Not requested 1 Requested 0 Reserved 14 Not used INT_LCD 0 Reserved 13 Reserved for future usag...

Page 249: ...as 27 bits each of which is related to an interrupt source If a specific bit is set to 1 the interrupt request from the corresponding interrupt source is not serviced by the CPU note that even in such a case the corresponding bit of the SUBSRCPND register is set to 1 If the mask bit is 0 the interrupt request can be serviced Register Address R W Description Reset Value INTSUBMSK 0X4A00001C R W Det...

Page 250: ... available 1 Masked 1 SUBINT_DMA2 20 0 Service available 1 Masked 1 SUBINT_DMA1 19 0 Service available 1 Masked 1 SUBINT_DMA0 18 0 Service available 1 Masked INT_DMA 1 SUBINT_LCD4 i80 I F 17 0 Service available 1 Masked 1 SUBINT_LCD3 LCD Frame 16 0 Service available 1 Masked 1 SUBINT_LCD2 LCD FIFO 15 0 Service available 1 Masked 1 Reserved 14 Not used INT_LCD 1 Reserved 13 Reserved for future usag...

Page 251: ..._MODE6 1 b0 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 2 ARB_MODE6 1 b1 000 REQ 0 1 2 3 4 5 001 REQ 1 2 3 4 5 0 010 REQ 2 3 4 5 0 1 011 REQ 3 4 5 0 1 2 100 REQ 4 5 0 1 2 3 101 REQ 5 0 1 2 3 4 0 ARB_MODE5 23 Arbiter 5 group priority mode selection 0 Fixed ends Rotate middle 0 ARB_SEL5 22 20 Arbiter 5 group priority order set 1 ARB_MODE5 1 b0 00 REQ 0 1 2 3 4 5 01 RE...

Page 252: ...tate middle 1 Rotate all 0 ARB_SEL2 10 8 Arbiter 2 group priority order set 1 ARB_MODE2 1 b0 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 2 ARB_MODE2 1 b1 000 REQ 0 1 2 3 4 5 001 REQ 1 2 3 4 5 0 010 REQ 2 3 4 5 0 1 011 REQ 3 4 5 0 1 2 100 REQ 4 5 0 1 2 3 101 REQ 5 0 1 2 3 4 0 ARB_MODE1 7 Arbiter 1 group priority mode selection 0 Fixed ends Rotate middle 1 Rotate all ...

Page 253: ... 1 2 3 4 5 001 REQ 1 2 3 4 5 0 010 REQ 2 3 4 5 0 1 011 REQ 3 4 5 0 1 2 100 REQ 4 5 0 1 2 3 101 REQ 5 0 1 2 3 4 0 ARB_MODE12 23 Arbiter 12 group priority mode selection 0 Fixed ends Rotate middle 0 ARB_SEL12 22 20 Arbiter 12 group priority order set 1 ARB_MODE12 1 b0 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 0 ARB_MODE11 19 Arbiter 11 group priority mode selection ...

Page 254: ...Rotate middle 1 Rotate all 0 ARB_SEL9 10 8 Arbiter 9 group priority order set 1 ARB_MODE9 1 b0 00 REQ 0 1 2 3 4 5 01 REQ 0 2 3 4 1 5 10 REQ 0 3 4 1 2 5 11 REQ 0 4 1 2 3 5 2 ARB_MODE9 1 b1 000 REQ 0 1 2 3 4 5 001 REQ 1 2 3 4 5 0 010 REQ 2 3 4 5 0 1 011 REQ 3 4 5 0 1 2 100 REQ 4 5 0 1 2 3 101 REQ 5 0 1 2 3 4 0 ARB_MODE8 7 Arbiter 8 group priority mode selection 0 Fixed ends Rotate middle 1 Rotate al...

Page 255: ...s not rotate 1 Priority rotate enable 1 ARB_UPDATE2 2 Arbiter 2 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 1 ARB_UPDATE1 1 Arbiter 1 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 1 ARB_UPDATE0 0 Arbiter 0 group priority rotate enable 0 Priority does not rotate 1 Priority rotate enable 1 PRIORITY_UPDATE2 Bit Description Initia...

Page 256: ... MICROPROCESSOR 10 30 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NOTES ...

Page 257: ...16 input output port Port F GPF 8 input output port Port G GPG 16 input output port Port H GPH 15 input output port Port J GPJ 16 input output port Port K GPK 16 input output port Port L GPL 15 input output port Port M GPM 2 input port Each port can be easily configured by software to meet various system configurations and design requirements You have to define which function of each pin is used b...

Page 258: ...TOUT GPA20 Output only nFRE GPA19 Output only nFWE GPA18 Output only ALE GPA17 Output only CLE GPA16 Output only nRCS5 GPA15 Output only nRCS4 GPA14 Output only nRCS3 GPA13 Output only nRCS2 GPA12 Output only nRCS1 GPA11 Output only nOE_CF GPA10 RDATA_OEN RADDR25 GPA9 Output only RADDR24 GPA8 Output only RADDR23 GPA7 Output only RADDR22 GPA6 Output only RADDR21 GPA5 Output only RADDR20 GPA4 Output...

Page 259: ...utput TOUT3 GPB2 Input output TOUT2 GPB1 Input output TOUT1 GPB0 Input output TOUT0 Port C Selectable Pin Functions GPC15 Input output RGB_VD7 SYS_VD7 GPC14 Input output RGB_VD6 SYS_VD6 GPC13 Input output RGB_VD5 SYS_VD5 GPC12 Input output RGB_VD4 SYS_VD4 GPC11 Input output RGB_VD3 SYS_VD3 GPC10 Input output RGB_VD2 SYS_VD2 GPC9 Input output RGB_VD1 SYS_VD1 GPC8 Input output RGB_VD0 SYS_VD0 GPC7 I...

Page 260: ... output RGB_VD12 SYS_VD12 GPD3 Input output RGB_VD11 SYS_VD11 GPD2 Input output RGB_VD10 SYS_VD10 GPD1 Input output RGB_VD9 SYS_VD9 GPD0 Input output RGB_VD8 SYS_VD8 Port E Selectable Pin Functions GPE15 Input output IICSDA GPE14 Input output IICSCL GPE13 Input output SPICLK0 GPE12 Input output SPIMOSI0 GPE11 Input output SPIMISO0 GPE10 Input output SD0_DAT3 GPE9 Input output SD0_DAT2 GPE8 Input o...

Page 261: ...NT1 GPF0 Input output EINT0 Port G Selectable Pin Functions GPG15 Input output EINT23 CARD_PWREN GPG14 Input output EINT22 RESET_CF GPG13 Input output EINT21 nREG_CF GPG12 Input output EINT20 nINPACK GPG11 Input output EINT19 nIREQ_CF GPG10 Input output EINT18 CAM_FIELD_A GPG9 Input output EINT17 GPG8 Input output EINT16 GPG7 Input output EINT15 GPG6 Input output EINT14 GPG5 Input output EINT13 GP...

Page 262: ...put RXD2 GPH4 Input output TXD2 GPH3 Input output RXD1 GPH2 Input output TXD1 GPH1 Input output RXD0 GPH0 Input output TXD0 Port J Selectable Pin Functions GPJ15 Input output nSD1_WP GPJ14 Input output nSD1_CD GPJ13 Input output SD1_LED I2S1_LRCK PCM1_FSYNC GPJ12 Input output CAMRESET GPJ11 Input output CAMCLKOUT GPJ10 Input output CAMHREF GPJ9 Input output CAMVSYNC GPJ8 Input output CAMPCLK GPJ7 ...

Page 263: ... Input output SDATA30 GPK13 Input output SDATA29 GPK12 Input output SDATA28 GPK11 Input output SDATA27 GPK10 Input output SDATA26 GPK9 Input output SDATA25 GPK8 Input output SDATA24 GPK7 Input output SDATA23 GPK6 Input output SDATA22 GPK5 Input output SDATA21 GPK4 Input output SDATA20 GPK3 Input output SDATA19 GPK2 Input output SDATA18 GPK1 Input output SDATA17 GPK0 Input output SDATA16 ...

Page 264: ...SPIMOSI1 GPL10 Input output SPICLK1 GPL9 Input output SD1_CLK GPL8 Input output SD1_CMD GPL7 Input output SD1_DAT7 I2S1_SDO PCM1_SDO GPL6 Input output SD1_DAT6 I2S1_SDI PCM1_SDI GPL5 Input output SD1_DAT5 I2S1_CDCLK PCM1_CDCLK GPL4 Input output SD1_DAT4 I2S1_SCLK PCM1_SCLK GPL3 Input output SD1_DAT3 GPL2 Input output SD1_DAT2 GPL1 Input output SD1_DAT1 GPL0 Input output SD1_DAT0 Port M Selectable ...

Page 265: ...ster controls the pull up down resister enable disable of each port group When the corresponding bit is 0 the pull down resister of the pin is enabled When 1 the pull down resister is disabled If the port pull down register is enabled then the pull down resisters work without pin s functional setting input output DATAn EINTn and etc MISCELLANEOUS CONTROL REGISTER This register controls mode select...

Page 266: ... Output 1 DQM2 GPA24 24 0 Output 1 RSMAVD GPA23 23 0 Output 1 RSMCLK GPA22 22 0 Output 1 nFCE GPA21 21 0 Output 1 nRSTOUT GPA20 20 0 Output 1 nFRE GPA19 19 0 Output 1 nFWE GPA18 18 0 Output 1 ALE GPA17 17 0 Output 1 CLE GPA16 16 0 Output 1 nRCS 5 GPA15 15 0 Output 1 nRCS 4 GPA14 14 0 Output 1 nRCS 3 GPA13 13 0 Output 1 nRCS 2 GPA12 12 0 Output 1 nRCS 1 GPA11 11 0 Output 1 nOE_CF GPA10 10 0 RDATA_O...

Page 267: ...EGISTERS GPACON GPADAT Continued GPADAT Bit Description Reserved 31 28 Reserved GPA 27 0 27 0 When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read NOTE GPA10 is excluded in data output mode ...

Page 268: ...0x1 GPBCON Bit Description Reserved 31 22 Reserved GPB10 21 20 00 Input 01 Output 10 nXDREQ 0 11 XDREQ 0 GPB9 19 18 00 Input 01 Output 10 nXDACK 0 11 XDACK 0 GPB8 17 16 00 Input 01 Output 10 nXDREQ 1 11 XDREQ 1 GPB7 15 14 00 Input 01 Output 10 nXDACK 1 11 XDACK 1 GPB6 13 12 00 Input 01 Output 10 nXBREQ 11 XBREQ GPB5 11 10 00 Input 01 Output 10 nXBACK 11 XBACK GPB4 9 8 00 Input 01 Output 10 TCLK 11...

Page 269: ...onfigured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPBUDP Bit Description Reserved 31 22 Reserved GPBUDP10 GPBUDP0 21 20 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available GPBSEL Bit Description Reserved 31 5 Reserved GPB10SEL 4 0 GPB10 1 I2SSDO_2 GPB9SEL ...

Page 270: ... GPC12 25 24 00 Input 01 Output 10 RGB SYS_VD 4 11 Reserved GPC11 23 22 00 Input 01 Output 10 RGB SYS_VD 3 11 Reserved GPC10 21 20 00 Input 01 Output 10 RGB SYS_VD 2 11 Reserved GPC9 19 18 00 Input 01 Output 10 RGB SYS_VD 1 11 Reserved GPC8 17 16 00 Input 01 Output 10 RGB SYS_VD 0 11 Reserved GPC7 15 14 00 Input 01 Output 10 Reserved 11 Reserved GPC6 13 12 00 Input 01 Output 10 Reserved 11 Reserve...

Page 271: ...en the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPCUDP Bit Description GPCUDP15 GPCUDP0 31 30 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available ...

Page 272: ... GPD12 25 24 00 Input 01 Output 10 RGB_VD 20 11 Reserved GPD11 23 22 00 Input 01 Output 10 RGB_VD 19 11 Reserved GPD10 21 20 00 Input 01 Output 10 RGB_VD 18 11 Reserved GPD9 19 18 00 Input 01 Output 10 RGB SYS_VD 17 11 Reserved GPD8 17 16 00 Input 01 Output 10 RGB SYS _VD 16 11 Reserved GPD7 15 14 00 Input 01 Output 10 RGB SYS _VD 15 11 Reserved GPD6 13 12 00 Input 01 Output 10 RGB SYS _VD 14 11 R...

Page 273: ...en the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPDUDP Bit Description GPDUDP15 GPDUDP0 31 30 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available ...

Page 274: ...d GPE13 27 26 00 Input 01 Output 10 SPICLK0 11 Reserved GPE12 25 24 00 Input 01 Output 10 SPIMOSI0 11 Reserved GPE11 23 22 00 Input 01 Output 10 SPIMISO0 11 Reserved GPE10 21 20 00 Input 01 Output 10 SD0_DAT3 11 Reserved GPE9 19 18 00 Input 01 Output 10 SD0_DAT2 11 Reserved GPE8 17 16 00 Input 01 Output 10 SD0_DAT1 11 Reserved GPE7 15 14 00 Input 01 Output 10 SD0_DAT0 11 Reserved GPE6 13 12 00 Inp...

Page 275: ...is configured as an output port the pin state is the same as the corresponding bit When the port is configured as a functional pin the undefined value will be read GPEUDP Bit Description GPEUDP15 GPEUDP0 31 30 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available GPESEL Bit Description Reserved 31 5 Reserved GPE4SEL 4 0 GPE4 1 PCM0_SDO GPE3SEL 3 0 GPE3 1 PCM0_S...

Page 276: ... 15 14 00 Input 01 Output 10 EINT 7 11 Reserved GPF6 13 12 00 Input 01 Output 10 EINT 6 11 Reserved GPF5 11 10 00 Input 01 Output 10 EINT 5 11 Reserved GPF4 9 8 00 Input 01 Output 10 EINT 4 11 Reserved GPF3 7 6 00 Input 01 Output 10 EINT 3 11 Reserved GPF2 5 4 00 Input 01 Output 10 EINT 2 11 Reserved GPF1 3 2 00 Input 01 Output 10 EINT 1 11 Reserved GPF0 1 0 00 Input 01 Output 10 EINT 0 11 Reserve...

Page 277: ...i n a r y S3C2451X RISC MICROPROCESSOR I O PORTS 11 21 GPFUDP Bit Description Reserved 31 16 Reserved GPFUDP7 GPFUDP0 15 14 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available ...

Page 278: ...t 10 EINT 22 11 RESET_CF GPG13 27 26 00 Input 01 Output 10 EINT 21 11 nREG_CF GPG12 25 24 00 Input 01 Output 10 EINT 20 11 nINPACK GPG11 23 22 00 Input 01 Output 10 EINT 19 11 nIREQ_CF GPG10 21 20 00 Input 01 Output 10 EINT 18 11 CAM_FIELD_A GPG9 19 18 00 Input 01 Output 10 EINT 17 11 Reserved GPG8 17 16 00 Input 01 Output 10 EINT 16 11 Reserved GPG7 15 14 00 Input 01 Output 10 EINT 15 11 Reserved...

Page 279: ...the port is configured as an input port the corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPGUDP Bit Description GPGUDP15 GPGUDP0 31 30 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available ...

Page 280: ...01 Output 10 CLKOUT0 11 Reserved GPH12 25 24 00 Input 01 Output 10 EXTUARTCLK 11 Reserved GPH11 23 22 00 Input 01 Output 10 nRTS1 11 Reserved GPH10 21 20 00 Input 01 Output 10 nCTS1 11 Reserved GPH9 19 18 00 Input 01 Output 10 nRTS0 11 Reserved GPH8 17 16 00 Input 01 Output 10 nCTS0 11 Reserved GPH7 15 14 00 Input 01 Output 10 RXD 3 11 nCTS2 GPH6 13 12 00 Input 01 Output 10 TXD 3 11 nRTS2 GPH5 11 ...

Page 281: ...configured as an input port the corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPHUDP Bit Description Reserved 31 30 Reserved GPHUDP14 GPHUDP0 29 28 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not availa...

Page 282: ... 26 00 Input 01 Output 10 SD1_LED 11 I2S1_LRCK GPJ12 25 24 00 Input 01 Output 10 CAMRESET 11 Reserved GPJ11 23 22 00 Input 01 Output 10 CAMCLKOUT 11 Reserved GPJ10 21 20 00 Input 01 Output 10 CAMHREF 11 Reserved GPJ9 19 18 00 Input 01 Output 10 CAMVSYNC 11 Reserved GPJ8 17 16 00 Input 01 Output 10 CAMPCLK 11 Reserved GPJ7 15 14 00 Input 01 Output 10 CAMDATA 7 11 Reserved GPJ6 13 12 00 Input 01 Out...

Page 283: ...ort the corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPJUDP Bit Description GPJUDP15 GPJUDP0 31 30 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available GPJSEL Bit Description Reserved 31 1 Reserve...

Page 284: ...27 26 00 Input 01 Output 10 Sdata 29 11 Reserved GPK12 25 24 00 Input 01 Output 10 Sdata 28 11 Reserved GPK11 23 22 00 Input 01 Output 10 Sdata 27 11 Reserved GPK10 21 20 00 Input 01 Output 10 Sdata 26 11 Reserved GPK9 19 18 00 Input 01 Output 10 Sdata 25 11 Reserved GPK8 17 16 00 Input 01 Output 10 Sdata 24 11 Reserved GPK7 15 14 00 Input 01 Output 10 Sdata 23 11 Reserved GPK6 13 12 00 Input 01 O...

Page 285: ...5 0 31 0 When the port is configured as an input port the corresponding bit is the pin state When the port is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPKUDP Bit Description GPKUDP15 GPKUDP0 31 30 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not avai...

Page 286: ...t 01 Output 10 SS0 11 Reserved GPL12 25 24 00 Input 01 Output 10 SPIMISO1 11 Reserved GPL11 23 22 00 Input 01 Output 10 SPIMOSI1 11 Reserved GPL10 21 20 00 Input 01 Output 10 SPICLK1 11 Reserved GPL9 19 18 00 Input 01 Output 10 SD1_CLK 11 Reserved GPL8 17 16 00 Input 01 Output 10 SD1_CMD 11 Reserved GPL7 15 14 00 Input 01 Output 10 SD1_DAT7 11 I2S1_SDO GPL6 13 12 00 Input 01 Output 10 SD1_DAT6 11 ...

Page 287: ...ort is configured as an output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read GPLUDP Bit Description Reserved 31 30 Reserved GPLUDP14 GPLUDP0 29 28 1 0 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up enable 11 not available GPLSEL Bit Description Reserved 31 4 Reserved GPL7SEL 3 0 GPL7 1 PCM1_SDO...

Page 288: ... GPM Input 10 FRnB GPM0 1 0 Others GPM Input 10 RSMBWAIT GPMDAT Bit Description Reserved 31 2 Reserved GPM 1 0 1 0 When the port is configured as an input port the corresponding bit is the pin state When the port is configured as functional pin the undefined value will be read GPMUDP Bit Description Reserved 31 6 Reserved nWAIT 5 4 CPU CPD 00 pull up down disable 01 pull down enable 10 pull up ena...

Page 289: ...e HSSPI_EN2 31 Must be set 1 1 nCD_CF 30 nCD_CF Signal Register 0 card detected 1 card not detected 1 Reserved 29 Reserved 0 Reserved 28 Should be 1 1 Reserved 27 25 Reserved 000 FLT_I2C 24 Clocked Noise Filter Enable for IIC 0 Reserved 23 15 Reserved 0 USB_DPPD 14 USB DP Pull down control 0 disable 1 enable 0 USB_DNPD 13 USB DN Pull down control 0 disable 1 enable 0 SEL_SUSPND 12 USB Port Suspend...

Page 290: ... y I O PORTS S3C2451X RISC MICROPROCESSOR 11 34 Reserved 3 0 Reserved 0 NOTE1 User must set first MISCCR 31 1 b1 when use the high speed SPI NOTE2 We recommend not using this output pad to other device s pll clock source ...

Page 291: ...vel duration is DCLK1DIV 1 n 1 DCLK1DIV 23 20 DCLK1 divide value DCLK1 frequency source clock DCLK1DIV 1 DCLK1SelCK 17 Select DCLK1 source clock 0 PCLK 1 EPLL DCLK1EN 16 DCLK1 enable 0 DCLK1 disable 1 DCLK1 enable DCLK0CMP 11 8 DCLK0 compare value clock toggle value DCLK0DIV If the DCLK0CMP is n Low level duration is n 1 High level duration is DCLK0DIV 1 n 1 DCLK0DIV 7 4 DCLK0 divide value DCLK0 f...

Page 292: ... Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN6 27 Filter enable for EINT6 0 Filter Enable 1 Filter Disable EINT6 26 24 Setting the ٛsignalling method of the EINT6 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN5 23 Filter enable for EINT5 0 Filter Enable 1 Filter Disable E...

Page 293: ...ilter enable for EINT1 0 Filter Enable 1 Filter Disable EINT1 6 4 Setting the signalling method of the EINT1 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN0 3 Filter enable for EINT0 0 Filter Enable 1 Filter Disable EINT0 2 0 Setting the signalling method of the EINT0 000 Low level 001 High level 01x Falling edge triggered 10x Rising...

Page 294: ...le 1 Filter Disable EINT12 18 16 Setting the signaling method of the EINT12 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered FLTEN11 15 Filter enable for EINT11 0 Filter Enable 1 Filter Disable EINT11 14 12 Setting the signaling method of the EINT11 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both ed...

Page 295: ...lter Disable 0 EINT21 22 20 Setting the signaling method of the EINT21 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 FLTEN20 19 Filter Enable for EINT20 0 Filter Enable 1 Filter Disable 0 EINT20 18 16 Setting the signaling method of the EINT20 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both e...

Page 296: ...lter Disable 0 EINT17 6 4 Setting the ٛsignalling method of the EINT17 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both edge triggered 000 FLTEN16 3 Filter enable for EINT16 0 Filter Enable 1 Filter Disable 0 EINT16 2 0 Setting the ٛsignalling method of the EINT16 000 Low level 001 High level 01x Falling edge triggered 10x Rising edge triggered 11x Both ed...

Page 297: ...FLTCLK18 23 Filter clock of EINT18 configured by OM 0 PCLK 1 EXTCLK OSC_CLK EINTFLT18 22 16 Filtering width of EINT18 FLTCLK17 15 Filter clock of EINT17 configured by OM 0 PCLK 1 EXTCLK OSC_CLK EINTFLT17 14 8 Filtering width of EINT17 FLTCLK16 7 Filter clock of EINT16 configured by OM 0 PCLK 1 EXTCLK OSC_CLK EINTFLT16 6 0 Filtering width of EINT16 EINTFLT3 Bit Description FLTCLK23 31 Filter clock ...

Page 298: ...ked EINT19 19 0 enable interrupt 1 masked EINT18 18 0 enable interrupt 1 masked EINT17 17 0 enable interrupt 1 masked EINT16 16 0 enable interrupt 1 masked EINT15 15 0 enable interrupt 1 masked EINT14 14 0 enable interrupt 1 masked EINT13 13 0 enable interrupt 1 masked EINT12 12 0 enable interrupt 1 masked EINT11 11 0 enable interrupt 1 masked EINT10 10 0 enable interrupt 1 masked EINT9 9 0 enable...

Page 299: ...Not occur 1 Occur interrupt 0 EINT16 16 It is cleared by writing 1 0 Not occur 1 Occur interrupt 0 EINT15 15 It is cleared by writing 1 0 Not occur 1 Occur interrupt 0 EINT14 14 It is cleared by writing 1 0 Not occur 1 Occur interrupt 0 EINT13 13 It is cleared by writing 1 0 Not occur 1 Occur interrupt 0 EINT12 12 It is cleared by writing 1 0 Not occur 1 Occur interrupt 0 EINT11 11 It is cleared b...

Page 300: ...GSTATUS0 0x560000ac R External pin status Not define GSTATUS1 0x560000b0 R Device ID 0x32450001 GSTATUS0 Bit Description Reserved 31 4 Reserved nWAIT 3 Status of nWAIT pin NCON 2 Status of NCON pin RnB 1 Status of RnB pin BATT_FLT 0 Status of BATT_FLT pin GSTATUS1 Bit Description Software Platform ID 31 0 Software Platform ID register 0x32450003 ...

Page 301: ...E 27 26 10 DSC_nROE 25 24 10 DSC_nRWE 23 22 nRBE nROE nRWE Drive strength 00 5 2mA 01 10 5mA 10 15 7mA 11 21 0mA 10 DSC_nRCS5 21 20 10 DSC_nRCS4 19 18 10 DSC_nRCS3 17 16 10 DSC_nRCS2 15 14 10 DSC_nRCS1 13 12 10 DSC_nRCS0 11 10 nRCS5 nRCS0 Address Bus Drive strength 00 5 2mA 01 10 5mA 10 15 7mA 11 21 0mA 10 DSC_RADDRH 9 8 ROM Address Bus 25 16 Drive strength 00 5 2mA 01 10 5mA 10 15 7mA 11 21 0mA 1...

Page 302: ...16 nSCAS drive strength 00 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_nSRAS 15 14 nSRAS drive strength 00 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_nSCS1 13 12 nSCS1 drive strength 00 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_nSCS0 11 10 nSCS0 drive strength 00 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_SADDR 9 8 SADDR drive strength 00 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_SDATA3 7 6 SDATA 31 2...

Page 303: ... strength 00 5 2mA 01 10 5mA 10 15 7mA 11 21 0mA 10 Reserved 17 16 Reserved 00 DSC_RSMAVD 15 14 RSMAVD drive strength 00 5 2mA 01 10 5mA 10 15 7mA 11 21 0mA 10 DSC_RSMCLK 13 12 RSMCLK drive strength 00 5 2mA 01 10 5mA 10 15 7mA 11 21 0mA 10 DSC_DQM3 11 10 DQM3 drive strength 00 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_DQM2 9 8 DQM2 drive strength 00 4 9mA 01 9 8mA 10 14 8mA 11 19 7mA 10 DSC_DQM1 ...

Page 304: ...D 23 16 drive strength 00 2 6mA 01 5 2mA 10 7 8mA 11 10 5mA 10 DSC_LCD1 7 6 LCD_VD 15 8 drive strength 00 2 6mA 01 5 2mA 10 7 8mA 11 10 5mA 10 DSC_LCD0 5 4 LCD_VD 7 0 drive strength 00 2 6mA 01 5 2mA 10 7 8mA 11 10 5mA 10 DSC_HS_MMC 3 2 HS_MMC drive strength 00 2 6mA 01 5 2mA 10 7 8mA 11 10 5mA 10 DSC_HS_SPI 1 0 HS_SPI drive strength 00 2 6mA 01 5 2mA 10 7 8mA 11 10 5mA 10 ...

Page 305: ...11 00 output 0 01 output 1 10 Hi Z 11 Not Available 01 PSC_DQS 15 14 DQS 1 0 pin status inactive 0 00 output 0 01 output 1 10 Hi Z 11 Not Available 00 PSC_nSWE 13 12 nSWE pin status inactive 1 00 output 0 01 output 1 10 Hi Z 11 Not Available 01 PSC_SDR 11 10 nSCAS nSRAS pin status inactive 1 00 output 0 01 output 1 10 Hi Z 11 Not Available 01 PSC_nSCS1 9 8 nSCS1 pin status inactive 1 00 output 0 0...

Page 306: ...utput 0 01 output 1 10 Hi Z 11 Not Available 00 PSC_nRWE 19 18 nRWE pin status inactive 1 00 output 0 01 output 1 10 Hi Z 11 Not Available 01 PSC_nROE 17 16 nROE pin status inactive 1 00 output 0 01 output 1 10 Hi Z 11 Not Available 01 PSC_RSM 15 14 RSMCLK RSMAVD pin status inactive 0 00 output 0 01 output 1 10 Hi Z 11 Not Available 00 PSC_nRBE 13 12 nRBE 1 0 pin status inactive 1 00 output 0 01 o...

Page 307: ...RISC MICROPROCESSOR I O PORTS 11 51 PSC_RADDRL 3 2 RADDR 15 1 pin status inactive 0 00 output 0 01 output 1 10 Hi Z 11 Not Available 00 PSC_RADDR0 1 0 RADDR 0 pin status inactive 0 00 output 0 01 output 1 10 Hi Z 11 Not Available 00 ...

Page 308: ...p PAD GPF 7 0 GPG 7 0 GPA GPB GPC GPD GPE GPG 15 8 GPH GPJ GPK GPL GPM SFR GPACON 27 0 GPADAT 27 0 GPFCON 15 0 GPFDAT 7 0 GPFUDP 15 0 GPGCONL 15 0 GPGDATL 7 0 GPGUDPL 15 0 GPKCON 31 0 GPKDAT 15 0 GPKUDP 31 0 EXTINT0 31 0 EXINT1 31 0 PDDMCON PDSMCON All registers except alive SFR GP CON GP DAT GP UDP ...

Page 309: ...chdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors The watchdog timer generates the reset signal It can be used as a normal 16 bit interval timer to request interrupt service Advantage in using WDT instead of PWM timer is that WDT generates the reset signal FEATURES The Watchdog Timer includes the following features Norma...

Page 310: ...ollowing equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle t_watchdog 1 PCLK Prescaler value 1 Division_factor WTDAT WTCNT Watchdog Timer operation based on the value of watchdog timer count WTCNT register Once timer is operated count value will be down counting from the initial value of WTCNT register During the watchdog timer operation it contain...

Page 311: ...on and disable the Watchdog timer output for reset signal Register Address R W Description Reset Value WTCON 0x53000000 R W Watchdog timer control register 0x8021 WTCON Bit Description Initial State Prescaler value 15 8 Prescaler value The valid range is from 0 to 255 28 1 0x80 Reserved 7 6 Reserved These two bits must be 00 in normal operation 00 Watchdog timer 5 Enable or disable bit of Watchdog...

Page 312: ...be automatically reloaded into WTCNT Register Address R W Description Reset Value WTDAT 0x53000004 R W Watchdog timer data register 0x8000 WTDAT Bit Description Initial State Count reload value 15 0 Watchdog timer count value for reload 0x8000 WATCHDOG TIMER COUNT WTCNT REGISTER The WTCNT register contains the current count values for the watchdog timer during normal operation Note that the conten...

Page 313: ...ffer register TCMPBn has an initial value which is loaded into the internal compare register to be compared with the internal down counter value This double buffering feature of TCNTBn and TCMPBn makes the timer generate a stable output when the frequency and duty ratio are changed Each timer has its own 16 bit internal down counter which is driven by the timer clock When the internal down counter...

Page 314: ...e 5 1 MUX 5 1 MUX Control Logic2 TCMPB2 TCNTB2 5 1 MUX 5 1 MUX TCMPB3 TCNTB3 Control Logic3 TOUT3 TCNTB4 Control Logic4 Figure 13 1 16 bit PWM Timer Block Diagram PWM TIMER OPERATION PRESCALER DIVIDER An 8 bit prescaler and a 4 bit divider make the following output frequencies 4 bit Divider Settings Minimum Resolution prescaler 0 Maximum Resolution prescaler 255 Min Interval TCNTBn 1 Max Interval ...

Page 315: ...rnal compare register respectively The TCNTn register can be read from the TCNTOn register If you want to generate interrupt at intervals 3cycle of TOUTn set TCNTBn TCMPBn and TCON register like Figure 13 2 That is i Set TCNTBn 3 and TCMPBn 1 ii Set auto reload 1 and manual update 1 When manual update bit is 1 TCNTBn and TCMPBn value are loaded to TCNTn and TCMPn iii Set TCNTBn 2 and TCMPBn 0 for ...

Page 316: ...be written into Timer Count Buffer register TCNTBn and the current counter value of the timer can be read from Timer Count Observation register TCNTOn If the TCNTBn is read the read value does not indicate the current state of the counter but the reload value for the next timer duration The auto reload operation copies the TCNTBn into TCNTn when the TCNTn reaches 0 The value written into the TCNTB...

Page 317: ...d by the manual update bit The following steps describe how to start a timer 1 Write the initial value into TCNTBn and TCMPBn 2 Set the manual update bit of the corresponding timer It is recommended that you configure the inverter on off bit Whether use inverter or not 3 Set start bit of the corresponding timer to start the timer and clear the manual update bit configure the inverter on off bit as...

Page 318: ...n The timer starts counting down after latency time within the timer resolution 3 When the TCNTn has the same value as that of the TCMPn the logic level of the TOUTn is changed from low to high 4 When the TCNTn reaches 0 the interrupt request is generated and TCNTBn value is loaded into a temporary register At the next timer tick the TCNTn is reloaded with the temporary register value TCNTBn 5 In ...

Page 319: ...TCMPBn 40 Write TCMPBn 30 Write TCMPBn 30 Write TCMPBn Next PWM Value 60 50 40 30 30 Figure 13 5 Example of PWM PWM function can be implemented by using the TCMPBn PWM frequency is determined by TCNTBn Figure 13 5 shows a PWM value determined by TCMPBn For a higher PWM value decrease the TCMPBn value For a lower PWM value increase the TCMPBn value If an output inverter is enabled the increment dec...

Page 320: ... 2 Timer Stop Inverter on Figure 13 6 Inverter On Off The following procedure describes how to maintain TOUT as high or low assume the inverter is off 1 Turn off the auto reload bit And then the timer is stopped after the TCNTn reaches 0 TOUTn goes to high level recommended 2 Stop the timer by clearing the timer start stop bit to 0 If TCNTn TCMPn at that moment the output level is high If TCNTn TC...

Page 321: ... time gap between a turn off of a switching device and a turn on of another switching device This time gap prohibits the two switching devices from being turned on simultaneously even for a very short time TOUT0 is the PWM output nTOUT0 is the inversion of the TOUT0 If the dead zone is enabled the output wave form of TOUT0 and nTOUT0 will be TOUT0_DZ and nTOUT0_DZ respectively nTOUT0_DZ is routed ...

Page 322: ...gnal it makes the request signal inactive The timer which generates the DMA request is determined by setting DMA mode bits in TCFG1 register If one of timers is configured as DMA request mode that timer does not generate an interrupt request The others can generate interrupt normally DMA mode configuration and DMA interrupt operation DMA Mode DMA Request Timer0 INT Timer1 INT Timer2 INT Timer3 INT...

Page 323: ...nput clock Frequency PCLK prescaler value 1 divider value prescaler value 0 255 divider value 2 4 8 16 Register Address R W Description Reset Value TCFG0 0x51000000 R W Configures the two 8 bit prescalers 0x00000000 TCFG0 Bit Description Initial State Reserved 31 24 0x00 Dead zone length 23 16 These 8 bits determine the dead zone length The 1 unit time of the dead zone length is equal to that of t...

Page 324: ...6 01xx External TCLK 0000 MUX 3 15 12 Select MUX input for PWM Timer3 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK 0000 MUX 2 11 8 Select MUX input for PWM Timer2 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK 0000 MUX 1 7 4 Select MUX input for PWM Timer1 0000 1 2 0001 1 4 0010 1 8 0011 1 16 01xx External TCLK 0000 MUX 0 3 0 Select MUX input for PWM Timer0 0000 1 2 0001 1 4 00...

Page 325: ...Timer 3 0 Inverter off 1 Inverter on for TOUT3 0 Timer 3 manual update note 17 Determine manual update for Timer 3 0 No operation 1 Update TCNTB3 TCMPB3 0 Timer 3 start stop 16 Determine start stop for Timer 3 0 Stop 1 Start for Timer 3 0 Timer 2 auto reload on off 15 Determine auto reload on off for Timer 2 0 One shot 1 Interval mode auto reload 0 Timer 2 output inverter on off 14 Determine outpu...

Page 326: ...e Reserved 7 5 Reserved Dead zone enable 4 Determine the dead zone operation 0 Disable 1 Enable 0 Timer 0 auto reload on off 3 Determine auto reload on off for Timer 0 0 One shot 1 Interval mode auto reload 0 Timer 0 output inverter on off 2 Determine the output inverter on off for Timer 0 0 Inverter off 1 Inverter on for TOUT0 0 Timer 0 manual update note 1 Determine the manual update for Timer 0...

Page 327: ...0C R W Timer 0 count buffer register 0x00000000 TCMPB0 0x51000010 R W Timer 0 compare buffer register 0x00000000 TCMPB0 Bit Description Initial State Timer 0 compare buffer register 15 0 Set compare buffer value for Timer 0 0x00000000 TCNTB0 Bit Description Initial State Timer 0 count buffer register 15 0 Set count buffer value for Timer 0 0x00000000 TIMER 0 COUNT OBSERVATION REGISTER TCNTO0 Regis...

Page 328: ...18 R W Timer 1 count buffer register 0x00000000 TCMPB1 0x5100001C R W Timer 1 compare buffer register 0x00000000 TCMPB1 Bit Description Initial State Timer 1 compare buffer register 15 0 Set compare buffer value for Timer 1 0x00000000 TCNTB1 Bit Description Initial State Timer 1 count buffer register 15 0 Set count buffer value for Timer 1 0x00000000 TIMER 1 COUNT OBSERVATION REGISTER TCNTO1 Regis...

Page 329: ...24 R W Timer 2 count buffer register 0x00000000 TCMPB2 0x51000028 R W Timer 2 compare buffer register 0x00000000 TCMPB2 Bit Description Initial State Timer 2 compare buffer register 15 0 Set compare buffer value for Timer 2 0x00000000 TCNTB2 Bit Description Initial State Timer 2 count buffer register 15 0 Set count buffer value for Timer 2 0x00000000 TIMER 2 COUNT OBSERVATION REGISTER TCNTO2 Regis...

Page 330: ...30 R W Timer 3 count buffer register 0x00000000 TCMPB3 0x51000034 R W Timer 3 compare buffer register 0x00000000 TCMPB3 Bit Description Initial State Timer 3 compare buffer register 15 0 Set compare buffer value for Timer 3 0x00000000 TCNTB3 Bit Description Initial State Timer 3 count buffer register 15 0 Set count buffer value for Timer 3 0x00000000 TIMER 3 COUNT OBSERVATION REGISTER TCNTO3 Regis...

Page 331: ...R REGISTER TCNTB4 Register Address R W Description Reset Value TCNTB4 0x5100003C R W Timer 4 count buffer register 0x00000000 TCNTB4 Bit Description Initial State Timer 4 count buffer register 15 0 Set count buffer value for Timer 4 0x00000000 TIMER 4 COUNT OBSERVATION REGISTER TCNTO4 Register Address R W Description Reset Value TCNTO4 0x51000040 R Timer 4 count observation register 0x00000000 TCN...

Page 332: ...OPROCESSOR 13 20 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NOTES ...

Page 333: ...eal Time Clock RTC unit can be operated by the backup battery when the system power is off The data include the time by second minute hour date day month and year The RTC unit works with an external 32 768 KHz crystal and can perform the alarm function 14 2 Features The Real Time Clock includes the following features BCD number second minute hour date day month and year Leap year generator Alarm f...

Page 334: ...CINT Figure 14 1 Real Time Clock Block Diagram 14 3 1 Leap Year Generator The leap year generator can determine the last date of each month out of 28 29 30 or 31 based on data from BCDDAY BCDMON and BCDYEAR This block considers leap year in deciding on the last date An 8 bit counter can only represent 2 BCD digits therefore it cannot decide whether 00 year the year with its last two digits zeros i...

Page 335: ...t if the value is 0 sec the year month date hour and minute may be changed to 2060 Year 1 Month 1 Date 0 Hour and 0 Minute because of the one second deviation that was mentioned In this case the user must re read from BCDYEAR to BCDSEC if BCDSEC is zero 14 3 3 Backup Battery Operation The RTC logic can be driven by the backup battery which supplies the power through the RTCVDD pin into the RTC blo...

Page 336: ...n 232 Tick counter clock source selection Tick clock source frequency Hz Clock range s Resolution ms TICSel 1 32768 2 15 0 217 0 03 TICsel2 0 TICSel 0 16384 2 14 0 218 0 06 TICsel2 1 TICSel 0 8192 2 13 0 219 0 12 TICsel2 2 TICSel 0 4096 2 12 0 220 0 24 TICsel2 3 TICSel 0 2048 2 11 0 221 0 49 TICsel2 6 TICSel 0 1024 2 10 0 222 0 97 TICsel2 7 TICSel 0 512 2 9 0 223 1 95 TICsel2 8 TICSel 0 256 2 8 0 ...

Page 337: ...z Counter Compare Tick interrupt RTCCON 4 Tick time interrupt enable 1bit TICK TIME COUNT REGISTER 1 0 2 048KHz cnt15 rtcif Q1N RTCCON 8 5 Q15N Q8N TICCNT0 6 0 TICCNT1 7 0 TICCNT2 16 0 Figure 14 2 RTC tick interrupt clock scheme Example For 1 ms Tick interrupt generation 1st RTCCON 0 1 b1 RTC enable 2nd RTCCON 3 1 b1 RTC clock counter reset 3rd RTCCON 3 1 b0 RTC clock counter enable 4th RTCCON 8 5...

Page 338: ...n herein are subject to change without notice 14 3 6 32 768 KHz X TAL Connection EXAMPLE The Figure 14 3 shows a circuit of the RTC unit oscillation at 32 768 Khz A RTC Block is used 15 22pF 5Mohm XTIRTC XTORTC XTIRTC XTORTC B RTC Block is not used 15 22pF VDD_RTC 32768Hz Figure 14 3 Main Oscillator Circuit Example 14 4 External Interface Name Direction Description XTI Input 32 KHz RTC Oscillator ...

Page 339: ...00050 R W RTC alarm control Register 0x0 ALMSEC 0x57000054 R W Alarm second data Register 0x0 ALMMIN 0x57000058 R W Alarm minute data Register 0x00 ALMHOUR 0x5700005C R W Alarm hour data Register 0x0 ALMDATE 0x57000060 R W Alarm date data Register 0x01 ALMMON 0x57000064 R W Alarm month data Register 0x01 ALMYEAR 0x57000068 R W Alarm year data Register 0x0 BCDSEC 0x57000070 R W BCD second Register ...

Page 340: ...cription Reset Value RTCCON 0x57000040 R W RTC control Register 0x00 RTCCON Bit Description Initial State TICsel2 8 5 Tick Time clock select2 0 clock period of 1 16384 second select 1 clock period of 1 8192 second select 2 clock period of 1 4096 second select 3 clock period of 1 2048 second select 4 clock period of 1 128 second select 5 clock period of 1 second select 6 clock period of 1 1024 seco...

Page 341: ...at TICNT2 register TICNT0 16 0 NOTES Tick time count value TICK TIME COUNT 0 x 28 T ICK TIME COUNT 1 TICK TIME COUNT2 x 215 Register Address R W Description Reset Value TICNT0 0x57000044 R W Tick time count register 0x00 TICNT Bit Description Initial State TICK INT ENABLE 7 Tick time interrupt enable 0 Disable 1 Enable b 0 TICK TIME COUNT 0 6 0 14 8 bits of 32 bit tick time count value b 0 14 6 3 ...

Page 342: ...LMWKUP ALMEN must be enable If compare value is year ALMEN and YEAREN must be enable If compare values are year mon date hour min and sec ALMEN YEAREN MONEN DATEEN HOUREN MINEN and SECEN must be enable Register Address R W Description Reset Value RTCALM 0x57000050 R W RTC alarm control Register 0x0 RTCALM Bit Description Initial State Reserved 7 0 ALMEN 6 Alarm global enable 0 Disable 1 Enable Not...

Page 343: ... data Register 0x0 ALMSEC Bit Description Initial State Reserved 7 0 6 4 BCD value for alarm second 0 5 000 SECDATA 3 0 0 9 0000 14 6 7 ALARM MIN DATA ALMMIN REGISTER Register Address R W Description Reset Value ALMMIN 0x57000058 R W Alarm minute data Register 0x00 ALMMIN Bit Description Initial State Reserved 7 0 6 4 BCD value for alarm minute 0 5 000 MINDATA 3 0 0 9 0000 14 6 8 ALARM HOUR DATA A...

Page 344: ...a Register 0x01 ALMDATE Bit Description Initial State Reserved 7 6 00 5 4 BCD value for alarm date from 0 to 28 29 30 31 0 3 00 DATEDATA 3 0 0 9 0001 14 6 10 ALARM MONth DATA ALMMON REGISTER Register Address R W Description Reset Value ALMMON 0x57000064 R W Alarm month data Register 0x01 ALMMON Bit Description Initial State Reserved 7 5 00 4 BCD value for alarm month 0 1 0 MONDATA 3 0 0 9 0001 14 ...

Page 345: ... are subject to change without notice 14 6 12 BCD SECOND BCDSEC REGISTER Register Address R W Description Reset Value BCDSEC 0x57000070 R W BCD second Register Undefined BCDSEC Bit Description Initial State 6 4 BCD value for second 0 5 SECDATA 3 0 0 9 14 6 13 BCD MINUTE BCDMIN REGISTER Register Address R W Description Reset Value BCDMIN 0x57000074 R W BCD minute Register Undefined BCDMIN Bit Descr...

Page 346: ...UR 0x57000078 R W BCD hour Register Undefined BCDHOUR Bit Description Initial State Reserved 7 6 5 4 BCD value for hour 0 2 HOURDATA 3 0 0 9 14 6 15 BCD DATE BCDDATE REGISTER Register Address R W Description Reset Value BCDDATE 0x5700007C R W BCD DATE Register Undefined BCDDAY Bit Description Initial State Reserved 7 6 5 4 BCD value for date 0 3 DATEDATA 3 0 0 9 14 6 16 BCD DAY BCDDAY REGISTER Reg...

Page 347: ...ate Reserved 7 5 4 BCD value for month 0 1 MONDATA 3 0 0 9 14 6 18 BCD YEAR BCDYEAR REGISTER Register Address R W Description Reset Value BCDYEAR 0x57000088 R W BCD year Register Undefined BCDYEAR Bit Description Initial State YEARDATA 7 4 BCD value for year 0 9 0x0 3 0 0 9 0x0 Note For setting BCD registers RTCEN RTCCON 0 bit must be ebable But at no setting BCD registers RTCEN must be disable fo...

Page 348: ...CROPROCESSOR 14 16 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NOTES ...

Page 349: ...includes programmable baud rates infrared IR transmit receive one or two stop bit insertion 5 bit 6 bit 7 bit or 8 bit data width and parity checking Each UART contains a baud rate generator transmitter receiver and a control unit as shown in Figure 15 1 The baud rate generator can be clocked by PCLK EXTUARTCLK or divided EPLL clock The transmitter and the receiver contain 64 byte FIFOs and data s...

Page 350: ...Control Unit Transmitter Receiver Peripheral BUS TXDn Clock Source PCLK FCLK n UEXTCLK RXDn Transmit FIFO Register FIFO mode Transmit Holding Register Non FIFO mode Receive FIFO Register FIFO mode Receive Holding Register Non FIFO mode only In FIFO mode all 64 Byte of Buffer register are used as FIFO register In non FIFO mode only 1 Byte of Buffer register is used as Holding register Transmit Shif...

Page 351: ...smission word is transmitted completely After the break signal transmission it continuously transmits data into the Tx FIFO Tx holding register in the case of Non FIFO mode Data Reception Like the transmission the data frame for reception is also programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits in the line control register ULCONn The receiver can...

Page 352: ...under 32 byte in AFC nRTS means that its own receive FIFO is ready to receive data UART A TxD nCTS UART B RxD nRTS Transmission Case in UART A UART A RxD nRTS UART B TxD nCTS Reception Case in UART A Figure 15 2 UART AFC interface NOTE UART 3 does not support AFC function because the S3C2451X has no nRTS 3 and nCTS 3 Example of Non Auto Flow Control Controlling nRTS and nCTS by Software Rx Operati...

Page 353: ... request and polling mode When the transmitter transfers data from its transmit FIFO register to its transmit shifter and the number of data left in transmit FIFO reaches Tx FIFO Trigger Level Tx interrupt is generated if Transmit mode in control register is selected as Interrupt request or polling mode In the Non FIFO mode transferring data from the transmit holding register to the transmit shift...

Page 354: ...cters sequentially and the frame error occurs while receiving B and the parity error occurs while receiving D The actual UART receive error will not generate any error interrupt because the character which is received with an error would have not been read The error interrupt will occur once the character is read Figure 15 3 shows the UART receiving the five characters including the two errors Tim...

Page 355: ...or to verify the internal transmit and to receive the data path of each SIO channel This mode can be selected by setting the loopback bit in the UART control register UCONn Infrared IR Mode The S3C2451X UART block supports infrared IR transmission and reception which can be selected by setting the Infrared mode bit in the UART line control register ULCONn Figure 15 4 illustrates how to implement t...

Page 356: ...opment for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 15 5 Serial I O Frame Timing Diagram Normal UART Figure 15 6 Infrared Transmit Mode Frame Timing Diagram Figure 15 7 Infrared Receive Mode Frame Timing Diagram ...

Page 357: ...ol register 0x00 ULCON2 0x50008000 R W UART channel 2 line control register 0x00 ULCON3 0x5000C000 R W UART channel 3 line control register 0x00 ULCONn Bit Description Initial State Reserved 7 0 Infrared Mode 6 Determine whether or not to use the Infrared mode 0 Normal mode operation 1 Infrared Tx Rx mode 0 Parity Mode 5 3 Specify the type of parity generation and checking during UART transmit and...

Page 358: ...e Clock Source Control Register in system controller 0 Tx Interrupt Type 9 Interrupt request type 0 Pulse Interrupt is requested as soon as the Tx buffer becomes empty in Non FIFO mode or reaches Tx FIFO Trigger Level in FIFO mode 0 Rx Interrupt Type 8 Interrupt request type 0 Pulse Interrupt is requested the instant Rx buffer receives the data in Non FIFO mode or reaches Rx FIFO Trigger Level in ...

Page 359: ...OTES 1 When you want to change EXTUARTCLK to PCLK for UART baudrate clock selection field must be set to 2 b10 2 When the UART does not reach the FIFO trigger level and does not receive data during 3 words time in Interrupt receive mode with FIFO the Rx interrupt will be generated receive time out and the users should check the FIFO status and read out the rest 3 If Tx DMA request signal were 0 Rx...

Page 360: ...O control register 0x0 UFCON3 0x5000C008 R W UART channel 3 FIFO control register 0x0 UFCONn Bit Description Initial State Tx FIFO Trigger Level2 7 6 Determine the trigger level of transmit FIFO 00 Empty 01 16 byte 10 32 byte 11 48 byte 00 Rx FIFO Trigger Level2 5 4 Determine the trigger level of receive FIFO 00 1 byte 01 8 byte 10 16 byte 11 32 byte 00 Reserved 3 0 Tx FIFO Reset 2 Auto cleared af...

Page 361: ...IFO contains 56 bytes 010 When RX FIFO contains 48 bytes 011 When RX FIFO contains 40 bytes 100 When RX FIFO contains 32 bytes 101 When RX FIFO contains 24 bytes 110 When RX FIFO contains 16 bytes 111 When RX FIFO contains 8 bytes 000 Auto Flow Control AFC 4 0 Disable 1 Enable 0 Reserved 3 1 These bits must be 0 s 00 Request to Send 0 If AFC bit is enabled this value will be ignored In this case t...

Page 362: ...ransmitter empty 2 Set to 1 automatically when the transmit buffer register has no valid data to transmit and the transmit shift register is empty 0 Not empty 1 Transmitter transmit buffer shifter register empty 1 Transmit buffer empty 1 Set to 1 automatically when transmit buffer register is empty 0 The buffer register is not empty 1 Empty In Non FIFO mode Interrupt or DMA is requested In FIFO mo...

Page 363: ...ister 0x0 UERSTAT3 0x5000C014 R UART channel 3 Rx error status register 0x0 UERSTATn Bit Description Initial State Break Detect 3 Set to 1 automatically to indicate that a break signal has been received 0 No break receive 1 Break receive Interrupt is requested 0 Frame Error 2 Set to 1 automatically whenever a frame error occurs during receive operation 0 No frame error during receive 1 Frame error...

Page 364: ...FSTAT0 0x50000018 R UART channel 0 FIFO status register 0x00 UFSTAT1 0x50004018 R UART channel 1 FIFO status register 0x00 UFSTAT2 0x50008018 R UART channel 2 FIFO status register 0x00 UFSTAT3 0x5000C018 R UART channel 3 FIFO status register 0x00 UFSTATn Bit Description Initial State Reserved 15 0 Tx FIFO Full 14 Set to 1 automatically whenever transmit FIFO is full during transmit operation 0 0 b...

Page 365: ...on Reset Value UMSTAT0 0x5000001C R UART channel 0 modem status register 0x0 UMSTAT1 0x5000401C R UART channel 1 modem status register 0x0 UMSTAT2 0x5000801C R UART channel 2 modem status register 0x0 Reserved 0x5000C01C Reserved Undef UMSTAT0 Bit Description Initial State Delta CTS 4 Indicate that the nCTS input to the S3C2451X has changed state since the last time it was read by CPU Refer to Fig...

Page 366: ...transmit buffer register UTXH3 0x5000C020 W by byte UART channel 3 transmit buffer register UTXHn Bit Description Initial State TXDATAn 7 0 Transmit data for UARTn UART RECEIVE BUFFER REGISTER HOLDING REGISTER FIFO REGISTER There are four UART receive buffer registers including URXH0 URXH1 URXH2 and URXH3 in the UART block URXHn has an 8 bit data for received data Register Address R W Description ...

Page 367: ...te divisor registers including UBRDIV0 UBRDIV1 UBRDIV2 and UBRDIV3 in the UART block The value stored in the baud rate divisor register UBRDIVn and dividing slot register UDIVSLOTn are used to determine the serial Tx Rx clock rate baud rate as follows DIV_VAL UBRDIVn num of 1 s in UDIVSLOTn 16 SRCCLK baud rate x 16 1 SRCCLK PCLK EXTUARTCLK or divided EPLL clock Where Interger part of DIV_VAL shoul...

Page 368: ...1 0xDDD5 1101_1101_1101_0101b 0 75 12 0xDDDD 1101_1101_1101_1101b 0 8125 13 0xDFDD 1101_1111_1101_1101b 0 875 14 0xDFDF 1101_1111_1101_1111b 0 9375 15 0xFFDF 1111_1111_1101_1111b Baud Rate Error Tolerance UART Frame error should be less than 1 87 3 160 tUPCLK UBRDIVn 1 x 16 x 1Frame PCLK tUPCLK Real UART Clock tEXTUARTCLK 1Frame baud rate tEXTUARTCLK Ideal UART Clock UART error tUPCLK tEXTUARTCLK ...

Page 369: ...BRDIV3 0x5000C028 R W Baud rate divisior integer place register 3 UBRDIVn Bit Description Initial State UBRDIV 15 0 Baud rate division value of integer part When UART clock source is PCLK UBRDIVn must be more than 0 UBRDIVn 0 NOTE If UBRDIV value is 0 UART baudrate is not affected by UDIVSLOT value Register Address R W Description Reset Value UDIVSLOT0 0x5000002C R W Baud rate divisior decimal pla...

Page 370: ...OCESSOR 15 22 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NOTES ...

Page 371: ...m ports Support for both LowSpeed and FullSpeed USB devices HCI SLAVE BLOCK APP_SADR 8 APP_SDATA 32 HCI_DATA 32 CONTROL CONTROL OHCI REGS USB STATE CONTROL LIST PROCESSOR BLOCK ED TD REGS Cntl HCI MASTER BLOCK CONTROL ED TD_DATA 32 ED TD STATUS 32 64x8 FIFO Cntl HC_DATA 8 DF_DATA 8 APP_MDATA 32 HCM_ADR DATA 32 CONTROL STATUS CONTROL CTRL CTRL RH_DATA 8 DF_DATA 8 HCF_DATA 8 Addr 6 FIFO_DATA 8 64x8 ...

Page 372: ... Controller Register Base Address R W Description Reset Value HcRevision 0x49000000 Control and status group HcControl 0x49000004 HcCommonStatus 0x49000008 HcInterruptStatus 0x4900000C HcInterruptEnable 0x49000010 HcInterruptDisable 0x49000014 HcHCCA 0x49000018 Memory pointer group HcPeriodCuttentED 0x4900001C HcControlHeadED 0x49000020 HcControlCurrentED 0x49000024 HcBulkHeadED 0x49000028 HcBulkC...

Page 373: ... 2 0 Controller is designed to aid the rapid implementation of the USB 2 0 peripheral device The controller supports both High and Full speed mode Using the standard UTMI interface and AHB interface the USB 2 0 Controller can support up to 9 Endpoints including Endpoint0 with programmable Interrupt Bulk mode FEATURE Compliant to USB 2 0 specification Supports FS HS dual mode operation EP 0 FIFO 64...

Page 374: ...8Mhz or 30Mhz PHY Clock 30Mhz PHY or Internal Clock 48Mhz Internal Clock 48Mhz System Controller SFR setting USB 2 0 Function USB 2 0 PHY Control Block USB 1 1 Host USB 2 0 PHY External USB HOST or Device Serial Interface 2 USB 1 1 Transceiver DP DN Figure 17 1 USB2 0 Block Diagram USB2 0 Function has a AHB Slave which provides the microcontroller with read and write access to the Control and Stat...

Page 375: ...B Function see USB control registers in System Controller Guide UTMI Interface AHB Slave Interface AHB Master Interface UPH SIE UTMI FIFO BLOCK Figure 17 2 USB2 0 Function Block Diagram SIE SERIAL INTERFACE ENGINE This block handles NRZI decoding encoding CRC generation and checking and bit stuffing It also provides the interface signals for USB Transceiver UPH UNIVERSAL PROTOCOL HANDLER This bloc...

Page 376: ...the system The control and status registers of endpoint0 belong to these non indexed registers Table 17 1 Non Indexed Registers Register Address R W Description IR 0x4980_0000 R W Index Register EIR 0x4980_0004 R W Endpoint Interrupt Register EIER 0x4980_0008 R W Endpoint Interrupt Enable Register FAR 0x4980_000C R Function Address Register EDR 0x4980_0014 R W Endpoint Direction Register TR 0x4980...

Page 377: ...egister ECR 0x4980_0030 R W Endpoints Control Register BRCR 0x4980_0034 R Byte Read Count Register BWCR 0x4980_0038 R W Byte Write Count Register MPR 0x4980_003C R W Max Packet Register DCR 0x4980_0040 R W DMA Control Register DTCR 0x4980_0044 R W DMA Transfer Counter Register DFCR 0x4980_0048 R W DMA FIFO Counter Register DTTCR1 0x4980_004C R W DMA Total Transfer Counter1 Register DTTCR2 0x4980_0...

Page 378: ...REGISTER IR The index register is used for indexing a specific endpoint In most cases setting the index register value should precede any other operation Register Address R W Description Reset Value IR 0x4980_0000 R W Index Register 0x00 IR Bit R W Description Initial State 31 16 Reserved 0000 15 4 Reserved Don t write to this field 0 INDEX 3 0 R W Endpoint Number Select 0 6 0000 Endpoint0 0001 En...

Page 379: ...the endpoint status register should be checked to identify if it s related to specific endpoint Clearing the bits can be accomplished by writing 1 to the bit position where the interrupt is detected Register Address R W Description Reset Value EIR 0x4980_0004 R C Endpoint Interrupt Register 0x00 EIR Bit R W Description Initial State 31 9 Reserved 0 EP8I 8 R C Endpoint 8 Interrupt Flag 0 EP7I 7 R C...

Page 380: ...r Address R W Description Reset Value EIER 0x4980_0008 R W Endpoint Interrupt Enable Register 0x00 EIER Bit R W Description Initial State 31 9 Reserved EP8IE 8 R W Endpoint 8 Interrupt Enable Flag 0 EP7IE 7 R W Endpoint 7 Interrupt Enable Flag 0 EP6IE 6 R W Endpoint 6 Interrupt Enable Flag 0 EP5IE 5 R W Endpoint 5 Interrupt Enable Flag 0 EP4IE 4 R W Endpoint 4 Interrupt Enable Flag 0 EP3IE 3 R W E...

Page 381: ...cations and information herein are subject to change without notice FUNCTION ADDRESS REGISTER FAR This register holds the address of USB device Register Address R W Description Reset Value FAR 0x4980_000C R Function Address Register 0x0 FAR Bit R W Description Initial State 31 7 Reserved FA 6 0 R MCU can read a unique USB function address from this register The address is transferred from USB Host...

Page 382: ...y new enumeration the direction can be altered Since the endpoint 0 is bi directional there is no direction bit assigned to it Register Address R W Description Reset Value EDR 0x4980_0014 R W Endpoint Direction Register 0x0 EDR Bit R W Description Initial State 31 9 Reserved EP8DS 8 R W Endpoint 8 Direction Select 0 EP7DS 7 R W Endpoint 7 Direction Select 0 EP6DS 6 R W Endpoint 6 Direction Select ...

Page 383: ... W Test Mode When TMD is set to 1 The core is forced into the test mode Following TPS TKS TJS TSNS bits are meaningful in test mode 0 TPS 3 R W Test Packets If this bit is set the USB repetitively transmit the test packets to Host The test packets are explained in 7 1 20 of USB 2 0 specification This bit can be set when TMD bit is set 0 TKS 2 R W Test K Select If this bit is set the transceiver po...

Page 384: ...Error If error interrupt enable bit of SCR register is set to 1 BAERR is set to 1 when byte alignment error is detected 0 TMERR 14 R C Timeout Error If error interrupt enable bit of SCR register is set to 1 TMERR is set to 1 when timeout error is detected 0 BSERR 13 R C Bit Stuff Error If error interrupt enable bit of SCR register is set to 1 BSERR is set to 1 when bit stuff error is detected 0 TC...

Page 385: ... State DM 5 R DM Data Line State DM informs the status of D Line 0 HSP 4 R Host Speed 0 Full Speed 1 High Speed 0 SDE 3 R C Speed Detection End SDE is set by the core when the HS Detect Handshake process is ended 0 HFRM 2 R C Host Forced Resume HFRM is set by the core in suspend state when host sends resume signaling 0 HFSUSP 1 R C Host Forced Suspend HFSUSP is set by the core when the SUSPEND sig...

Page 386: ...ss R W Description Reset Value SCR 0x4980_0020 R W System Control Register 0x0 SCR Bit R W Description Initial State 31 15 Reserved DTZIEN 14 R W DMA Total Counter Zero Interrupt Enable 0 Disable 1 Enable When set to 1 DMA total counter zero interrupt is generated 0 13 Reserved DIEN 12 R W DUAL Interrupt Enable 0 Disable 1 Enable When set to 1 Interrupt is activated until Interrupt source is clear...

Page 387: ...PDC 3 R W Speed detection Control Software can reset Speed detection Logic through this bit This bit is used to control speed detection process in case of System with a long initial time 0 Enable 1 Disable 0 MFRM 2 R W Resume by MCU If this bit is set the suspended core generates a resume signal This bit is set when MCU writes 1 This bit is cleared when MCU writes 0 0 HSUSPE 1 R W Suspend Enable W...

Page 388: ...24 R W EP0 Status Register 0x0 EP0SR Bit R W Description Initial State 31 7 Reserved LWO 6 R Last Word Odd LWO informs that the last word of a packet in FIFO has an invalid upper byte This bit is cleared automatically after the MCU reads it from the FIFO 0 5 Reserved SHT 4 R C Stall Handshake Transmitted SHT informs that STALL handshake due to stall condition is sent to Host This bit is an interru...

Page 389: ... and toggle controls can be handled by EP0 control register Register Address R W Description Reset Value EP0CR 0x4980_0028 R W EP0 Control Register 0x0 EP0CR Bit R W Description Initial State 31 2 Reserved ESS 1 R W Endpoint Stall Set ESS is set by MCU when it intends to send STALL handshake to Host This bit is cleared when the MCU writes 0 on it ESS is needed to be set 0 after MCU writes 1 on it ...

Page 390: ...fer Register Address R W Description Reset Value EP0BR 0x4980_0060 R W EP0 Buffer Register 0x0 EP1BR 0x4980_0064 R W EP1 Buffer Register 0x0 EP2BR 0x4980_0068 R W EP2 Buffer Register 0x0 EP3BR 0x4980_006C R W EP3 Buffer Register 0x0 EP4BR 0x4980_0070 R W EP4 Buffer Register 0x0 EP5BR 0x4980_0074 R W EP5 Buffer Register 0x0 EP6BR 0x4980_0078 R W EP6 Buffer Register 0x0 EP7BR 0x4980_007C R W EP7 Buf...

Page 391: ...UT Packet interrupt Disable in OUT DMA operation First Received OUT packet generates interrupt if this bit is disabled and DEN in DMA control register is enabled 0 Disable 1 Enable 0 OSD 10 R C OUT Start DMA Operation OSD is set when First OUT packet is received after Registers related DMA Operation are set 0 DTCZ 9 R C DMA Total Count Zero DTCZ is set when DMA Operation Total Counter reach to 0 T...

Page 392: ...y the MCU This bit is cleared when the MCU writes 1 on it 0 LWO 4 R Last Word Odd LWO informs that the lower byte of last word is only valid This bit is automatically cleared after the MCU reads packet data received Host 0 PSIF 3 2 R Packet Status In FIFO 00 No packet in FIFO 01 One packet in FIFO 10 Two packet in FIFO 11 Invalid value 0 TPS 1 R C Tx Packet Success TPS is used for Single or Dual t...

Page 393: ...ister 0x0 ECR Bit R W Description Initial State 31 13 Reserved INPKTHLD 12 R W The MCU can control Tx FIFO status through this bit If this bit is set to one USB does not send IN data to Host 0 The USB can send IN data to Host according to IN FIFO status normal operation 1 The USB sends NAK handshake to Host regardless of IN FIFO status 0 OUTPKTHLD 11 R W The MCU can control Rx FIFO Status through ...

Page 394: ...e Specifications and information herein are subject to change without notice ECR Bit R W Description Initial State ESS 1 R W Endpoint Stall Set ESS is set by the MCU when the MCU intends to send STALL handshake to Host This bit is cleared when the MCU writes 0 in it 0 IEMS 0 R W Interrupt Endpoint Mode Set IEMS determines the transfer type of an endpoint 0 Interrupt Transfer mode Disable 1 Interru...

Page 395: ...REGISTER BRCR The byte read count register keeps byte half word counts of a RX packet from USB host Register Address R W Description Reset Value BRCR 0x4980_0034 R Byte Read Count Register 0x0 BRCR Bit R W Description Initial State 31 10 Reserved RDCNT 9 0 R FIFO Read Byte Count 9 0 RDCNT is read only The BRCR inform the amount of received data from host In 16 bit Interface RDCNT informs the amoun...

Page 396: ... BWCR The byte write count register keeps the byte half word count value of a TX packet from MCU The counter value will be used to determine the end of TX packet Register Address R W Description Reset Value BWCR 0x4980_0038 R W Byte Write Count Register 0x0 BWCR Bit R W Description Initial State 31 10 Reserved WRCNT 9 0 R W Through BWCR the MCU must load the byte counts of a TX data packet to the ...

Page 397: ...sed to determine the end of TX packet Register Address R W Description Reset Value MPR 0x4980_003C R W MAX Packet Register 0x0 MPR Bit R W Description Initial State 31 11 Reserved MAXP 10 0 R W MAX Packet 10 0 The max packet size of each endpoint is determined by MAX packet register The range of max packet is from 0 to 1024 bytes 000_0000_0000 Max Packet 0 byte 000_0000_1000 Max Packet 8 bytes 000...

Page 398: ...s ended 0 FMDE 4 R W Burst Mode Enable This bit is used to run Burst Mode DMA Operation 0 Burst mode disable 1 Burst mode enable 0 DMDE 3 R W Demand Mode DMA Enable This bit is used to run Demand mode DMA operation 0 Demand mode disable 1 Demand mode enable 0 TDR 2 R W Tx DMA Operation Run This bit is used to set start DMA operation for Tx Endpoint IN endpoint 0 DMA operation stop 1 DMA operation ...

Page 399: ...notice DMA TRANSFER COUNTER REGISTER DTCR The byte write count register keeps the byte half word count value of a TX packet from MCU The counter value will be used to determine the end of TX packet Register Address R W Description Reset Value DTCR 0x4980_0044 R W DMA Transfer Counter Register 0x0 MTCR Bit R W Description Initial State 31 11 Reserved DTCR 10 0 R W To operate single mode transfer DT...

Page 400: ...ce DMA FIFO COUNTER REGISTER DFCR This register has the byte number of data per DMA operation The max packet size is loaded in this register Register Address R W Description Reset Value DFCR 0x4980_0048 R W DMA FIFO Counter Register 0x0 MFCR Bit R W Description Initial State 31 12 Reserved DFCR 11 0 R W In case of OUT Endpoint the size value of received packet will be loaded in this register autom...

Page 401: ...his register has the total byte number of data to transfer using DMA Interface When this counter register value is zero DMA operation is ended Register Address R W Description Reset Value DTTCR1 DTTCR2 0x4980_004C 0x4980_0050 R W DMA Total Transfer Counter Register 1 2 0x0 MTTCR Bit R W Description Initial State 31 16 Reserved DTTCR 15 0 R W This register should have total byte size to be transfer...

Page 402: ...is controlled by the programming DMA Control Register and DMA IF Control Register Register Address R W Description Reset Value DICR 0x4980_0084 R W DMA Interface Counter Register 0x0 DICR Bit R W Description Initial State Reserved 31 4 Reserved 0 RELOAD_ MBAR 4 R W Select Reload Condiion 0 Every end of Full DMA operation 1 Every Packet transfer 0 Reserved 3 2 Reserved 0 MAX_BURST 1 0 R W Max Burst...

Page 403: ...ssociated errata are not yet available Specifications and information herein are subject to change without notice MEMORY BASE ADDRESS REGISTER MBAR Register Address R W Description Reset Value MBAR 0x4980_0088 R W Memory Base Address Register 0x0 MBAR Bit R W Description Initial State MBAR 31 0 R W This register should have memory base address to be transferred using DMA Interface 32 h0 ...

Page 404: ...ress to be transferred using DMA Interface BURST FIFO CONTROL REGISTER FCON Register Address R W Description Reset Value FCON 0x4980_0100 R W Burst DMA transfer Control 0x0 MBAR Bit R W Description Initial State Reserved 31 9 R W Reserved 000000 DMAEN 8 R W DMA enable 0 Rreserved 7 5 R W Reserved 000 TF_CLR 4 R W TX fifo clear 0 Reserved 3 1 R W Reserved 000 RF_CLR 0 R W RX fifo clear 0 BURST FIFO...

Page 405: ...eration Flow Total Transfer Counter in USB core is Zero USB Core receives OUT data from HOST PC and transfers to Memory AHB Master IF Registers Unit Counter Total Transfer Counter Control are set in initial state or Interrupt service routine AHB Master IF Registers are to be set after MCU reads all data packets from USB OUT FIFO to operate a AHB Master operation after interrupt service mode Master...

Page 406: ...ore receives IN TOKEN from Host PC and sends IN data to HOST PC If Host receives IN data successfully Host send ACK handshake Master writes data to IN FIFO AHB Master Registers Unit Counter Total Transfer Counter Control are set in intial state or Interrupt service routine AHB Master Registers are to be set after MCU writes one packet data to USB IN FIFO to operate a AHB Master operation after int...

Page 407: ...multi master IIC bus operations values must be written to the following registers Multi master IIC bus control register IICCON Multi master IIC bus control status register IICSTAT Multi master IIC bus Tx Rx data shift register IICDS Multi master IIC bus address register IICADD When the IIC bus is free the SDA and SCL lines should be both at High level A High to Low transition of SDA can initiate a...

Page 408: ...evelopment for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice PCLK Address Register SDA 4 bit Prescaler IIC Bus Control Logic IICSTAT IICCON Comparator Shift Register Shift Register IICDS Data Bus SCL Figure 18 1 IIC Bus Block Diagram ...

Page 409: ...ne can be initiated and SCL signal generated A Start condition can transfer a one byte serial data over the SDA line and a Stop condition can terminate the data transfer A Stop condition is a Low to High transition of the SDA line while SCL is High Start and Stop conditions are always generated by the master The IIC bus gets busy when a Start condition is generated A Stop condition will make the I...

Page 410: ... following a Start condition should have the address field The address field can be transmitted by the master when the IIC bus is operating in Master mode Each byte should be followed by an acknowledgement ACK bit The MSB bit of the serial data and addresses are always sent first NOTES 1 S Start rS Repeat Start P Stop A Acknowledge 2 From Master to Slave From Slave to Master Write Mode Format with...

Page 411: ...K bit to the transmitter The ACK pulse should occur at the ninth clock of the SCL line Eight clocks are required for the one byte data transfer The master should generate the clock pulse required to transmit the ACK bit The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received The receiver should also drive the SDA line Low during the ACK clock pu...

Page 412: ... when the masters simultaneously lower the SDA line each master should evaluate whether the mastership is allocated itself or not For the purpose of evaluation is that each master should detect the address bits While each master generates the slaver address it should also detect the address bit on the SDA line because the SDA line is likely to get Low rather than to keep High Assume that one maste...

Page 413: ...perations 1 Write own slave address on IICADD register if needed 2 Set IICCON register a Enable interrupt b Define SCL period 3 Set IICSTAT to enable Serial Output Write slave address to IICDS Write 0xF0 M T Start to IICSTAT The data of the IICDS is transmitted ACK period and then interrupt is pending Write 0xD0 M T Stop to IICSTAT Write new data transmitted to IICDS Stop Clear pending bit to resu...

Page 414: ...in are subject to change without notice Write slave address to IICDS Write 0xB0 M R Start to IICSTAT The data of the IICDS slave address is transmitted ACK period and then interrupt is pending Write 0x90 M R Stop to IICSTAT Read a new data from IICDS Stop Clear pending bit to resume SDA is shifted to IICDS START Master Rx mode has been configured Clear pending bit Wait until the stop condition tak...

Page 415: ...tions and information herein are subject to change without notice IIC detects start signal and IICDS receives data IIC compares IICADD and IICDS the received slave address Write data to IICDS The IIC address match interrupt is generated Clear pending bit to resume The data of the IICDS is shifted to SDA START Slave Tx mode has been configured END Matched N Y Stop Interrupt is pending N Y Figure 18...

Page 416: ...Specifications and information herein are subject to change without notice IIC detects start signal and IICDS receives data IIC compares IICADD and IICDS the received slave address Read data from IICDS The IIC address match interrupt is generated Clear pending bit to resume SDA is shifted to IICDS START Slave Rx mode has been configured END Matched N Y Stop Interrupt is pending N Y Figure 18 9 Ope...

Page 417: ...s bit cannot be written to 1 When this bit is read as 1 the IICSCL is tied to L and the IIC is stopped To resume the operation clear this bit as 0 0 1 No interrupt pending when read 2 Clear pending condition Resume the operation when write 1 1 Interrupt is pending when read 2 N A when write 0 Transmit clock value 4 3 0 IIC Bus transmit clock prescaler IIC Bus transmit clock frequency is determined...

Page 418: ...ondition 5 IIC Bus busy signal status bit 0 read Not busy when read write STOP signal generation 1 read Busy when read write START signal generation The data in IICDS will be transferred automatically just after the start signal 0 Serial output 4 IIC bus data output enable disable bit 0 Disable Rx Tx 1 Enable Rx Tx 0 Arbitration status flag 3 IIC bus arbitration procedure status flag bit 0 Bus arb...

Page 419: ...ss latched from the IIC bus When serial output enable 0 in the IICSTAT IICADD is write enabled The IICADD value can be read any time regardless of the current serial output enable bit IICSTAT setting Slave address 7 1 Not mapped 0 XXXXXXXX MULTI MASTER IIC BUS TRANSMIT RECEIVE DATA SHIFT IICDS REGISTER Register Address R W Description Reset Value IICDS0 0x5400000C R W IIC0 Bus transmit receive dat...

Page 420: ...n Reset Value IICLC0 0x54000010 R W IIC0 Bus multi master line control register 0x00 IICLC1 0x54000110 R W IIC1 Bus multi master line control register 0x00 IICLC0 IICLC1 Bit Description Initial State Filter enable 2 IIC bus filter enable bit When SDA port is operating as input this bit should be High This filter can prevent from occurred error by a glitch during double of PCLK time 0 Filter disabl...

Page 421: ...nate data by setting the drawing context registers 2 start the rendering process by setting the relevant command registers accordingly FEATURES Primitives Line Point Drawing DDA Digital Differential Analyzer algorithm Do Not Draw Last Point support BitBLT Stretched BitBLT support Nearest sampling Memory to Screen Host to Screen Color Expansion Memory to Screen Host to Screen Per pixel Operation Ma...

Page 422: ...en a 16 bit color data is converted to 32 bit the data of each field is shifted 8 x bits to left where x is the bit width of the field The least significant x bits of the new field data are padded with the most significant x bits of the original field data For example if the R value in RGB_565 format is 5 b11010 it will be converted to 8 b11010110 with three LSBs padded with three MSBs 3 b110 from...

Page 423: ... in the FIFO and wait to be dispatched after the current rendering process completes It is user s responsibility to make sure that the data written to the FIFO do not exceed its maximum capacity User can monitor the number of data entries used in FIFO by reading FIFO_USED bits in FIFO_STAT_REG or ask graphics engine to give an interrupt signal when the number of entries in FIFO reaches a certain l...

Page 424: ...nate of the starting point COORD_2 Coordinate of the ending point ignored if a point is rendered X INCR X increment value ignored if x axis is the Major Axis or a point is rendered X INCR ex sx ey sy Y INCR Y increment value ignored if y axis is the Major Axis or a point is rendered Y INCR ey sy ex sx FG_COLOR The color of the drawn line point CMD0_REG Configure the line point drawing parameters s...

Page 425: ...same color with background color BG_COLOR are replaced by the blue screen color BS_COLOR 2D supports both host to screen mode and memory to screen mode of BLT Related Registers COORD_0 Coordinate of the leftmost topmost coordinate of the source image COORD_1 Coordinate of the rightmost bottommost coordinate of the source image COORD_2 Coordinate of the leftmost topmost coordinate of the destinatio...

Page 426: ...bit is set the image will be shrunk or stretched depending on the values of X INCR and Y INCR CMD2_REG CMD3_REG The host provides the source image data through these two command registers When the host writes the first 32 bit data into CMD2_REG the rendering process starts in the host to screen mode Then the host should provide the rest of data by writing into CMD3_REG continuously Note that the d...

Page 427: ...e background color is set to white and the foreground black Figure 19 7 Font Drawing with Transparent Mode 2D supports both host to screen mode and memory to screen mode of Color Expansion Related Registers COORD_0 Coordinate of the leftmost topmost coordinate of the destination window COORD_1 Coordinate of the rightmost bottommost coordinate of the destination window FG_COLOR Foreground Color BG_...

Page 428: ...0 270 degree clockwise or perform a X axis Y axis flip around the horizontal or vertical line on which ox oy lies The effects of all rotation options are summarized in the following table and illustrated in Figure 19 8 Related Registers ROT_OC_REG Coordinate of the rotation reference point ROTATE_REG Rotation mode configuration Rotation Effect 0 90 180 270 X flip Y flip x dcx dcy ox oy dcx 2ox dcy...

Page 429: ...EST The Stencil Test conditionally discards a pixel based on the outcome of a comparison between the color value of this pixel of the source image and the DR min DR max values If each field R G B A of the color value falls in the range of DR min DR max this pixel is passed to the next stage otherwise discarded User can disable the stencil test on a specific field by clearing the corresponding bits...

Page 430: ...ata matter so ROP Value 11001100 3 Final Data Pattern Only the Pattern data matter so ROP Value 10101010 4 Final Data Source AND Destination ROP Value 11110000 11001100 11000000 5 Final Data Source OR Pattern ROP Value 11110000 10101010 11111010 Note that the Raster Operation only applies on R G B fields of the color data the A field will not be affected Related Registers PATTERN_REG 0 31 Pattern ...

Page 431: ...tions and information herein are subject to change without notice Per pixel alpha blending ALPHA given by the source image from 0 to 255 Alpha Blending data source ALPHA 1 destination 255 ALPHA 8 Fading data source ALPHA 1 8 fading offset Related Registers ROP_REG Alpha blending configurations alpha blending disable enable per pixel alpha blending disable enable fading disable enable ALPHA_REG Alp...

Page 432: ...egister for Host to Screen Bitblt transfer continue CMD4_REG 0x0110 W Command register for Color Expansion Host to Screen Font Start CMD5_REG 0x0114 W Command register for Color Expansion Host to Screen Font Continue CMD6_REG 0x0118 W Reserved CMD7_REG 0x011C W Command register for Color Expansion Memory to Screen Parameter Setting Registers Resolution SRC_ RES_REG 0x0200 R W Source Image Resoluti...

Page 433: ...s 3 0x0000_0000 COORD3_Y_REG 0x0338 R W Y coordinate of Coordinates 3 0x0000_0000 Rotation ROT_OC_REG 0x0340 R W Rotation Origin Coordinates 0x0000_0000 ROT_OC_X_REG 0x0344 R W X coordinate of Rotation Origin Coordinates 0x0000_0000 ROT_OC_Y_REG 0x0348 R W Y coorindate of Rotation Origin Coordinates 0x0000_0000 ROTATE_REG 0x034C R W Rotation Mode register 0x0000_0001 X Y Increment Setting X_INCR_R...

Page 434: ...bject to change without notice STENCIL_CNTL_REG 0x0720 R W Stencil control register 0x0000_0000 STENCIL_DR_MIN_REG 0x0724 W Stencil decision reference MIN register 0x0000_0000 STENCIL_DR_MAX_REG 0x0728 W Stencil decision reference MAX register 0xFFFF_FFFF Image Base Address SRC_BASE_ADDR_REG 0x0730 R W Source Image Base Address register 0x0000_0000 DEST_BASE_ADDR_REG 0x0734 R W Dest Image Base Add...

Page 435: ...004 R W Interrupt Enable register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 CCF 10 Current Command Finished interrupt enable If this bit is set when the graphics engine finishes the execution of current command an interrupt occurs and the INTP_CMD_FIN flag in INTC_PEND_REG will be set ACF 9 All Commands Finished interrupt enable If this bit is set when the graphics engine finishes...

Page 436: ... Register Address R W Description Reset Value INTC_PEND_REG 0x4D40800C R W Interrupt Pending Register 0x0 Field Bit Description Initial State Reserved 31 Should be set 1 Reserved 30 11 Reserved INTP_CMD_FIN 10 Current Command Finished interrupt flag Writing 1 to this bit clears this flag INTP_ALL_FIN 9 All Commands Finished interrupt flag Writing 1 to this bit clears this flag INTP_FULL 8 Command ...

Page 437: ...ics engine is in idle state The graphics engine finishes the execution of all commands in the command FIFO Note that ALL_FIN CMD_FIN FIFO_USED 0 0 In the middle of rendering process or FIFO_USED is greater than 0 0x1 FIFO_OVERFLOW 8 1 Command FIFO is full no more commands can be handled 0 Command FIFO is not full 0x0 Reserved 7 FIFO_USED 6 1 The number of entries occupied in command FIFO 0x0 FIFO_...

Page 438: ...Do not Draw Last Point M 8 0 Major axis is Y 1 Major axis is X Reserved 7 2 L 1 0 Nothing 1 Line Drawing P 0 0 Nothing 1 Point Drawing BitBLT REGISTER CMD1_REG Register Address R W Description Reset Value CMD1_REG 0x4D408104 W BitBLT Register 0x0 Field Bit Description Initial State Reserved 31 2 S 1 0 Nothing 1 Stretch BitBLT N 0 0 Nothing 1 Normal BitBLT HOST SCREEN START BitBLT REGISTER CMD2_REG...

Page 439: ...f the source color mode is 16 bpp e g RGB565 the upper 16 bits of the data are ignored HOST TO SCREEN START COLOR EXPANSION REGISTER CMD4_REG Register Address R W Description Reset Value CMD4_REG 0x4D408110 W Host to Screen Start Color Expansion Register 0x0 Field Bit Description Initial State Data 31 0 Color Expansion Data Start HOST TO SCREEN CONTINUE COLOR EXPANSION REGISTER CMD5_REG Register A...

Page 440: ...eserved 15 11 0x0 HoriRes 10 0 Horizontal resolution of source image Range 1 2040 Note that in YUV mode HoriRes must be an even number 0x0 SOURCE IMAGE HORIZONTAL RESOLUTION REGISTER SRC_HORI_RES_REG Register Address R W Description Reset Value SRC_HORI_RES_R EG 0x4D408204 R W Source Image Horizontal Resolution Register 0x0 Field Bit Description Initial State Reserved 31 1 0x0 HoriRes 10 0 Horizon...

Page 441: ... resolution of the screen Range 1 2040 0x0 Reserved 15 11 0x0 HoriRes 10 0 Horizontal resolution of the screen Range 1 2040 0x0 SCREEN HORIZONTAL RESOLUTION REGISTER SC_HORI_RES_REG Register Address R W Description Reset Value SC_HORI_RES_RE G 0x4D408214 R W Screen Horizontal Resolution Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 HoriRes 10 0 Horizontal resolution of the sc...

Page 442: ...26 16 Top Y Clipping Window Requirement TopCW_Y BottomCW_Y 0x0 Reserved 15 11 0x0 LeftCW_X 10 0 Left X Coordinate of Clipping Window Requirement LeftCW_X RightCW_X 0x0 LEFT X CLIPPING WINDOW REGISTER CW_LT_X_REG Register Address R W Description Reset Value CW_LT_X_REG 0x4D408224 R W Left X Clipping Window Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 LeftCW_X 10 0 Left X Clip...

Page 443: ...ement BottomCW_Y VeriRes SC_VERI_RES_REG 0x0 Reserved 15 11 0x0 RightCW_X 10 0 Right X Clipping Window Requirement RightCW_X HoriRes SC_HORI_RES_REG 0x0 RIGHT X CLIPPING WINDOW REGISTER CW_RB_X_REG Register Address R W Description Reset Value CW_RB_X_REG 0x4D408234 R W Right X Clipping Window Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 RightCW_X 10 0 Right X Clipping Window...

Page 444: ...0 Field Bit Description Initial State Reserved 31 27 0x0 Y 26 16 Coordinate_0 Y Range 0 2039 0x0 Reserved 15 11 0x0 X 10 0 Coordinate_0 X Range 0 2039 0x0 COORDINATE_0 X REGISTER COORD0_X_REG Register Address R W Description Reset Value COORD0_X_REG 0x4D408304 R W Coordinate_0 X Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 COORD0_X 10 0 Coordinate_0 X Range 0 2039 0x0 COORDI...

Page 445: ...ate_1 Y Range 0 2039 0x0 Reserved 15 11 0x0 X 10 0 Coordinate_1 X Range 0 2039 0x0 COORDINATE_1 X REGISTER COORD1_X_REG Register Address R W Description Reset Value COORD1_X_REG 0x4D408314 R W Coordinate_1 X Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 COORD1_X 10 0 Coordinate_1 X Range 0 2039 0x0 COORDINATE_1 Y REGISTER COORD1_Y_REG Register Address R W Description Reset Va...

Page 446: ...COORD2_X_REG Register Address R W Description Reset Value COORD2_ X_REG 0x4D408324 R W Coordinate_2 X Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 COORD2_X 10 0 Coordinate_2 X Range 0 2039 0x0 COORDINATE_2 Y REGISTER COORD2_Y_REG Register Address R W Description Reset Value COORD2_ Y_REG 0x4D408328 R W Coordinate_2 Y Register 0x0 Field Bit Description Initial State Reserved ...

Page 447: ...x0 X 10 0 Coordinate_3 X Range 0 2039 0x0 COORDINATE_3 X REGISTER COORD3_X_REG Register Address R W Description Reset Value COORD3_ X_REG 0x4D408334 R W Coordinate_3 X Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 COORD3_X 10 0 Coordinate_3 X Range 0 2039 0x0 COORDINATE_3 Y REGISTER COORD3_Y_REG Register Address R W Description Reset Value COORD3_ Y_REG 0x4D408338 R W Coordin...

Page 448: ... 15 11 0x0 X 10 0 Y coordinate of the reference point of rotation Range 0 2039 0x0 ROTATION ORIGIN COORDINATE X REGISTER ROT_OC_X_REG Register Address R W Description Reset Value ROT_OC_X 0x4D408344 R W Rotation Origin Coordinate X Register 0x0 Field Bit Description Initial State Reserved 31 11 0x0 ROT_OC_X 10 0 X coordinate of the reference point of rotation Range 0 2039 0x0 ROTATION ORIGIN COORD...

Page 449: ...ssociated errata are not yet available Specifications and information herein are subject to change without notice Field Bit Description Initial State Reserved 31 6 0x0 FY 5 Y flip 0x0 FX 4 X flip 0x0 R3 3 270 Rotation 0x0 R2 2 180 Rotation 0x0 R1 1 90 Rotation 0x0 R0 0 0 Rotation 0x1 If the two or more of Rn are set to 1 at the same time drawing engine operates unpredictably ...

Page 450: ...etting X INCREMENT REGISTER X_INCR_REG Register Address R W Description Reset Value X_INCR_REG 0x4D408400 R W X Increment Register 0x0 Field Bit Description Initial State Reserved 31 22 0x0 X_INCR 21 0 X increment value 2 s complement 11 digit fraction 0x0 Y INCREMENT REGISTER Y_INCR_REG Register Address R W Description Reset Value Y_INCR_REG 0x4D408404 R W Y Increment Register 0x0 Field Bit Descr...

Page 451: ...elect 1 b0 Pattern 1 b1 Foreground Color 0x0 ABM 12 10 Alpha Mode 3 b000 No Alpha Blending 3 b001 Perpixel Alpha Blending with Source Bitmap 3 b010 Alpha Blending with Alpha Register 3 b100 Fading Others Reserved Note that Perpixel Alpha Blending can only be applied on bit block transfer 0x0 T 9 0 Opaque Mode 1 Transparent Mode 0x0 B 8 0 Blue screen Mode Disable 1 Blue screen Mode Enable Note that...

Page 452: ...ROUND COLOR REGISTER BG_COLOR_REG Register Address R W Description Reset Value BG_COLOR_REG 0x4D408504 R W Background Color Register 0x0 Field Bit Description Initial State BackgroundColor 31 0 Background Color Value The alpha field of the background color will be discarded 0x0 BLUESCREEN COLOR REGISTER BS_COLOR_REG Register Address R W Description Reset Value BS_COLOR_REG 0x4D408508 R W BlueScree...

Page 453: ...0 in point line drawing mode and color expansion mode 0x0 Color Setting 2 0 3 b000 RGB_565 3 b001 RGBA_5551 3 b010 ARGB_1555 3 b011 RGBA_8888 3 b100 ARGB_8888 3 b101 XRGB_8888 3 b110 RGBX_8888 The Color Setting is ignored if YUV mode is selected 0x0 DESTINATION IMAGE COLOR MODE REGISTER DEST_COLOR_MODE_REG Register Address R W Description Reset Value DEST_COLOR_MO DE_REG 0x4D408514 R W Destination...

Page 454: ...Register Address R W Description Reset Value PATOFF_REG 0x4D408700 R W Pattern Offset Register 0x0 Field Bit Description Initial State Reserved 31 19 0x0 POffsetY 18 16 Pattern Offset Y Value 0x0 Reserved 15 3 0x0 POffsetX 2 0 Pattern OffsetX Value 0x0 PATTERN OFFSET X REGISTER PATOFF_X_REG Register Address R W Description Reset Value PATOFF_X_REG 0x4D408704 R W Pattern Offset X Register 0x0 Field...

Page 455: ...tencil Test Off for R value 1 Stencil Test On for R value 0x0 StencilOnG 2 0 Stencil Test Off for G value 1 Stencil Test On for G value 0x0 StencilOnB 1 0 Stencil Test Off for B value 1 Stencil Test On for B value 0x0 StencilOnA 0 0 Stencil Test Off for A value 1 Stencil Test On for A value 0x0 COLORKEY DECISION REFERENCE MINIMUM REGISTER COLORKEY_DR_MIN_REG Register Address R W Description Reset ...

Page 456: ...xF B_DR max 7 0 BLUE DR MAX value 0xF Image Base Address SOURCE IMAGE BASE ADDRESS REGISTER SRC_BASE_ADDR_REG Register Address R W Description Reset Value SRC_BASE_ADDR _REG 0x4D408730 R W Source Image Base Address Register 0x0 Field Bit Description Initial State ADDR 31 0 Base address of the source image 0x0 DESTINATION IMAGE BASE ADDRESS REGISTER DEST_BASE_ADDR_REG Register Address R W Descripti...

Page 457: ...transmission and receiving respectively During an HS_SPI transfer data is simultaneously transmitted shifted out serially and received shifted in serially HS_SPI supports the protocols for National Semiconductor Microwire and Motorola Serial Peripheral Interface FEATURES The features of the HS_SPI are z Supports full duplex z 8 16 32 bit shift register for TX RX z 8 bit prescale logic z 3 clock so...

Page 458: ...is port is to be input port to get data from slave output port Data are transmitted to master through this port when in slave mode PSPIMOSI1 Inout In Master mode this port is to be output port to transfer data from master output port Data are received from master through this port when in slave mode Channel 1 PSS1 Inout As to be slave selection signal all data TX RX sequences are executed when PSS...

Page 459: ...amples in Rx FIFO is less than the threshold value in INT mode or DMA 4 burst mode and no additional data is received the remaining bytes are called trailing bytes To remove these bytes in RX FIFO internal timer and interrupt signal are used The value of internal timer can be set up to 1024 clocks based on APB BUS clock When timer value is to be zero interrupt signal is occurred and CPU can remove...

Page 460: ...e 29 1 shows four waveforms for HS_SPICLK Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB SPICLK MISO MSB CPOL 1 CPHA 1 Format B Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB SPICLK MISO MSB CPOL 1 CPHA 0 Format A Cycle MOSI 1 2 3 4 5 6 7 8 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB SPICLK MISO LSB CPOL 0 CPHA 1 Format B Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4...

Page 461: ...t Tx or Rx Channel on 7 Set nSSout low to start Tx or Rx operation A Set nSSout Bit to low then start TX data writing B If auto chip selection bit is set should not control nCS SPECIAL FUNCTION REGISTER Register Address R W Description Reset Value CH_CFG Ch0 0x52000000 R W HS_SPI configuration register 0x0000_0040 CH_CFG Ch1 0x59000000 R W HS_SPI configuration register 0x0000_0040 CH_CFG Bit Descr...

Page 462: ...tion to generate HS_SPI clock out 00 PCLK 01 USBCLK 10 Epll clock 11 reserved For using USBCLK source The USB_SIG_MASK at system controller should be set to on Epll clock is from System Controller and has 4 sources MOUTEPLL DOUTMPLL PLL_SRCLK CLK27M 2 b0 ENCLK 8 R W Clock on off 0 disable 1 enable 1 b0 Prescaler Value 7 0 R W HS_SPI clock out division rate HS_SPI clock out Clock source 2 x Prescal...

Page 463: ...b0 DMA transfer 0 R W DMA transfer type single or 4 bust 0 single 1 4 burst DMA transfer size should be set as the same size in DMA as it in HS_SPI 1 b0 Channel Transfer size must be smaller than Bus Transfer size or the same as Register Address R W Description Reset Value Slave_slection_reg Ch0 0x5200000C R W Slave selection signal 0x1 Slave_slection_reg Ch1 0x5900000C R W Slave selection signal ...

Page 464: ...ble 1 b0 IntEnTxUnderrun 2 R W Interrupt Enable for TxUnderrun In slave mode this bit should be clear first after turning on slave TX path 0 Disable 1 Enable 1 b0 IntEnRxFifoRdy 1 R W Interrupt Enable for RxFifoRdy INT mode 0 Disable 1 Enable 1 b0 IntEnTxFifoRdy 0 R W Interrupt Enable for TxFifoRdy INT mode 0 Disable 1 Enable 1 b0 Register Address R W Description Reset Value HS_SPI_STATUS Ch0 0x52...

Page 465: ... always occur at slave mode 1 b0 RxFifoRdy 1 R 0 data in FIFO less than trigger level 1 data in FIFO more than trigger level 1 b0 TxFifoRdy 0 R 0 data in FIFO more than trigger level 1 data in FIFO less than trigger level 1 b0 Register Address R W Description Reset Value HS_SPI_TX_DATA Ch0 0x52000018 W HS_SPI TX DATA register 0x0 HS_SPI_TX_DATA Ch1 0x59000018 W HS_SPI TX DATA register 0x0 HS_SPI_T...

Page 466: ...tions and information herein are subject to change without notice the HS_SPI channel Register Address R W Description Reset Value Packet_Count_reg Ch0 0x52000020 R W Count how many data master gets 0x0 Packet_Count_reg Ch1 0x59000020 R W Count how many data master gets 0x0 Packet_Count_reg Bit Description Initial State Packet_Count_En 16 R W Enable bit for packet count 0 Disable 1 Enable 1 b0 Coun...

Page 467: ...n clear 1 clear 1 b0 TX_overrun_clr 3 R W TX overrun pending clear bit 0 non clear 1 clear 1 b0 RX_underrun_clr 2 R W RX underrun pending clear bit 0 non clear 1 clear 1 b0 RX_overrun_clr 1 R W RX overrun pending clear bit 0 non clear 1 clear 1 b0 Trailing_clr 0 R W Trailing pending clear bit 0 non clear 1 clear 1 b0 Register Address R W Description Reset Value SWAP_CFG Ch0 0x52000028 R W SWAP con...

Page 468: ...hange without notice TX_SWAP_en 0 R W Swap enable 0 normal 1 swap 1 b0 Data size must be larger than swap size Register Address R W Description Reset Value FB_Clk_sel Ch0 0x5200002C R W Feedback clock selecting register 0x3 FB_Clk_sel Ch1 0x5900002C R W Feedback clock selecting register 0x3 FB_Clk_sel Bit Description Initial State FB_Clk_sel 1 0 R W 00 0ns additional delay 01 3ns additional delay ...

Page 469: ... This host is compatible for SD Association s SDA Host Standard Specification You can interface your system with SD card and MMC card This performance of this host is very powerful you would get 50MHz clock rate and access 8 bit data pin simultaneously We provide 2 Channel HSMMC support CH0 only 4 bit data interface support FEATURES SD Standard Host Spec ver 2 0 compatible SD Memory Card Spec ver ...

Page 470: ...iated errata are not yet available Specifications and information herein are subject to change without notice BLOCK DIAGRAM Figure 21 1HSMMC block diagram SFR SDCLK Domain HCLK Domain System Bus AHB CM D ARG Control Status AHB slave I F DM A controller AHB master FIFO DATA packet Status Control CMDRS Ppacket Status Control RSP Lin e Control Pad I F INTREQ BaseCLK Clock Control DPSRA M Control ...

Page 471: ...xecuted as follows 1 To enable interrupt for card detection write 1 to the following bits Card Insertion Status Enable ENSTACARDNS in the Normal Interrupt Status Enable register Card Insertion Signal Enable ENSIGCARDNS in the Normal Interrupt Signal Enable register Card Removal Status Enable ENSTACARDREM in the Normal Interrupt Status Enable register Card Removal Signal Enable ENSIGCARDREM in the ...

Page 472: ... The clock shall be supplied to the card before either of the following actions is taken a Issuing a SD command b Detect an interrupt from a SD card in 4 bit mode 1 Calculate a divisor to determine SD Clock frequency by reading Base Clock Frequency for SD Clock in the Capabilities register If Base Clock Frequency for SD Clock is 00 0000b the Host System shall provide this information to the Host D...

Page 473: ...lock Stop Sequence The flow chart for stopping the SD Clock is shown in Figure 21 4 The Host Driver shall not stop the SD Clock when a SD transaction is occurring on the SD Bus namely when either Command Inhibit DAT or Command Inhibit CMD in the Present State register is set to 1 1 Set SD Clock Enable ENSDCLK in the Clock Control register to 0 Then the Host Controller stops supplying the SD Clock ...

Page 474: ...ies register get the support voltage of the Host Controller 2 Set SD Bus Voltage Select in the Power Control register with maximum voltage that the Host Controller supports 3 Set SD Bus Power PWRON in the Power Control register to 1 4 Get the OCR value of all function internal of SD card 5 Judge whether SD Bus voltage needs to be changed or not In case where SD Bus voltage needs to be changed go t...

Page 475: ... Set Card Interrupt Status Enable STACARDINT in the Normal Interrupt Status Enable register to 0 for masking incorrect interrupts that may occur while changing the bus width 2 In case of SD memory only card go to step 4 In case of other card go to step 3 3 Set IENM of the CCCR in a SDIO or SD combo card to 0 by CMD52 4 Change the bit mode for a SD card Changing SD memory card bus width by ACMD6 Se...

Page 476: ... the Host Driver by another method 2 Set Data Timeout Counter Value TIMEOUTCON in the Timeout Control register in accordance with the value from step 1 above SD TRANSACTION GENERATION This section describes the sequences how to generate and control various kinds of SD transactions SD transactions are classified into three cases 1 Transactions that do not use the DAT line 2 Transactions that use th...

Page 477: ...change without notice SD COMMAND ISSUE SEQUENCE Figure 21 9 Timeout Setting Sequence 1 Check Command Inhibit CMD in the Present State register Repeat this step until Command Inhibit CMD is 0 That is when Command Inhibit CMD is 1 the Host Driver shall not issue a SD Command 2 If the Host Driver issues a SD Command with busy signal go to step 3 If without busy signal go to step 5 3 If the Host Drive...

Page 478: ...ete STACMDCMPLT in the Normal Interrupt Status register to clear this bit 3 Read the Response register and get necessary information in accordance with the issued command 4 Judge whether the command uses the Transfer Complete Interrupt or not If it uses Transfer Complete go to step 5 If not go to step 7 5 Wait for the Transfer Complete Interrupt If the Transfer Complete Interrupt has occurred go t...

Page 479: ... information herein are subject to change without notice START Wait for Command Complete Int Command Complete Int occur Clr Command Complete Status Get Response Data Command with Transfer Complete Int Wait for Transfer Complete Int Clr Transfer Complete Status Transfer Complete Int occur Check Response Data no No error Return Status No Error Return Status Response Contents Error Error END 1 2 3 4 ...

Page 480: ...on the sequences for SD transfers are basically classified into following three kinds according to how the number of blocks is specified 1 Single Block Transfer The number of blocks is specified to the Host Controller before the transfer The number of blocks specified is always one 2 Multiple Block Transfer The number of blocks is specified to the Host Controller before the transfer The number of ...

Page 481: ... Complete Status Command Complete Int occur Get Response Data Write or Read 6 7 8 Wait for Buffer Write Ready Int Buffer Write Ready Int occur Clr Buffer Write Ready Status Set Block Data More Blocks write read 9 10 W 11 W 12 W 13 W yes no Wait for Buffer Read Ready Int Buffer Read Ready Int occur Clr Buffer Read Ready Status Get Block Data 11 R 12 R 10 R More Blocks yes 13 R no Single Multi Infin...

Page 482: ...and get necessary information in accordance with the issued command 9 In the case where this sequence is for write to a card go to step 10 W In case of read from a card go to step 10 R 10 W And then wait for Buffer Write Ready Interrupt 11 W Write 1 to the Buffer Write Ready STABUFWTRDY in the Normal Interrupt Status register for clearing this bit 12 W Write block data in according to the number o...

Page 483: ...s Reg 10 11 12 13 Clr Transfer Complete status Clr DMA Interrupt status 14 END Figure 21 12 Transaction Control with Data Transfer Using DAT Line Sequence Using DMA 1 Set the system address for DMA in the System Address register 2 Set the value corresponding to the executed data byte length of one block in the Block Size register 3 Set the value corresponding to the executed data block count in th...

Page 484: ...the next data position to the System Address register and go to Step 10 14 Write 1 to the Transfer Complete and DMA Interrupt in the Normal Interrupt Status register to clear this bit Note Step 2 and Step 3 can be executed simultaneously Step 5 and Step 6 can also be executed simultaneously ABORT TRANSACTION An abort transaction is performed by issuing CMD12 for a SD memory card and by issuing CMD...

Page 485: ... or R W Read write register Register bits are read write and may be either set or cleared by software to the desired state RW1C Read only status Write 1 to clear status Register bits indicate status when read a set bit indicating a status event may be cleared by writing a 1 Writing a 0 to RW1C bits has no effect RWAC Read Write automatic clear register The Host Driver requests a Host Controller op...

Page 486: ...ss of the next contiguous data position It can be accessed only if no transaction is executing i e after a transaction has stopped Read operations during transfers may return an invalid value The Host Driver shall initialize this register before starting a DMA transaction After DMA has stopped the next system address of the next contiguous data position can be read from this register The DMA trans...

Page 487: ...t Driver to update the System Address register In case of this register is set to 0 buffer size 4K bytes lower 12 bit of byte address points data in the contiguous buffer and the upper 20 bit points the location of the buffer in the system memory The DMA transfer stops when the Host Controller detects carry out of the address from bit 11 to 12 These bits shall be supported when the DMA Support in ...

Page 488: ... in the Transfer Mode register is set to 1 and is valid only for multiple block transfers The Host Driver shall set this register to a value between 1 and the maximum block count The Host Controller decrements the block count after each block transfer and stops when the count reaches zero Setting the block count to 0 results in no data blocks being transferred This register should be accessed only...

Page 489: ...in are subject to change without notice ARGUMENT REGISTER This register contains the SD Command Argument Register Address R W Description Reset Value ARGUMENT0 0X4AC00008 R W Command Argument Register Channel 0 0x0 ARGUMENT1 0X4A800008 R W Command Argument Register Channel 1 0x0 Name Bit Description Initial Value ARGUM ENT 31 0 Command Argument The SD Command Argument is specified as bit39 8 of Co...

Page 490: ...ing Register Channel 1 0x0 Name Bit Description Initial Value 15 10 Reserved 0 CCSCO N 9 8 Command Completion Signal Control 00 No CCS Operation Normal operation Not CE ATA mode 01 Read or Write data transfer CCS enable Only CE ATA mode 10 Without data transfer CCS enable Only CE ATA mode 11 Abort Completion Signal ACS generation Only CE ATA mode 0 7 6 Reserved 0 MUL1SI N0 5 Multi Single Block Sel...

Page 491: ...Enable 0 Disable 0 ENDMA 0 DMA Enable This bit enables DMA functionality DMA can be enabled only if it is supported as indicated in the DMA Support in the Capabilities register If DMA is not supported this bit is meaningless and shall always read 0 If this bit is set to 1 a DMA operation shall begin when the Host Driver writes to the upper byte of Command register 00Fh 1 Enable 0 Disable 0 Table b...

Page 492: ...There are three types of special commands Suspend Resume and Abort These bits shall be set to 00b for all other commands Suspend Command If the Suspend command succeeds the Host Controller shall assume the SD Bus has been released and that it is possible to issue the next command which uses the DAT line The Host Controller shall de assert Read Wait for read transactions and stop checking busy for ...

Page 493: ... ENCMD CRC 3 Command CRC Check Enable If this bit is set to 1 the Host Controller shall check the CRC field in the response If an error is detected it is reported as a Command CRC Error If this bit is set to 0 the CRC field is not checked The number of bits checked by the CRC field value changes according to the length of the response 1 Enable 0 Disable 2 Reserved RSPTYP 1 0 Response Type Select 0...

Page 494: ...n the SD Bus REP refers to a bit range within the Response register 128 bit Response bit order RSPREG3 RSPREG2 RSPREG1 RSPREG0 Kind of Response Meaning of Response Response Field Response Register R1 R1b normal response Card Status R 39 8 REP 31 0 R1b Auto CMD12 response Card Status for Auto CMD12 R 39 8 REP 127 96 R2 CID CSD register CID or CSD reg incl R 127 8 REP 119 0 R3 OCR register OCR regis...

Page 495: ...length is 136 the Host Controller shall check R 119 1 Since the Host Controller may have a multiple block data DAT line transfer executing concurrently with a CMD_wo_DAT command the Host Controller stores the Auto CMD12 response in the upper bits REP 127 96 of the Response register The CMD_wo_DAT response is stored in REP 31 0 This allows the Host Controller to avoid overwriting the Auto CMD12 res...

Page 496: ...are subject to change without notice BUFFER DATA PORT REGISTER 32 bit data port register to access internal buffer Register Address R W Description Reset Value BDATA0 0X4AC00020 R W Buffer Data Register Channel 0 BDATA1 0X4A800020 R W Buffer Data Register Channel 1 Name Bit Description Initial Value BUFDAT 31 0 Buffer Data The Host Controller buffer can be accessed through this 32 bit Data Port re...

Page 497: ...ted for memory and combo cards This bit reflects the SDWP pin 1 Write enabled SDWP 1 0 Write protected SDWP 0 Note SDWP port is mapped to SD0_nWP pin In S3C2451 case SD _nWP port is fixed to High 1 PRNT CD 18 Card Detect Pin Level RO This bit reflects the inverse value of the SDCD pin Debouncing is not performed on this bit This bit may be valid when Card State Stable is set to 1 but it is not gua...

Page 498: ...Rx mode when this bit is HIGH more than or equal to 4 word can be read by CPU side 0 DIFF1 W 12 FIFO Pointer Difference 1 Word ROC When the difference of the address pointer between AHB side and SD side is more than or equal to 1 word this status bit is set to HIGH When others clears automatically Write Tx mode when this bit is HIGH more than or equal to 1 word can be written by CPU side Read Rx m...

Page 499: ... Host Controller This bit is set in either of the following cases 1 After the end bit of the write command 2 When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer This bit is cleared in either of the following cases 1 After getting the CRC status of the last data block as specified by the transfer count Single and Multiple 2 After getting the CRC status...

Page 500: ... drive Not Busy 2 When the SD card releases write busy prior to waiting for write transfer as a result of a Stop At Block Gap Request 1 DAT Line Active 0 DAT Line Inactive CMDI NHDA T 1 Data Inhibit DAT ROC This status bit is generated if either the DAT Line Active or the Read Transfer Active is set to 1 If this bit is 0 it indicates the Host Controller can issue the next SD Command Commands with ...

Page 501: ...characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 21 13 Card Detect State The above Figure shows the state definitions of hardware that handles Debouncing Reset Power ON Debouncing Once debouncing clock becomes valid Card Inserted No Card SDCD 1 SDCD 0 Stable Stable ...

Page 502: ...ization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 21 14Timing of Command Inhibit DAT and Command Inhibit CMD with data transfer Figure 21 15 Timing of Command Inhibit DAT for the case of response with busy Figure 21 16 Timing of Command Inhibit CMD for the case of no response command ...

Page 503: ...ransfer Mode register 00 SDMA is selected 01 Reserved 10 32 bit Address ADMA2 is selected 11 64 bit Address ADMA2 is selected Not supported 0 ENHI GHSP D 2 High Speed Enable This bit is optional Before setting this bit the Host Driver shall check the High Speed Support in the Capabilities register If this bit is set to 0 default the Host Controller outputs CMD line and DAT lines at the falling edg...

Page 504: ...Bit Description Initial Value 7 4 Reserved SELP WRLV L 3 1 SD Bus Voltage Select By setting these bits the Host Driver selects the voltage level for the SD card Before setting this register the Host Driver shall check the Voltage Support bits in the Capabilities register If an unsupported voltage is selected the Host System shall not supply SD Bus voltage 111b 3 3V Typ 110b 3 0V Typ 101b 1 8V Typ ...

Page 505: ...ontroller has to stop the SD Clock to hold read data which restricts commands generation When the Host Driver detects an SD card insertion it shall set this bit according to the CCCR of the SDIO card If the card does not support read wait this bit shall never be set to 1 otherwise DAT line conflict may occur If this bit is set to 0 Suspend Resume cannot be supported RW 1 Enable Read Wait Control 0...

Page 506: ...e Present State register Regarding detailed control of bits D01 and D00 RW 1 Stop 0 Transfer There are three cases to restart the transfer after stop at the block gap Which case is appropriate depends on whether the Host Controller issues a Suspend command or the SD card accepts the Suspend command 1 If the Host Driver does not issue a Suspend command the Continue Request shall be used to restart ...

Page 507: ...CON0 0X4AC0002B R W Wakeup Control Register Channel 0 0x0 WAKCON1 0X4A80002B R W Wakeup Control Register Channel 1 0x0 Name Bit Description Initial Value 7 3 Reserved 0 ENWK UPRE M 2 Wakeup Event Enable On SD Card Removal This bit enables wakeup event via Card Removal assertion in the Normal Interrupt Status register FN_WUS Wake Up Support in CIS does not affect this bit RW 1 Enable 0 Disable 0 EN...

Page 508: ...y 2 00h base clock 10MHz 63MHz Setting 00h specifies the highest frequency of the SD Clock When setting multiple bits the most significant bit is used as the divisor But multiple bits should not be set The two default divider values can be calculated by the frequency that is defined by the Base Clock Frequency For SD Clock in the Capabilities register 1 25MHz divider value 2 400KHz divider value A...

Page 509: ...t shall be cleared RW 1 Enable 0 Disable 0 STBLINT CLK 1 Internal Clock Stable This bit is set to 1 when SD Clock is stable after writing to Internal Clock Enable in this register to 1 The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1 Note This is useful when using PLL for a clock oscillator that requires setup time ROC 1 Ready 0 Not Ready 0 ENINTCL K 0 Internal Clock...

Page 510: ...neration Timeout clock frequency will be generated by dividing the base clock SDCLK value by this value When setting this register prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable in the Error Interrupt Status Enable register 1111b Reserved 1110b SDCLK x 227 1101b SDCLK x 226 0001b SDCLK x 214 0000b SDCLK x 213 0 SOFTWARE RESET REGISTER A reset pulse is generated...

Page 511: ...eset RWAC The following registers and bits are cleared by this bit Present State register Command Inhibit CMD Normal Interrupt Status register Command Complete 1 Reset 0 Work 0 RSTDAT 0 Software Reset For All This reset affects the entire Host Controller except for the card detection circuit Register bits of type ROC RW RW1C RWAC are cleared to 0 During its initialization the Host Driver shall set...

Page 512: ...nterrupt If any of the bits in the Error Interrupt Status register are set then this bit is set Therefore the Host Driver can efficiently test for an error by checking this bit first This bit is read only ROC 0 No Error 1 Error 0 STAFIA3 14 FIFO SD Address Pointer Interrupt 3 Status RW1C 0 Occurred 1 Not Occurred 0 STAFIA2 13 FIFO SD Address Pointer Interrupt 2 Status RW1C 0 Occurred 1 Not Occurre...

Page 513: ...nserted in the Present State register changes from 0 to 1 When the Host Driver writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed Because the card detect state may possibly be changed when the Host Driver clear this bit and interrupt event may not be generated RW1C 1 Card inserted 0 Card state stable or Debouncing 0 STABUFRD ...

Page 514: ...s when data transfers are stopped at the block gap by setting Stop At Block Gap Request in the Block Gap Control register and data transfers completed After valid data is written to the SD card and the busy signal released RW1C The table below shows that Transfer Complete has higher priority than Data Timeout Error If both bits are set to 1 the data transfer can be considered complete Relation bet...

Page 515: ...r The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register In addition the Host Controller generates this Interrupt when it detects invalid descriptor data Valid 0 at the ST_FDS state ADMA Error State in the ADMA Error Status indicates that an error occurs in ST_FDS state The Host Driver may find that Valid bit is not set at the error descriptor 1 Error 0 No Error 0 ...

Page 516: ... 2 The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued If the Host Controller drives the CMD line to 1 level but detects 0 level on the CMD line at the next SDCLK edge then the Host Controller shall abort the command Stop driving CMD line and set this bit to 1 The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict 1 CRC Err...

Page 517: ... Enabled 0 Masked 0 ENSTAFIA2 13 FIFO SD Address Pointer Interrupt 2 Status Enable 1 Enabled 0 Masked 0 ENSTAFIA1 12 FIFO SD Address Pointer Interrupt 1 Status Enable 1 Enabled 0 Masked 0 ENSTAFIA0 11 FIFO SD Address Pointer Interrupt 0 Status Enable 1 Enabled 0 Masked 0 ENSTARWAI T 10 Read Wait interrupt status enable 1 Enabled 0 Masked 0 ENSTACCS 9 CCS Interrupt Status Enable 1 Enabled 0 Masked ...

Page 518: ...tion herein are subject to change without notice ENSTABUFR DRDY 5 Buffer Read Ready Status Enable 1 Enabled 0 Masked 0 ENSTABUF WTRDY 4 Buffer Write Ready Status Enable 1 Enabled 0 Masked 0 ENSTADMA 3 DMA Interrupt Status Enable 1 Enabled 0 Masked 0 ENSTABLKG AP 2 Block Gap Event Status Enable 1 Enabled 0 Masked 0 ENSTASTAN SCMPLT 1 Transfer Complete Status Enable 1 Enabled 0 Masked 0 ENSTACMD CMP...

Page 519: ...it Description Initial Value 15 10 Reserved 0 ADMAER R 9 ADMA Error Status Enable 1 Enabled 0 Masked 0 ENSTAAC MDERR 8 Auto CMD12 Error Status Enable 1 Enabled 0 Masked 0 ENSTACU RERR 7 Current Limit Error Status Enable This function is not implemented in this version 1 Enabled 0 Masked 0 ENSTADE NDERR 6 Data End Bit Error Status Enable 1 Enabled 0 Masked 0 ENSTADA TCRCER R 5 Data CRC Error Status...

Page 520: ...annel 1 0x0 Name Bit Description Initial Value 15 Fixed to 0 The Host Driver shall control error interrupts using the Error Interrupt Signal Enable register 0 ENSIGFIA3 14 FIFO SD Address Pointer Interrupt 3 Signal Enable 1 Enabled 0 Masked 0 ENSIGFIA2 13 FIFO SD Address Pointer Interrupt 2 Signal Enable 1 Enabled 0 Masked 0 ENSIGFIA1 12 FIFO SD Address Pointer Interrupt 1 Signal Enable 1 Enabled ...

Page 521: ...vailable Specifications and information herein are subject to change without notice ENSIGBUFW TRDY 4 Buffer Write Ready Signal Enable 1 Enabled 0 Masked 0 ENSIGDMA 3 DMA Interrupt Signal Enable 1 Enabled 0 Masked 0 ENSIGBLKG AP 2 Block Gap Event Signal Enable 1 Enabled 0 Masked 0 ENSIGSTAN SCMPLT 1 Transfer Complete Signal Enable 1 Enabled 0 Masked 0 ENSIGCMD CMPLT 0 Command Complete Signal Enable...

Page 522: ...ror Interrupt Signal Enable Register Channel 1 0x0 Name Bit Description Initial Value 15 10 Reserved 0 ENSIGADM AERR 9 ADMA Error Signal Enable 1 Enabled 0 Masked 0 ENSIGACM DERR 8 Auto CMD12 Error Signal Enable 1 Enabled 0 Masked 0 ENSIGCUR ERR 7 Current Limit Error Signal Enable This function is not implemented in this version 1 Enabled 0 Masked 0 ENSIGDEN DERR 6 Data End Bit Error Signal Enable...

Page 523: ...o error 0 6 5 Reserved 0 STACMDIDX ERR 4 Auto CMD12 Index Error Occurs if the Command Index error occurs in response to a command 1 Error 0 No Error 0 STACMDEBI TAER 3 Auto CMD12 End Bit Error Occurs when detecting that the end bit of command response is 0 1 End Bit Error Generated 0 No Error 0 STACMDCR CAER 2 Auto CMD12 CRC Error Occurs when detecting a CRC error in the command response 1 CRC Err...

Page 524: ...Auto CMD12 cannot be issued due to an error in the previous command Set D00 to 0 if Auto CMD12 is issued 2 At the end bit of an Auto CMD12 response Check received responses by checking the error bits D01 D02 D03 and D04 Set to 1 if error is detected Set to 0 if error is not detected 3 Before reading the Auto CMD12 Error Status bit D07 Set D07 to 1 if there is a command cannot be issued Set D07 to ...

Page 525: ... 0V Supported 0 3 0V Not Supported 0 CAPAV33 24 Voltage Support 3 3V HWInit 1 3 3V Supported 0 3 3V Not Supported 1 CAPASUS RES 23 Suspend Resume Support HWInit This bit indicates whether the Host Controller supports Suspend Resume functionality If this bit is 0 the Suspend and Resume mechanism are not supported and the Host Driver shall not issue either Suspend or Resume commands 1 Supported 0 No...

Page 526: ...to the SDCLK Frequency Select in the Clock Control register and it shall not exceed upper limit of the SD Clock frequency The supported clock range is 10MHz to 63MHz If these bits are all 0 the Host System has to get information via another method Not 0 1MHz to 63MHz 000000b Get information via another method 0 CAPATOU TUNIT 7 Timeout Clock Unit HWInit This bit shows the unit of base clock frequen...

Page 527: ...Host System via another method all Maximum Current Capabilities register shall be 0 Register Address R W Description Reset Value MAXCURR0 0X4AC00048 HWInit Maximum Current Capabilities Register Channel 0 0x0 MAXCURR1 0X4A800048 HWInit Maximum Current Capabilities Register Channel 1 0x0 Name Bit Description Initial Value 31 24 Reserved MAXCURR1 8 23 16 Maximum Current for 1 8V HWInit 0 MAXCURR3 0 1...

Page 528: ...e 1 Mask Enable 0 CDINVRXD3 29 Card Detect signal inversion for RX_DAT 3 0 Disable 1 Enable 0 SELCARDOUT 28 Card Removed Condition Selection 0 Card Removed condition is Not Card Insert State When the transition from Card Inserted state to Debouncing state 1 Card Removed state is Card Out State When the transition from Debouncing state to No Card state 0 FLTCLKSEL 27 24 Filter Clock iFLTCLK Selecti...

Page 529: ... RWAITMODE 7 Read Wait Release Control 0 Read Wait state is released by the Host Controller Auto 1 Read Wait state is released by the Host Device Manual 0 DISBUFRD 6 Buffer Read Disable 0 Normal mode user can read buffer FIFO data using 0x20 register 1 User cannot read buffer FIFO data using 0x20 register In this case the buffer memory only can be read through memory area Debug purpose 0 SELBASECL...

Page 530: ...on data and associated errata are not yet available Specifications and information herein are subject to change without notice Note Ensure to always set SDCLK Hold Enable EnSCHold if the card does not support Read Wait to guarantee for Receive data not overwritten to the internal FIFO memory Note CMD_wo_DAT issue is prohibited during READ transfer when SDCLK Hold Enable is set ...

Page 531: ...dress unit Initial value 0x7F generates at 512 byte 128 word position 0x7F FCSEL2 23 Feedback Clock Select 2 Reference Note 1 0x0 FIA2 22 16 FIFO Interrupt Address register 2 FIFO 512Byte Buffer memory word address unit Initial value 0x5F generates at 384 byte 96 word position 0x5F FCSEL1 15 Feedback Clock Select 1 Reference Note 2 0x0 FIA1 14 8 FIFO Interrupt Address register 1 FIFO 512Byte Buffe...

Page 532: ... DEBUG register Channel 0 Not fixed DEBUG_1 0X4A800088 R W DEBUG register Channel 1 Not fixed Name Bit Description Initial Value DBGREG 31 0 Debug Register Read Only Register for Debug Purpose RO Not fixed CONTROL REGISTER 4 Register Address R W Description Reset Value CONTROL4_0 0x4AC0008C R W Control register 4 Channel 0 0x0 CONTROL4_1 0x4A80008C R W Control register 4 Channel 1 0x0 Name Bit Des...

Page 533: ...e Force Event Register is not a physically implemented register Rather it is an address at which the Auto CMD12 Error Status Register can be written Writing 1 set each bit of the Auto CMD12 Error Status Register Writing 0 no effect D15 D12 Name Bit Description Initial Value 15 8 0x0 7 Force Event for Command Not Issued By Auto CMD12 Error 1 Interrupt is generated 0 No Interrupt 0 6 5 0 4 Force Eve...

Page 534: ...t of the Error Interrupt Status Enable Register is set Writing 1 set each bit of the Error Interrupt Status Register Writing 0 no effect Note By setting this register the Error Interrupt can be set in the Error Interrupt Status register In order to generate interrupt signal both the Error Interrupt Status Enable and Error Interrupt Signal Enable shall be set Name Bit Description Initial Value 15 1...

Page 535: ...t information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 0 Force Event for Command Timeout Error 1 Interrupt is generated 0 No Interrupt 0 ...

Page 536: ...rates the ADMA Error Interrupt when it detects invalid descriptor data Valid 0 at the ST_FDS state In this case ADMA Error State indicates that an error occurs at ST_FDS state The Host Driver may find that the Valid bit is not set in the error descriptor Register Address R W Description Reset Value ADMAERR0 0X4AC00054 R W ADMA Error Status Register Channel 0 0x00 ADMAERR1 0X4A800054 R W ADMA Error...

Page 537: ...e without notice 1 Error 1 0 ADMA Error State This field indicates the state of ADMA when error is occurred during ADMA data transfer This field never indicates 10 because ADMA never stops in this state D01 D00 ADMA Error State when error is occurred Contents of SYS_SDR register 00 ST_STOP Stop DMA Points next of the error descriptor 01 ST_FDS Fetch Descriptor Points the error descriptor 10 Never ...

Page 538: ...ess of executing command of the Descriptor table 32 bit Address Descriptor uses lower 32 bit of this register At the start of ADMA the Host Driver shall set start address of the Descriptor table The ADMA increments this register address which points to next line when every fetching a Descriptor line When the ADMA Error Interrupt is generated this register shall hold valid Descriptor address depend...

Page 539: ... Controller Version Register Channel 0 0x0401 HCVER1 0X4A8000FE HWInit Host Controller Version Register Channel 1 0x0401 Name Bit Description Initial Value VENVER 15 8 Vendor Version Number This status is reserved for the vendor version number The Host Driver should not use this status 0x04 SDMMC4 0 Host Controller 0x04 SPECVER 7 0 Specification Version Number This status indicates the Host Contro...

Page 540: ...ICROPROCESSOR 21 72 Preliminary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice NOTES ...

Page 541: ...r is i80 System interface The LCD controller supports up to two overlay image windows which support various color format 16 level alpha blending color key x y position control soft scrolling variable window size and etc The LCD controller can support the various requirements on the screen related to the number of horizontal and vertical pixels data line width for the data interface interface timin...

Page 542: ...4 bit Alpha blending Plane Pixel only supports 24 bit 8 8 8 mode Source format Window 0 Supports 1 2 4 or 8 bpp palletized color Supports 16 18 or 24 bpp non palletized color Window 1 Supports 1 2 4 or 8 bpp palletized color Supports 16 18 or 24 bpp non palletized color Configurable Burst Length Programable 4 8 16 Burst DMA Palette Look up table 256 x 25 ARGB bits palette 2ea for Window 0 Window1 ...

Page 543: ...d in different LCD drivers The VTIME block generates RGB_VSYNC RGB_HSYNC RGB_VCLK RGB_VDEN SYS_CS1 SYS_CS0 and so on DATA FLOW FIFO is present in the VDMA When FIFO is empty or partially empty VDMA requests data fetching from the frame memory based on the burst memory transfer mode Consecutive memory fetching of 4 8 16 words per one burst request without allowing the bus mastership to another bus ...

Page 544: ...ng Color key OUTPUT RGB Figure 22 2 Block diagram of the Data Flow INTERFACE LCD controller supports 2 types of display device One type is the conventional RGB interface that uses RGB data Vertical horizontal sync data valid signal and data sync clock The Second type is i80 System interface that uses address data chip select read write control and register status indicating signal In this type of ...

Page 545: ...COLOR DATA RGB Data format The LCD controller requests the specified memory format of frame buffer The next table shows some examples of each display mode 28BPP display A4 888 BSWP 0 HWSWP 0 BLD_PIX 1 ALPHA_SEL 1 D 31 28 D 27 24 D 23 0 000H Dummy Bit Alpha value P1 004H Dummy Bit Alpha value P2 008H Dummy Bit Alpha value P3 P1 P2 P3 P4 P5 LCD Panel NOTE D 23 16 Red data D 15 8 Green data D 7 0 Blu...

Page 546: ...out notice 25BPP display A888 BSWP 0 HWSWP 0 D 31 25 D 24 D 23 0 000H Dummy Bit AEN P1 004H Dummy Bit AEN P2 008H Dummy Bit AEN P3 P1 P2 P3 P4 P5 LCD Panel NOTE 1 AEN Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN 0 ALPHA0_R G B values are applied AEN 1 ALPHA1_R G B values are applied Each pixel of LCD panel displays blended color with lower layer window Refer to the eq...

Page 547: ...out notice 24BPP display A887 BSWP 0 HWSWP 0 D 31 24 D 23 D 22 0 000H Dummy Bit AEN P1 004H Dummy Bit AEN P2 008H Dummy Bit AEN P3 P1 P2 P3 P4 P5 LCD Panel NOTE 1 AEN Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN 0 ALPHA0_R G B values are applied AEN 1 ALPHA1_R G B values are applied Each pixel of LCD panel displays blended color with lower layer window Refer to the eq...

Page 548: ...ent for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 24BPP display 888 BSWP 0 HWSWP 0 D 31 24 D 23 0 000H Dummy Bit P1 004H Dummy Bit P2 008H Dummy Bit P3 P1 P2 P3 P4 P5 LCD Panel NOTE D 23 16 Red data D 15 8 Green data D 7 0 Blue data ...

Page 549: ...out notice 19BPP display A666 BSWP 0 HWSWP 0 D 31 19 D 18 D 17 0 000H Dummy Bit AEN P1 004H Dummy Bit AEN P2 008H Dummy Bit AEN P3 P1 P2 P3 P4 P5 LCD Panel NOTE 1 AEN Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN 0 ALPHA0_R G B values are applied AEN 1 ALPHA1_R G B values are applied Each pixel of LCD panel displays blended color with lower layer window Refer to the eq...

Page 550: ...h full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 18BPP display 666 BSWP 0 HWSWP 0 D 31 18 D 17 0 000H Dummy Bit P1 004H Dummy Bit P2 008H Dummy Bit P3 P1 P2 P3 P4 P5 LCD Panel P1 P2 P3 P4 P5 LCD Panel NOTE D 17 12 Red data D 11 6 Green data D 5 0 Blue data ...

Page 551: ...D 30 16 D 15 D 14 0 000H AEN1 P1 AEN2 P2 004H AEN3 P3 AEN4 P4 008H AEN5 P5 AEN6 P6 BSWP 0 HWSWP 1 31 D 30 16 D 15 D 14 0 000H AEN2 P2 AEN1 P1 004H AEN4 P4 AEN3 P3 008H AEN6 P6 AEN5 P5 P1 P2 P3 P4 P5 LCD Panel NOTE 1 AEN Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN 0 ALPHA0_R G B values are applied AEN 1 ALPHA1_R G B values are applied Each pixel of LCD panel displays ...

Page 552: ...nd associated errata are not yet available Specifications and information herein are subject to change without notice 16BPP display 1 555 BSWP 0 HWSWP 0 D 31 16 D 15 0 000H P1 P2 004H P3 P4 008H P5 P6 BSWP 0 HWSWP 1 D 31 16 D 15 0 000H P2 P1 004H P4 P3 008H P6 P5 NOTE D 14 10 D 15 Red data D 9 5 D 15 Green data D 4 0 D 15 Blue data Figure 22 3 16BPP 1 5 5 5 BSWP HWSWP 0 Display Types ...

Page 553: ...on data and associated errata are not yet available Specifications and information herein are subject to change without notice 16BPP display 565 BSWP 0 HWSWP 0 D 31 16 D 15 0 000H P1 P2 004H P3 P4 008H P5 P6 BSWP 0 HWSWP 1 D 31 16 D 15 0 000H P2 P1 004H P4 P3 008H P6 P5 NOTE D 15 11 Red data D 10 5 Green data D 4 0 Blue data Figure 22 4 16BPP 5 6 5 BSWP HWSWP 0 Display Types ...

Page 554: ...P5 AEN6 P6 AEN7 P7 AEN8 P8 008H AEN9 P9 AEN10 P10 AEN11 P11 AEN12 P12 BSWP 1 HWSWP 0 D 31 D 30 24 D 23 D 22 16 D 15 D 14 8 D 7 D 6 0 000H AEN4 P4 AEN3 P3 AEN2 P2 AEN1 P1 004H AEN8 P8 AEN7 P7 AEN6 P6 AEN5 P5 008H AEN12 P12 AEN11 P11 AEN10 P10 AEN9 P9 P1 P2 P3 P4 P5 LCD Panel P6 P7 P8 P10 P11 P12 P9 NOTE 1 AEN Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN 0 ALPHA0_R G B ...

Page 555: ...P1 P2 P3 P4 004H P5 P6 P7 P8 008H P9 P10 P11 P12 BSWP 1 HWSWP 0 D 31 24 D 23 16 D 15 8 D 7 0 000H P4 P3 P2 P1 004H P8 P7 P6 P5 008H P12 P11 P10 P9 P1 P2 P3 P4 P5 LCD Panel P6 P7 P8 P10 P11 P12 P9 NOTE The values of frame buffer are index of palette memory The MSB value of Palette memory is AEN bit AEN Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN 0 ALPHA0_R G B values ...

Page 556: ...004H P9 P10 P11 P12 P13 P14 P15 P16 008H P17 P18 P19 P20 P21 P22 P23 P24 BSWP 1 HWSWP 0 D 31 28 D 27 24 D 23 20 D 19 16 D 15 12 D 11 8 D 7 4 D 3 0 000H P7 P8 P5 P6 P3 P4 P1 P2 004H P15 P16 P13 P14 P11 P12 P9 P10 008H P23 P24 P21 P22 P19 P20 P17 P18 NOTE The values of frame buffer are index of palette memory The MSB value of Palette memory is AEN bit AEN Select Alpha value in Window 1 Alpha Value R...

Page 557: ...08H P41 P42 P43 P44 P45 P46 P47 P48 1BPP display Palette BSWP 0 HWSWP 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 002H P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 006H P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000H P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 004H P49 P50 P51 P52 P53 P54 P55 P56 P57 P58...

Page 558: ...5 4 3 2 1 0 BLUE 7 6 5 4 3 2 1 0 VD Pin Descriptions at 18BPP RGB parallel VD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RED 5 4 3 2 1 0 GREEN 5 4 3 2 1 0 BLUE NC NC 5 4 3 2 1 0 NC VD Pin Descriptions at 16BPP RGB parallel 5 6 5 VD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RED 4 3 2 1 0 GREEN 5 4 3 2 1 0 BLUE NC NC 4 3 2 1 0 NC VD Pin Descriptions at 24BPP RG...

Page 559: ...vailable Specifications and information herein are subject to change without notice VD Pin Descriptions at 18BPP i80 System Interface VD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RED 5 4 3 2 1 0 GREEN 5 4 3 2 1 0 BLUE NC 5 4 3 2 1 0 VD Pin Descriptions at 16BPP i80 System Interface VD 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RED 4 3 2 1 0 GREEN 5 4 3 2 1 0 ...

Page 560: ... 25 bit DPSRAM Palette supports 8 8 8 6 6 6 5 6 5 R G B and etc format For example of A 5 5 5 format write palette like Table 22 3 and then connect VD pin to LCD panel R 5 VD 23 19 G 5 VD 15 11 and B 5 VD 7 3 Select Alpha value in Window 1 Alpha Value Register At the last Set Window Palette Control W0PAL case window0 register to 0 b101 Table 22 1 25BPP A 8 8 8 Palette Data Format INDEX Bit Pos 24 ...

Page 561: ...10 9 8 7 6 5 4 3 2 1 0 00H AEN R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 01H AEN R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 FFH AEN R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Number of VD 23 22 21 20 19 18 15 14 13 12 15 14 7 6 5 4 3 2 Table 22 3 16BPP A 5 5 5 Palette Data Format INDEX Bit Pos 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00H AE...

Page 562: ... can use win0 as an OS window full TV screen window or etc This feature enhances the system performance by reducing the data rate of total system Total 2 windows Window 0 base RGB with palette Window 1 overlay RGB with palette Overlay Priority Win 1 Win 0 Blending equation WinOut R Win0 R x 1 AR Win1 R x AR WinOut G Win0 G x 1 AG Win1 G x AG WinOut B Win0 B x 1 AB Win1 B x AB Where AR Win1 s Red b...

Page 563: ...ON1 6 ALPHA_SEL 1 WINCON1 1 ALPHA1_R G B AEN 0 ALPHA0_R G B KEYBLEND 0 W1KEYCON0 26 AEN 1 ALPHA1_R G B Non Key area ALPHA0_R G B ALPHA_SEL 0 WINCON1 1 KEYBLEND 1 W1KEYCON0 26 Key area ALPHA1_R G B BLD_PIX 1 WINCON1 6 ALPHA_SEL 1 WINCON1 1 DATA 27 24 in frame buffer for 28bpp mode COLOR KEY FUNCTION The LCD controller can support color key function for the various effect of image mapping Color imag...

Page 564: ...e without notice Window0 Background Window1 Foreground DIRCON Selected Window Mask bit of COLVAL to compare with Window color Match with COLVAL Unselected window Unmatched with CONVAL Selected window COMPKEY Frame Buffer R G B COLVAL Compare Figure 22 6 Color Key Block Diagram Window0 Green Window1 Red Window0 Green Key area Non Key area COLVAL 0Xff0000 Key area Match with COLVAL area Non Key area...

Page 565: ...ization data and associated errata are not yet available Specifications and information herein are subject to change without notice No Blend and Color Key Enable Blended Alpha 0x0 OSD Image 180x100 Back Ground 320x240 Blended Alpha 0xf and No Color key Blended Alpha 0x9 and No Color key Blended Alpha 0x9 and Color Key Enable Figure 22 8 Color Key Function Configurations ...

Page 566: ...e determined by the size of the LCD panel according to the following equations HOZVAL Horizontal display size 1 LINEVAL Vertical display size 1 The rate of RGB_VCLK signal can be controlled by the CLKVAL field in the VIDCON0 register The table below defines the relationship of RGB_VCLK and CLKVAL The minimum value of CLKVAL is 1 RGB_VCLK Hz HCLK CLKVAL 1 Table 22 5 Relation between VCLK and CLKVAL...

Page 567: ...8 of virtual screen This is the data of line 8 of virtual screen This is the data of line 9 of virtual screen This is the data of line 9 of virtual screen This is the data of line 10 of virtual screen This is the data of line 10 of virtual screen This is the data of line 11 of virtual screen This is the data of line 11 of virtual screen Before Scrolling View Port The same size of LCD panel LINEVAL...

Page 568: ...without notice RGB INTERFACE I O Signals Name Type Description RGB_HSYNC Output Horizontal Sync Signal RGB_VSYNC Output Vertical Sync Signal RGB_VCLK Output LCD Video Clock RGB_VDEN Output Data Enable RGB_VD 23 0 Output RGB data output RGB I F Timing VSPW 1 VBPD 1 LINEVAL 1 VFPD 1 1 FRAME INT_FrSyn internal RGB_VSYNC RGB_HSYNC RGB_VDEN 1 LINE HSPW 1 HBPD 1 HOZVAL 1 HFPD 1 RGB_HSYNC RGB_VCLK RGB_VD...

Page 569: ... yet available Specifications and information herein are subject to change without notice LCD CPU INTERFACE I O i80 SYSTEM I F Signals Name Type Description SYS_VD 17 0 InOut Video Data SYS_CS0 Output Chip select for Main LCD SYS_CS1 Output Chip select for Sub LCD SYS_WR Output Write enable SYS_OE Output Output enable SYS_RS Output Register State select CPU i80 System I F Timing Figure 22 11 Write...

Page 570: ...to change without notice LCD SIGNAL MUXING Table 22 6 LCD Signal Muxing Table RGB and i 80 I F PAD VIDOUT Signals 10 11 SYS_WR 01 Reserved RGB_VCLK SYS_WR 00 RGB_VCLK 10 11 SYS_CS0 01 Reserved RGB_HSYNC SYS_CS0 00 RGB_HSYNC 10 11 SYS_CS1 01 Reserved RGB_VSYNC SYS_CS1 00 RGB_VSYNC 10 11 SYS_RS 01 Reserved RGB_VDEN SYS_RS 00 RGB_VDEN 10 11 SYS_OE 01 Reserved RGB_LEND SYS_OE 00 RGB_LEND 10 11 SYS_VD ...

Page 571: ...MAP Window color control 11 WPALCON Palette control register 12 WxPDATAxx Window Palette Data of the each Index Register Descriptions Register Address R W Description Reset Value VIDCON0 0x4C800000 R W Video control 0 register 0x0000_0000 VIDCON1 0x4C800004 R W Video control 1 register 0x0000_0000 VIDTCON0 0x4C800008 R W Video time control 0 register 0x0000_0000 VIDTCON1 0x4C80000C R W Video time ...

Page 572: ...or key control register 0x0000_0000 W1KEYCON1 0x4C8000B4 R W Color key value transparent value register 0x0000_0000 W2KEYCON0 0x4C8000B8 R W Color key control register 0x0000_0000 W2KEYCON1 0x4C8000BC R W Color key value transparent value register 0x0000_0000 W3KEYCON0 0x4C8000C0 R W Color key control register 0x0000_0000 W3KEYCON1 0x4C8000C4 R W Color key value transparent value register 0x0000_0...

Page 573: ...01 Reserved 10 i80 System I F for Main LDI 11 i80 System I F for Sub LDI 0 L1_DATA16 21 19 Select the mode of output data format of i80 System I F Sub LDI Only when VIDOUT 2 b11 000 16 bit mode 16 bpp 001 16 2 bit mode 18 bpp 010 9 9 bit mode 18 bpp 011 16 8 bit mode 24 bpp 100 18 bit mode 18bpp 000 L0_DATA16 18 16 Select the mode of output data format of i80 System I F Main LDI Only when VIDOUT 2...

Page 574: ...L 1 CLKVAL 1 0 VCLKEN 5 VCLK Enable Control 0 Disable 1 Enable 0 CLKDIR 4 Select the clock source as direct or divide using CLKVAL_F register 0 Direct clock frequency of VCLK frequency of Clock source 1 Divided using CLKVAL_F 0 CLKSEL_F 3 2 Select the Video Clock source 00 HCLK 01 LCD video Clock from SYSCON EPLL 10 reserved 11 reserved 0 ENVID 1 0 Video output and the LCD logics enable disable co...

Page 575: ... of the VCLK active edge 0 The video data is fetched at VCLK falling edge 1 The video data is fetched at VCLK rising edge 0 IHSYNC 6 This bit indicates the HSYNC pulse polarity 0 normal active high 1 inverted active low 0 IVSYNC 5 This bit indicates the VSYNC pulse polarity 0 normal active high 1 inverted active low 0 IVDEN 4 This bit indicates the VDEN signal polarity 0 normal active high 1 inver...

Page 576: ...to 0 in serial mode the period becomes 3 VLCK 0000000 HFPD 15 8 Horizontal front porch is the number of VCLK periods between the end of active data and the edge of next HSYNC Period HFPD 1 Note When the PNRMODE VIDCON0 14 13 is set to serial format the period of HFPD becomes 3 times of VCLK If HFPD is set to 0 in serial mode the period becomes 3 VLCK 0x00 HSPW 7 0 Horizontal sync pulse width deter...

Page 577: ...N 22 Double Buffer Auto change control bit 0 Fixed by BUFSEL 1 Auto changed by SWTRIG in CPUTRIGCON2 register Note RGB I F does not support auto change mode Only i80 Sytem I F supports auto change mode 0 BITSWP 18 Bit swap control bit 0 Swap Disable 1 Swap Enable 0 BYTSWP 17 Byte swaps control bit 0 Swap Disable 1 Swap Enable 0 HAWSWP 16 Half Word swap control bit 0 Swap Disable 1 Swap Enable 0 Re...

Page 578: ...le 1 Swap Enable 0 15 11 Reserved 0 BURSTLEN 10 9 DMA s Burst Length selection 00 16 word burst 01 8 word burst 10 4 word burst 11 Reserved 0 Reserved 8 7 Reserved 0 BLD_PIX 6 Select blending category 0 Per plane blending 1 Per pixel blending 0 BPPMODE_F 5 2 Select the BPP Bits Per Pixel mode Window image 0000 1bpp palletized 0001 2bpp palletized 0010 4bpp palletized 0011 8bpp palletized 0100 8bpp...

Page 579: ...rol 0 Off window1 1 On window1 0 Window 0 Position Control A Register Register Address R W Description Reset Value VIDOSD0A 0x4C800028 R W Video Window 0 s position control register 0x0000_0000 VIDOSD0A Bit Description initial state OSD_LeftTopX_F 21 11 Horizontal screen coordinate for left top pixel of OSD image 0 OSD_LeftTopY_F 10 0 Vertical screen coordinate for left top pixel of OSD image 0 Wi...

Page 580: ... Value VIDOSD1B 0x4C800038 R W Video Window 1 s position control register 0x0000_0000 VIDOSD1B Bit Description Initial state OSD_RightBotX_F 21 11 Horizontal screen coordinate for right bottom pixel of OSD image 0 OSD_RightBotY_F 10 0 Vertical screen coordinate for right bottom pixel of OSD image 0 NOTE Registers must have word boundary X position So 24bpp mode should have X position by 1 pixel ex...

Page 581: ... 1 s buffer start address register 0x0000_0000 VIDWxxADD0 Bit Description Initial State VBANK_F 31 24 These bits indicate A 31 24 of the bank location for the video buffer in the system memory 0x0 VBASEU_F 23 0 These bits indicate A 23 0 of the start address of the Video frame buffer 0x0 FRAME Buffer Address 1 Register Register Address R W Description Reset Value VIDW00ADD1B0 0x4C80007C R W Window...

Page 582: ...W00ADD2B1 0x4C800098 R W Window 0 s buffer size register buffer 1 0x0000_0000 VIDW01ADD2 0x4C80009C R W Window 1 s buffer size register 0x0000_0000 VIDWxxADD2 Bit Description Initial State OFFSIZE_F 25 13 Virtual screen offset size the number of byte This value defines the difference between the address of the last byte displayed on the previous Video line and the address of the first byte to be d...

Page 583: ...T_LCD3 at start of 00 BACK Porch 01 VSYNC 10 ACTIVE 11 FRONT Porch 0 FRAMESEL1 14 13 Video Frame Interrupt 1 SUBINT_LCD3 at start of 00 None 01 BACK Porch 10 VSYNC 11 FRONT Porch 0 INTFRMEN 12 Video Frame interrupts SUBINT_LCD3 Enable control bit 0 Video Frame Interrupt Disable 1 Video Frame Interrupt Enable 0 FIFOSEL 11 5 FIFO Interrupt control bit each bit has the meaning of 11 7 Reserved 6 Wind...

Page 584: ...ea or Non Key area 0 Alpha value selected by AEN bit in frame buffer 1 Alpha value selected by below area Non Key area ALPHA0_R G B Key area ALPHA1_R G B Note This bit is meaningful when BLD_PIX is 1 and ALPHA_SEL is 0 0 KEYEN_F 25 Color Key Chroma key Enable control 0 Color key disable 1 Color key enable 0 DIRCON 24 Color key Chroma key direction control 0 If the pixel value match fore ground ima...

Page 585: ...alue register 0x0000_0000 W1KEYCON1 Bit Description Initial state COLVAL 23 0 Color key value for the transparent pixel effect 0 Note COLVAL and COMPKEY use 24 bit color data at all bpp mode Unused higher bits should be 1b BPP24 mode 24 bit color value is valid A COLVAL Red COLVAL 23 16 Green COLVAL 15 8 Blue COLVAL 7 0 B COMPKEY Red COMPKEY 23 16 Green COMPKEY 15 8 Blue COMPKEY 7 0 BPP16 5 6 5 mo...

Page 586: ...P Bit Description Initial state MAPCOLEN_F 24 Window s color mapping control bit If this bit is enabled then Video DMA will stop and MAPCOLOR will be appear on back ground image instead of original image 0 disable 1 enable 0 MAPCOLOR 23 0 Color Value 0 WIN1 Color MAP Register Address R W Description Reset Value WIN1MAP 0x4C8000D4 R W Window color control 0x0000_0000 WIN1MAP Bit Description Initial...

Page 587: ...lette memory access right control bit Users should set this bit before access write or read palette memory in this case LCD controller cannot access palette After update users should clear this bit for operation of palletized LCD 0 Normal Mode LCD controller access 1 Enable ARM access 0 W1PAL 5 3 This bit determines the size of the palette data format of Window 1 000 25 bit A 8 8 8 001 24 bit 8 8 ...

Page 588: ...D 0x0000_0000 SYSIFCONx Bit Description Initial State Reserved 23 20 Reserved 0 LCD_CS_SETUP 19 16 Numbers of clock cycles for the active period of the address signal enable to the chip select enable 0 LCD_WR _SETUP 15 12 Numbers of clock cycles for the active period of the CS signal enable to the write signal enable 0 LCD_WR_ACT 11 8 Numbers of clock cycles for the active period of the chip selec...

Page 589: ... Register Address R W Description Reset Value DITHMODE 0x4C800138 R W Dithering mode register 0x0000_0000 DITHMODE Bit Description Initial state Reserved 30 7 Not used for normal access Write not zero values to these register make to come out abnormal result 0 RDithPos 6 5 Red Dither bit control 00 5 bit 01 6 bit 10 8 bit 0 GDithPos 4 3 Green Dither bit control 00 5 bit 01 6 bit 10 8 bit 0 BDithPo...

Page 590: ...rol 0x0000_0000 SIFCCON0 Bit Description Initial State Reserved 11 10 Reserved 0 SYS_CS0_CON 9 LCD i80 System Interface SYS_CS0 main Signal control 0 Disable High 1 Enable Low 0 SYS_CS1_CON 8 LCD i80 System Interface SYS_CS1 sub Signal control 0 Disable High 1 Enable Low 0 SYS_OE_CON 7 LCD i80 System Interface SYS_OE Signal control 0 Disable High 1 Enable Low 0 SYS_WR_CON 6 LCD i80 System Interfac...

Page 591: ...trol 1 Register Address R W Description Reset Value SIFCCON1 0x4C800140 R W i80 System Interface Command Data Write register 0x0000_0000 SIFCCON1 Bit Description Initial State Reserved 23 18 Reserved 0 SYS_WDATA 17 0 LCD i80 System Interface Write Data 0 i80 System Interface Command Control 2 Register Address R Description Reset Value SIFCCON2 0x4C800144 R i80 System Interface Command Data Read re...

Page 592: ...rigger When this bit is set trigger happens This bit is automatically cleared Trigger function is valid only when the LCD is enabled state ENVID 11b 0 WIN0 Palette RAM Access Address Register Address R W Description Reset Value WIN0_PALENTRY0 0x4C800400 R W Window 0 Palette entry 0 address Undefined WIN0_PALENTRY1 0x4C800404 R W Window 0 Palette entry 1 address Undefined WIN0_PALENTRY255 0x4C8007F...

Page 593: ...6x4096 pixels 2048x2048 pixels for scaling Two scalers exist The one is the preview scaler which is dedicated to generate smaller size image for preview The other one is the codec scaler which is dedicated to generate codec useful image like plane type YCbCr 4 2 0 or 4 2 2 Two master DMAs can do mirror and rotate the captured image for mobile environments And test pattern generation can be used to...

Page 594: ...dec DMA output image generation RGB 16 24 bit format or YCbCr 4 2 0 4 2 2 format Capture frame control support in codec_path Scan line offset support in codec_path and preview_path YCbCr 4 2 2 codec image format interleave support MSDMA supports memory data for preview path input Image effect EXTERNAL INTERFACE CAMIF can support the next video standards ITU R BT 601 YCbCr 8 bit mode ITU R BT 656 Y...

Page 595: ...ange without notice TIMING DIAGRAM VSYNC Y Cb Y Cr Y Cb Y Cb Y Cr HREF HREF 1H PCLK DATA 7 0 Vertical lines Horizontal width 1 frame 8 bit mode Figure 23 2 ITU R BT 601 Input timing diagram VSYN C FIELD Field 1 Field 2 VSYN C FIELD FieldMode 1 Field port connects with FIELD Figure 23 3 ITU R BT 601 interlace timing diagram PCLK DATA 7 0 Cr FF 00 00 XY Cb Y FF 00 00 XY Video timing reference codes ...

Page 596: ... 6 1 0 0 H 5 1 0 0 P3 4 1 0 0 P2 3 1 0 0 P1 2 1 0 0 P0 1 Note 1 0 0 0 0 1 0 0 0 NOTE For compatibility with existing 8 bit interfaces the values of bits D1 and D0 are not defined F 0 during field 1 1 during field 2 V 0 elsewhere 1 during field blanking H 0 in SAV Start of Active Video 1 in EAV End of Active Video P0 P1 P2 P3 protection bit Camera interface logic can catch the video sync bits like ...

Page 597: ...ction guide CAMERA INTERFACE OPERATION TWO DMA PORTS CAMIF has two DMA port P port Preview port and C port Codec port are separated from each other on AHB bus At the view of system bus two ports are independent The P port stores the RGB image data into memory for preview The C port stores the YCbCr 4 2 0 or 4 2 2 image data or RGB image data into memory for Codec as MPEG 4 H 263 etc These two mast...

Page 598: ...pecifications and information herein are subject to change without notice Frame Memory SDRAM P port C port ITU format Preview image RGB 16 24 bit Codec image YCbCr 4 2 0 or YCbCr 4 2 2 or RGB 16 24 bit Frame Memory SDRAM P port C port ITU format Preview image RGB 16 24 bit Codec image YCbCr 4 2 0 or YCbCr 4 2 2 RGB 16 24 bit Window cut External Camera Processor CAMIF External Camera Processor CAMI...

Page 599: ...al Camera Processor CAMIF MPLL fEmpll Divide Counter fmpll d fEPLL d or HCLK d EPLL 96 MHz or HCLK EPLL HCLK HCLK fEPLL Figure 23 8 CAMIF clock generation FRAME MEMORY HIRERARCHY Frame memories consist of four ping pong memories for each P and C ports C port ping pong memories have three element memories that are luminance Y chrominance Cb and chrominance Cr It is recommended that the arbitration ...

Page 600: ...ation herein are subject to change without notice 4 pingpong Frame memory SDRAM ITU 601 656 YCbCr 4 2 2 8 bits P port RGB 4 4 4 C port YCbCr 4 2 0 2 RGB 4 4 4 Camera Interface AHB bus Memorycontroller C port Y 1 RGB 1 C port Cb 1 C port Cr 1 C port Y 2 RGB 2 C port Cb 2 C port Cr 2 C port Y 3 RGB 3 C port Cb 3 C port Cr 3 C port Y 4 RGB 4 C port Cb 4 C port Cr 4 P port RGB 1 P port RGB 2 P port RG...

Page 601: ...e endian style For RGB format two different formats exist One pixel Color 1 pixel is one word for RGB 24 bit format Otherwise two pixels are one word for RGB 16 bit format Refer to next diagram Y frame memory PCLK DATA ITU 601 656 YCbCr 4 2 2 8 bit input timing Cb frame memory Cr frame memory Little endian method time Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 Cr2 Little endian method Little endian method RGB frame ...

Page 602: ...rame period But it is recommend to do first setting at the VSYNC L state VSYNC information can be read from status SFR Refer to the below figure All command include ImgCptEn is valid at VSYNC falling edge Be sure that except first SFR setting all command should be programmed in ISR Interrupt Service Routine It is not allowed for target size information to be changed during capture operation Howeve...

Page 603: ...re Read Memory New command SFR setting New command PreviewDMA end PIPDMA end Read start In capturing Image Capture Read Memory SFR setting ImgCptEn_PrSc SEL_DMA_CAM SFR setting SEL_DMA_CAM VSYNC HREF INTERRUPT New SFR command In Capturing Reserved Image Capture New command valid timing diagram New Command VSYNC HREF INTERRUPT SFR setting ImgCptEn Multi frame capturing Reserved Image Capture Frame ...

Page 604: ...nt is increased by 1 at IRQ rising Camera input capture path applied both Preview Codec path ISR region ISR region ISR region VSYNC ISR region ImgCptEn cmd LastIRQEn Capture O Capture O Capture O Capture X IRQ Auto cleared Last IRQ ISR region ISR region ISR region FrameCnt Capture O Capture O Frame_3 Frame_0 Frame_1 Frame_3 Frame_0 0 1 2 3 0 1 3 ISR region ISR region ISR region VSYNC ISR region Im...

Page 605: ...ture O Frame_1 ImgCptEn_PrSC FrameCnt Figure 23 12 Timing diagram for last IRQ MSDMA FEATURE MSDMA supports memory data scaling Camera interface has two input devices only preview path First is external camera Second is Memory data If MSDMA reading the memory data want to use in preview path SFR SEL_DMA_CAM signal should be set 1 This input path is called Memory Scaling DMA path NOTE Only two imag...

Page 606: ...e enable O change X not change SOURCE FORMAT REGISTER Register Address R W Description Reset Value CISRCFMT 0x4D80_0000 RW Source format register 0 CISRCFMT Bit Description Initial State Change State ITU601_656n 31 1 ITU R BT 601 YCbCr 8 bit mode enable 0 ITU R BT 656 YCbCr 8 bit mode enable 0 X UVOffset 30 Cb Cr value offset control 1 128 0 0 normally used 0 X In16bit 29 This bit must be 0 0 X So...

Page 607: ...nHorOfst2 WinVerOfst2 are assigned in the CIWDOFST2 register CIWDOFST Bit Description Initial State Change State WinOfsEn 31 1 window offset enable 0 no offset 0 O ClrOvCoFiY 30 1 clear the overflow indication flag of input CODEC FIFO Y 0 normal 0 X Reserved 29 27 0 X WinHorOfst 26 16 Window horizontal offset by pixel unit It should be 2 s multiple Caution SourceHsize WinHorOfst WinHorOfst2 should...

Page 608: ...change without notice NOTE Clear bits should be set by zero after clearing the flags It should be as WinHorOfst WinHorOfst2 SourceHsize 720 PreHorRatio_Pr Crop Hsize SourceHsize WinHorOfst WinHorOfst2 must be 4 s multiple of PreHorRatio Crop Vsize SourceVsize WinVerOfst WinVerOfst2 must be multiple of PreVerRatio when scale down and must be an even number if In422_Co 0 and Out422_Co 0 Example Crop...

Page 609: ...essor Reset or Power Down control 0 X Reserved 29 Must be 1 1 X TestPattern 28 27 This register should be set at only ITU T 601 8 bit mode Not allowed with ITU T 656 mode max 1280 X 1024 00 external camera processor input normal 01 color bar test pattern 10 horizontal increment test pattern 11 vertical increment test pattern 0 X InvPolPCLK 26 1 inverse the polarity of PCLK 0 normal 0 X InvPolVSYNC...

Page 610: ...escribe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Overflow preview IRQ_p IRQ_Cl_p Overflow codec IRQ_Ovfen IRQ_c IRQ_Cl_c Figure 23 15 Interrupt generation scheme ...

Page 611: ...SourceHsize WinHorOfst WinHorOfst2 should be 8 s multiple 0 O Reserved 15 11 0 X WinVerOfst2 10 0 Window vertical offset2 by pixel unit 0 O Y1 START ADDRESS REGISTER Register Address R W Description Reset Value CICOYSA1 0x4D80_0018 RW 1st frame start address for codec DMA 0 CICOYSA1 Bit Description Initial State Change State CICOYSA1 31 0 Output format YCbCr 4 2 2 or 4 2 0 Æ Y 1st frame start addr...

Page 612: ...0 Output format YCbCr 4 2 2 or 4 2 0 Æ Y 3rd frame start address Output format RGB 16 24 bit Æ RGB 3rd frame start address 0 X Y4 START ADDRESS REGISTER Register Address R W Description Reset Value CICOYSA4 0x4D80_0024 RW 4th frame start address for codec DMA 0 CICOYSA4 Bit Description Initial State Change State CICOYSA4 31 0 Output format YCbCr 4 2 2 or 4 2 0 Æ Y 4th frame start address Output fo...

Page 613: ...CB3 START ADDRESS REGISTER Register Address R W Description Reset Value CICOCBSA3 0x4D80_0030 RW Cb 3rd frame start address for codec DMA 0 CICOCBSA3 Bit Description Initial State Change State CICOCBSA3 31 0 Cb 3rd frame start address for codec DMA 0 X CB4 START ADDRESS REGISTER Register Address R W Description Reset Value CICOCBSA4 0x4D80_0034 RW Cb 4th frame start address for codec DMA 0 CICOCBS...

Page 614: ...r codec DMA 0 CICOCRSA2 Bit Description Initial State Change State CICOCRSA2 31 0 Cr 2nd frame start address for codec DMA 0 X CR3 START ADDRESS REGISTER Register Address R W Description Reset Value CICOCRSA3 0x4D80_0040 RW Cr 3rd frame start address for codec DMA 0 CICOCRSA3 Bit Description Initial State Change State CICOCRSA3 31 0 Cr 3rd frame start address for codec DMA 0 X CR4 START ADDRESS RE...

Page 615: ...e format This mode is mainly for S W JPEG 0 YCbCr 4 2 0 codec scaler output image format This mode is mainly for MPEG 4 codec and H W JPEG DCT normal It must not be set to 0 when In422_Co is set to 0 0 O Interleave_Co 29 1 Interleave ON support image format YCbCr 4 2 2 only Y0Cb0Y1Cr0Y2Cb1Y3Cr1 0 Interleave OFF Y0Y1Y2Y3 Cb0Cb1 Cr0Cr1 0 O TargetHsize_Co 28 16 Horizontal pixel number of target image...

Page 616: ...mation describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Original image X axis flip Y axis flip 180 rotation Figure 23 16 Codec image mirror and rotation ...

Page 617: ... format YCbCr Æ Remained burst length for codec Y frames Output format RGB Æ Remained burst length for RGB frame 0 X Cburst1_Co 13 9 Main burst length for codec Cb Cr frames 0 X Cburst2_Co 8 4 Remained burst length for codec Cb Cr frames 0 X Reserved 3 0 X LastIRQEn_Co 2 1 enable last IRQ at the end of frame capture It is recommended to check the done signal of capturing image for JPEG One pulse 0...

Page 618: ... 176 pixels 1 pixel 1 Byte 1 word 4 pixel 176 4 44 words 44 8 4 Æ main burst 8 remained burst 4 If Interleave_Co 1 and YCbCr 4 2 2 176 x 1 word 2 pixles 88 words 88 16 8 Æ Wanted main burst 16 Wanted remained burst 8 Wanted main burst 16 2 Yburst1 4 Cburst1 Wanted remained burst 8 2 Yburst2 4 Cburst2 Yburst1_Co 8 Yburst2_Co 4 Example 2 Target image size VGA horizontal Y width 640 pixels 1 pixel 1 ...

Page 619: ...TargetHsize_Pr DST_Width TargetHsize_xx DST_Height TargetVsize_xx SRC_Width SourceHsize WinHorOfst WinHorOfst2 SRC_Height SourceVsize WinVerOfst WinVerOfst2 SourceVsize TargetVsize_xx 3 1 4 2 1 2 3 4 Figure 23 17 Scaling scheme The other control registers of pre scaled image size pre scale ratio pre scale shift ratio and main scale ratio are defined according to the following equations If SRC_Widt...

Page 620: ...Shift Caution In preview path Pre scaled H_width must be the less than 720 The maximum size of preview path scaler s horizontal line buffer is 720 Example 1 Source image horizontal size SRC_Width 1280 Target image horizontal size DST_Width 480 SRC_Width 2 DST_Width PreHorRatio_xx 2 PreDstWidth_xx SRC_Width PreHorRatio_xx 1280 2 640 PreDstWidth_xx 640 640 The maximum size of preview path scaler s h...

Page 621: ...SCPRERATIO Bit Description Initial State Change State SHfactor_Co 31 28 Shift factor for codec pre scaler 0 O Reserved 27 23 0 X PreHorRatio_Co 22 16 Horizontal ratio of codec pre scaler 0 O Reserved 15 7 0 X PreVerRatio_Co 6 0 Vertical ratio of codec pre scaler 0 O CODEC PRE SCALER CONTROL REGISTER 2 Register Address R W Description Reset Value CICOSCPREDST 0x4D80_0054 RW Codec pre scaler destina...

Page 622: ...ended to capture JPEG input image for DSC application In this case input pixel buffering depends on only input FIFOs so system bus should be not busy in this mode 0 O ScaleUp_H_Co 30 Horizontal scale up down flag for codec scaler In 1 1 scale ratio this bit should be 1 1 up 0 down 0 O ScaleUp_V_Co 29 Vertical scale up down flag for codec scaler In 1 1 scale ratio this bit should be 1 1 up 0 down 0...

Page 623: ...t can be referred by CPU for first SFR setting after external camera muxing And it can be seen in the ITU R BT 656 mode 0 X FrameCnt_Co 27 26 Frame count of codec DMA This counter value means the next frame number 0 X WinOfstEn_Co 25 Window offset enable status 0 X FlipMd_Co 24 23 Flip mode of codec DMA 0 X ImgCptEn_ CamIf 22 Image capture enable of camera interface 0 X ImgCptEn_ CoSC 21 Image cap...

Page 624: ... CIPRCLRSA2 Bit Description Initial State Change State CIPRCLRSA2 v 31 0 RGB 2nd frame start address for preview DMA 0 X RGB3 START ADDRESS REGISTER Register Address R W Description Reset Value CIPRCLRSA3 0x4D80_0074 RW RGB 3rd frame start address for preview DMA 0 CIPRCLRSA3 Bit Description Initial State Change State CIPRCLRSA3 v 31 0 RGB 3rd frame start address for preview DMA 0 X RGB4 START ADD...

Page 625: ...image mirror and rotation CIPRTRGFMT Bit Description Initial State Change State CSCRange v 31 30 YCbCr Input Data Dynamic Range Selection for the Color Space Conversion 2 b11 Forbidden 2 b10 0 Y Cb Cr 255 Recommended 2 b01 16 Y 235 16 Cb Cr 240 2 b00 Reserved 2 b10 O Reserved 29 0 X TargetHsize_Pr v 28 16 Horizontal pixel number of target image for preview DMA 16bppRGB 4n n 1 2 3 24bpp RGB 2n n 1 ...

Page 626: ...served 31 24 0 X RGBburst1_Pr v 23 19 Main burst length for preview RGB frames 0 X RGBburst2_Pr v 18 14 Remained burst length for preview RGB frames 0 X Reserved 13 3 0 X LastIRQEn_Pr v 2 1 enable last IRQ at the end of frame capture One pulse 0 normal 0 X Reserved 1 0 0 X Main burst lengths must be one of the 4 8 16 and Remained burst lengths must be one of the 2 4 8 16 Example 1 Target image siz...

Page 627: ...PRERATIO Bit Description Initial State Change State SHfactor_Pr v 31 28 Shift factor for preview pre scaler 0 O Reserved 27 23 0 X PreHorRatio_Pr v 22 16 Horizontal ratio of preview pre scaler 0 O Reserved 15 7 0 X PreVerRatio_Pr v 6 0 Vertical ratio of preview pre scaler 0 O PREVIEW PRE SCALER CONTROL REGISTER 2 Register Address R W Description Reset Value CIPRSC PREDST 0x4D80_0088 RW Preview pre...

Page 628: ...it RGB 0 16 bit RGB 0 O ScaleUp_H_Pr v 29 Horizontal scale up down flag for preview scaler In 1 1 scale ratio this bit should be 1 1 up 0 down 0 O ScaleUp_V_Pr v 28 Vertical scale up down flag for preview scaler In 1 1 scale ratio this bit should be 1 1 up 0 down 0 O Reserved 27 25 0 X MainHorRatio_ Pr v 24 16 Horizontal scale ratio for preview main scaler 0 O PrScalerStart v 15 Preview scaler sta...

Page 629: ...otice PREVIEW STATUS REGISTER Register Address R W Description Reset Value CIPRSTATUS 0x4D80_0098 R Preview path status 0 CIPRSTATUS Bit Description Initial State Change State OvFiCb_Pr 31 Overflow state of preview FIFO Cb 0 X OvFiCr_Pr 30 Overflow state of preview FIFO Cr 0 X Reserved 29 28 0 X FrameCnt_Pr 27 26 Frame count of preview DMA 0 X Reserved 25 0 X FlipMd_Pr 24 23 Flip mode of preview D...

Page 630: ...served 28 27 0 X Cpt_CoDMA_ Sel 26 Codec DMA output format 1 RGB 16 24 bit Must be Out422_Co 1 Interleave_Co 1 0 YCbCr 4 2 2 or 4 2 0 0 O Cpt_CoDMA_ RGBFMT 25 Codec DMA RGB format 1 RGB 24 bit 0 RGB 16 bit 0 O Cpt_CoDMA_ En 24 Capture codec dma frame control It is also used for start signal of Codec image capture Therefore it must be set to 1 if codec image is wanted or it must be set to 0 if code...

Page 631: ...hout notice CODEC CAPTURE SEQUENCE REGISTER Register Address R W Description Reset Value CICOCPTSEQ 0x4D80_00A4 RW Codec dma capture sequence related 0xFFFFFFFF CICOCPTSEQ Bit Description Initial State Cpt_CoDMA_Seq 31 0 Capture sequence pattern in Codec DMA 0xFFFF_FFF F Cpt_CoDMA_Ptr 31 30 29 1 0 Cpt_CoDMA_Seq 31 0 Repeat Capture Capture No Capture Capture 1 1 1 0 1 0 Figure 23 19 Capture codec d...

Page 632: ... X Line_Yoffset_Co 12 0 The number of the skipped pixels in the screen of the target image when scan line is changed should be even number for word boundary alignment This value must be set to 0 when scanline offset is not used And scanline offset can be used only when Interleave_Co is set to 1 0 O PREVIEW SCAN LINE OFFSET REGISTER Register Address R W Description Reset Value CIPRSCOS 0x4D80_00AC ...

Page 633: ...duct information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Target image SCREEN Initial offset Line offset Figure 23 20 Scan line offset ...

Page 634: ...ed 0010_0080 CIIMGEFF Bit Description Initial State Change State Reserved 31 29 0 X FIN 28 26 Image Effect selection 3 b000 Bypass 3 b001 Arbitrary Cb Cr 3 b010 Negative 3 b011 Art Freeze 3 b100 Embossing 3 b101 Silhouette 0 O Reserved 25 21 0 X PAT_Cb 20 13 It is used only for FIN is Arbitrary Cb Cr PAT_Cb Cr 8 d128 for GRAYSCALE 16 PAT_Cb 223 8 d128 O Reserved 12 8 0 X PAT_Cr 7 0 It is used only...

Page 635: ...S REGISTER Register Address R W Description Reset Value CIMSCBSA 0x4D80_00B8 RW MSDMA Cb start address related 0000_0000 CIMSCBSA Bit Description Initial State Change State Reserved 31 0 X CIMSCBSA v 30 0 DMA start address for Cb component YCbCr 4 2 0 0 X MSDMA CR START ADDRESS REGISTER Register Address R W Description Reset Value CIMSCRSA 0x4D80_00BC RW MSDMA Cr start address related 0000_0000 CI...

Page 636: ...Description Initial State Change State Reserved 31 0 X CIMSCBEND v 30 0 DMA End address for Cb component YCbCr 4 2 0 0 X MSDMA CR END ADDRESS REGISTER Register Address R W Description Reset Value CIMSCREND 0x4D80_00C8 RW MSDMA Cr end address related 0000_0000 CIMSCREND Bit Description Initial State Change State Reserved 31 0 X CIMSCREND v 30 0 DMA End address for Cr component YCbCr 4 2 0 0 X MSDMA...

Page 637: ...tial State Change State Reserved 31 24 0 X CIMSCBOFF v 23 0 Offset of Cb component for fetching source image 0 X MSDMA CR OFFSET REGISTER Register Address R W Description Reset Value CIMSCROFF 0x4D80_00D4 RW MSDMA Cr offset related 0000_0000 CIMSCROFF Bit Description Initial State Change State Reserved 31 24 0 X CIMSCROFF v 23 0 Offset of Cr component for fetching source image 0 X MSDMA SOURCE IMA...

Page 638: ...for the YCbCr420 source image format MSDMA End address 1 ADDREnd_Y ADDRStart_Y Memory size for the component of Y ADDRStart_Y SRC_Width SRC_Height ByteSize_Per_Pixel Offset_Y SRC_Height 1 2 ADDREnd_Cb Valid for YCbCr420 source format ADDRStart_Cb Memory size for the component of Cb ADDRStart_Cb SRC_Width 2 SRC_Height 2 ByteSize_Per_Pixel Offset_Cb SRC_Height 2 1 3 ADDREnd_ Cr Valid for YCbCr420 so...

Page 639: ...ixed inside single word 0 X Order422_MS v 4 3 When source MSDMA image is interleaved YCbCr 4 2 2 Interleaved YCbCr 4 2 2 input memory storing style 4 3 LSB MSB 00 Y0Cb0Y1Cr0 01 Y0Cr0Y1Cb0 10 Cb0Y0Cr0Y1 11 Cr0Y0Cb0Y1 0 X SEL_DMA_CA M v 2 Preview path data selection codec path don t care 0 External camera input path 1 Memory data input path MSDMA 0 X SRC420_MS v 1 Source image format for MSDMA 0 YCb...

Page 640: ...subject to change without notice ENVID_MS start start 0 1 setting 1 0 setting 0 1 setting Figure 23 22 ENVID_MS SFR setting when DMA start to read memory data RGB start address Preview Target format Preview DMA Control etc Operation Done EOF signal generation Operation Done IRQ signal generation SFR SFR Memory MSDMA Scaler Preview DMA MSDMA Start End OFFSET MSDMA Source image width MSDMA control F...

Page 641: ... A D converter clock A D converter operates with on chip sample and hold function and power down standby mode is supported Touch screen interface can controls input pads XP XM YP and YM to obtain X Y positions on the external touch screen device Touch Screen Interface contains three main blocks these are touch screen pads control logic ADC interface logic and interrupt generation logic FEATURES Re...

Page 642: ...C TOUCH SCREEN INTERFACE OPERATION BLOCK DIAGRAM Figure 24 1 shows the functional block diagram of A D converter and touch screen interface Note that the A D converter device is a recycling type 10 1 MUX PULL_UP XM_SEN YM_SEN XP_SEN YP_SEN Touch screen pads control A D Converter ADC interface Touch screen control ADC input control Interrupt generation SUBINT_ADC SUBINT_TC Waiting for interrupt VDD...

Page 643: ...e converted data can be read out from ADC conversion data 0 register ADCDAT0 2 Separate X Y position conversion mode AUTO_PST 0 XY_PST contorl This mode consists of two states one is X position measurement state and the other is Y position measurement state X position measurement state is operated as the following way set XY_PST is 1 and read out the converted data X position from ADCDAT0 The end ...

Page 644: ...Standby Mode Standby mode is activated when ADCCON 2 is set to 1 In this mode A D conversion operation is halted and ADCDAT0 ADCDAT1 register contains the previous converted data Programming Notes 1 The A D converted data can be accessed by means of interrupt or polling method With interrupt method the overall conversion time from A D converter start to converted data read may be delayed because o...

Page 645: ...ess 1 End of A D conversion 0 PRSCEN 14 A D converter prescaler enable 0 Disable 1 Enable 0 PRSCVL 13 6 A D converter prescaler value Data value 5 255 Note that division factor is N 1 when the prescaler value is N Note ADC frequency should be set less than PCLK by 5 times Ex PCLK 10MHz ADC Frequency 2MHz 0xFF Reserved 5 4 Reserved 0 RESSEL 3 A D converter resolution selection 0 10 bit resolution 1...

Page 646: ...ble YP VDDA_ADC 1 Switch disable YP AIN7 Hi z 1 XM_SEN 5 XM to GND Switch Enable 0 Switch disable XM AIN8 Hi z 1 Switch enable XM VSSA_ADC 0 XP_SEN 4 XP to VDD Switch Enable 0 Switch enable XP VDDA_ADC 1 Switch disable XP AIN9 Hi z 1 PULL_UP 3 XP Pull up Switch Enable 0 XP pull up enable 1 XP pull up disable 1 AUTO_PST 2 Automatically sequencing conversion of X Position and Y Position 0 Normal ADC...

Page 647: ...ter Address R W Description Reset Value ADCDLY 0x58000008 R W ADC start or interval delay register 0x00ff ADCDLY Bit Description Initial State DELAY 15 0 Incase of ADC conversion mode Normal Separate Auto conversion ADC conversion is delayed by counting this value Counting clock is PCLK In case of waiting for interrupt mode When stylus down occurs in waiting for interrupt mode counts this value an...

Page 648: ...Waiting for Interrupt Mode 0 Stylus down state 1 Stylus up state AUTO_PST 14 Automatic sequencing conversion of X position and Y position mirroring AUTO_PST in ADCTSC register 0 Normal ADC conversion 1 Auto measurement of X position Y position XY_PST 13 12 Manual measurement of X position or Y position mirroring XY_PST in ADCTSC register 00 No operation mode 01 X position measurement 10 Y position...

Page 649: ...to measurement of X position Y position XY_PST 13 12 Manual measurement of X position or Y position mirroring XY_PST in ADCTSC register 00 No operation mode 01 X position measurement 10 Y position measurement 11 Waiting for Interrupt Mode YPDATA_12 11 10 When A D resolution is 12bit X position conversion MSB 2 bit data value Data value data 11 0 0 0xFFF YPDATA 9 0 Y position conversion data value ...

Page 650: ...subject to change without notice ADC CHANNEL MUX REGISTER ADCMUX Register Address R W Description Reset Value ADCMUX 0x5800018 R W Analog input channel select 0x0 ADCMUX Bit Description Initial State ADCMUX 3 0 Analog input channel select 0000 AIN 0 0001 AIN 1 0010 AIN 2 0011 AIN 3 0100 AIN 4 0101 AIN 5 0110 AIN 6 YM 0111 AIN 7 YP 1000 AIN8 XM 1001 AIN9 XP 0 NOTE When Touch Screen Pads YM YP XM XP...

Page 651: ...d select line and a clock line IIS interface transmits or receives sound data from external stereo audio codec For transmitting and receiving data two 32x16 FIFOs First In First Out data structures are included and DMA transfer mode for transmitting or receiving samples can be supported IIS specific clock can be supplied from internal system clock controller through IIS clock divider or direct clo...

Page 652: ... Diagram FUNCTIONAL DESCRIPTIONS IIS interface consists of register bank FIFOs shift registers clock control DMA finite state machine and channel control block as shown in Figure 25 1 Note that each FIFO has 32 bit width and 16 depth structure which contains left right channel data So FIFO access and data transfer are handled with left right pair unit Figure 25 1 shows the internal functional bloc...

Page 653: ...that is RX mode Let s distinguish Master Slave mode from TX RX mode Figure 25 2 shows the route of the root clock with internal master PCLK divided EPLL clock EPLLRefClock or external master External I2S clock mode setting in IIS clock control block and system controller Note that RCLK indicates root clock and this clock can be supplied to external IIS codec chip at internal master mode and slave ...

Page 654: ...t be latched into the receiver on the leading edge of the serial clock signal and so there are some restrictions when transmitting data that is synchronized with the leading edge The LR channel select line indicates the channel being transmitted I2SLRCLK may be changed either on a trailing or leading edge of the serial clock but it does not need to be symmetrical In the slave this signal is latche...

Page 655: ...ed errata are not yet available Specifications and information herein are subject to change without notice Figure 25 3 shows the audio serial format of IIS MSB justified and LSB justified Note that in this figure the word length is 16 bit and I2SLRCLK makes transition every 24 cycle of I2SSCLK BFS is 48 fs where fs is sampling frequency I2SLRCLK frequency Figure 25 3 IIS Audio Serial Data Formats ...

Page 656: ...0 5 6448 8 1920 11 2900 16 3840 22 5790 24 5760 32 7680 45 1580 49 1520 768fs 6 1440 8 4672 12 2880 16 9340 24 5760 33 8690 36 8640 49 1520 Note fs represents sampling frequency CODECLK Frequency fs 256 or 384 or 512 or 768 IIS CLOCK MAPPING TABLE On selecting BFS RFS and BLC bits of I2SMOD register user should refer to the following table Table 25 2 shows the allowable clock frequency mapping rel...

Page 657: ...peration If you don t distinguish Master Slave mode from TX RX mode you must study Master Slave mode and TX RX mode Refer Master Slave chapter 2 To configure I2SMOD register and I2SPSR IIS pre scaler register properly 3 To operate system in stability the internal TXFIFO should be almost full before transmission First of all DMA starts because of that reason 4 Basically IIS bus doesn t support the ...

Page 658: ...the processor or DMA can write upto 16 left right data samples After enabling the channel for transmission An Example sequence is as the following Ensure the PCLK and CLKAUDIO are coming correctly to the I2S controller and FLUSH the TX FIFO using the TFLUSH bit in the Please ensure that I2S Controller is configured in one of the following modes TX only mode TX RX simultaneous mode This can be done...

Page 659: ... are not yet available Specifications and information herein are subject to change without notice The Data is aligned in the TX FIFO for 8 bits channel or 16 bits channel BLC as shown RIGHT CHANNEL LEFT CHANNEL Figure 25 4 TX FIFO Structure for BLC 00 or BLC 01 LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 0 15 7 BLC 00 BLC 01 16 31 BLC 00 BL...

Page 660: ... to the bit clock SCLK and word select clock LRCLK The TXCHPAUSE in the I2SCON Register I2S Control Register can stop the serial data transmission on the I2SSDO The transmission is stopped once the current Left Right channel is transmitted If the control registers in the I2SCON Register I2S Control Register and I2SMOD Register I2S Mode Register are to be reprogrammed then it is advisable to disabl...

Page 661: ...CLKAUDIO are coming correctly to the I2S controller and FLUSH the RX FIFO using the RFLUSH bit in the I2SFIC Register I2S FIFO Control Register and the I2S controller is configured in any of the modes Receive only Receive Transmit simultaneous mode This can be done by Programming the TXR bit in the I2SMOD Register I2S Mode Register 1 Then Program the following parameters according to the need IMS ...

Page 662: ...a are not yet available Specifications and information herein are subject to change without notice The Data is aligned in the RX FIFO for 8 bits channel or 16 bits channel BLC as shown RIGHT CHANNEL LEFT CHANNEL Figure 25 6 RX FIFO Structure for BLC 00 or BLC 01 LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 0 15 7 BLC 00 BLC 01 16 31 BLC 00 B...

Page 663: ...n the I2SCON register can stop the serial data reception on the I2SSDI The reception is stopped once the current Left Right channel is received If the control registers in the I2SCON Register I2S Control Register and I2SMOD Register I2S Mode Register are to be reprogrammed then it is advisable to disable the RX channel The Status of RX FIFO can be checked by checking the bits in the I2SFIC Registe...

Page 664: ...ble 25 3 Register summary of IIS interface Register Address R W Description Reset Value IISCON 0x55000100 R W IIS interface control register 0x600 IISMOD 0x55000104 R W IIS interface mode register 0x0 IISFIC 0x55000108 R W IIS interface FIFO control register 0x0 IISPSR 0x5500010C R W IIS interface clock divider control register 0x0 IISTXD 0x55000110 W IIS interface transmit data register 0x0 IISRX...

Page 665: ...e value of LRP bit of I2SMOD register 0 Left when LRP bit is low or right when LRP bit is high 1 Right when LRP bit is low or left when LRP bit is high FTXEMPT 10 R Tx FIFO empty status indication 0 FIFO is not empty ready for transmit data to channel 1 FIFO is empty not ready for transmit data to channel FRXEMPT 9 R Rx FIFO empty status indication 0 FIFO is not empty 1 FIFO is empty FTXFULL 8 R T...

Page 666: ...ated at any time the channel operation will be halted after left right channel data transfer is completed 0 No pause operation 1 Pause operation TXDMACTIVE 2 R W Tx DMA active start DMA request Note that when this bit is set from high to low the DMA operation will be forced to stop immediately 0 Inactive 1 Active RXDMACTIVE 1 R W Rx DMA active start DMA request Note that when this bit is set from ...

Page 667: ...1 Get codec clock from external codec chip to CLKAUDIO Refer to Figure 25 2 IMS 11 10 R W IIS master or slave mode select and select source of codec clock 00 Master mode PCLK is source clock for I2SSCLK I2SLRCLK I2SCDCLK 01 Master mode CLKAUDIO is source clock for I2SSCLK I2SLRCLK CLKAUDIO EPLL EPLLRefCLK is source clock for I2SCDCLK 10 Slave mode PCLK is source clock for I2SCDCLK 11 Slave mode CL...

Page 668: ...ociated errata are not yet available Specifications and information herein are subject to change without notice 01 512 fs 10 384 fs 11 768 fs Even in the slave mode this bit should be set for correct BFS 2 1 R W Bit clock frequency select 00 32 fs where fs is sampling frequency 01 48 fs 10 16 fs 11 24 fs Even in the slave mode this bit should be set for correct 0 R W Reserved Program to zero ...

Page 669: ...o FTXCNT 12 8 R TX FIFO data count 0 16 RFLUSH 7 R W RX FIFO flush command 0 No flush 1 Flush 6 5 R W Reserved Program to zero FRXCNT 4 0 R RX FIFO data count 0 16 NOTES Tx FIFOs Rx FIFO has 32 bit width and 16 depth structure so FIFO data count value ranges from 0 to 16 IIS PRESCALER CONTROL REGISTER IISPSR Register Address Description Reset Value IISPSR 0x5500010C IIS interface clock divider con...

Page 670: ...data register 0x0000_0000 IISTXD Bit R W Description IISTXD 31 0 W TX FIFO write data Note that the left right channel data is allocated as the following bit fields R 23 0 L 23 0 when 24 bit BLC R 31 16 L 15 0 when 16 bit BLC R 23 16 L 7 0 when 8 bit BLC IIS RECEIVE REGISTER IISRXD Register Address Description Reset Value IISRXD 0x55000114 IIS interface receive data register 0x0000_0000 IISRXD Bit...

Page 671: ...ound data from external stereo audio codec For transmitting and receiving data three 32x16 TXFIFOs First In First Out and one 32x16 RXFIFO data structures are included and DMA transfer mode for transmitting or receiving samples can be supported IIS specific clock can be supplied from internal system clock controller through IIS clock divider or direct clock source FEATURE Up to 5 1ch IIS bus for a...

Page 672: ...lock Diagram FUNCTIONAL DESCRIPTIONS IIS interface consists of register bank FIFOs shift registers clock control DMA finite state machine and channel control block as shown in Figure 26 1 Note that each FIFO has 32 bit width and 16 depth structure which contains left right channel data So FIFO access and data transfer are handled with left right pair unit Figure 26 1 shows the internal functional ...

Page 673: ...dec that is RX mode Let s distinguish Master Slave mode from TX RX mode Figure 26 2 shows the route of the root clock with internal master PCLK divided EPLL clock EPLLRefClock or external master External I2S clock mode setting in IIS clock control block and system controller Note that RCLK indicates root clock and this clock can be supplied to external IIS codec chip at internal master mode and sl...

Page 674: ... must be latched into the receiver on the leading edge of the serial clock signal and so there are some restrictions when transmitting data that is synchronized with the leading edge The LR channel select line indicates the channel being transmitted I2SLRCLK may be changed either on a trailing or leading edge of the serial clock but it does not need to be symmetrical In the slave this signal is la...

Page 675: ...ciated errata are not yet available Specifications and information herein are subject to change without notice Figure 26 3 shows the audio serial format of IIS MSB justified and LSB justified Note that in this figure the word length is 16 bit and I2SLRCLK makes transition every 24 cycle of I2SSCLK BFS is 48 fs where fs is sampling frequency I2SLRCLK frequency Figure 26 3 IIS Audio Serial Data Form...

Page 676: ... 0960 5 6448 8 1920 11 2900 16 3840 22 5790 24 5760 32 7680 45 1580 49 1520 768fs 6 1440 8 4672 12 2880 16 9340 24 5760 33 8690 36 8640 49 1520 Note fs represents sampling frequency CODECLK Frequency fs 256 or 384 or 512 or 768 IIS CLOCK MAPPING TABLE On selecting BFS RFS and BLC bits of I2SMOD register user should refer to the following table Table 26 2 shows the allowable clock frequency mapping...

Page 677: ...re operation If you don t distinguish Master Slave mode from TX RX mode you must study Master Slave mode and TX RX mode Refer Master Slave chapter 2 To configure I2SMOD register and I2SPSR IIS pre scaler register properly 3 To operate system in stability the internal TXFIFO should be almost full before transmission First of all DMA starts because of that reason 4 Basically IIS bus doesn t support ...

Page 678: ...sor or DMA can write upto 16 left right data samples after enabling the channel for transmission An Example sequence is as the following Ensure the PCLK and CLKAUDIO are coming correctly to the I2S controller and FLUSH the TX FIFO using the TFLUSH bit in the I2SFIC Register I2S FIFO Control Register Please ensure that I2S Controller is configured in one of the following modes TX only mode TX RX si...

Page 679: ...rata are not yet available Specifications and information herein are subject to change without notice The Data is aligned in the TX FIFO for 8 bits channel or 16 bits channel BLC as shown RIGHT CHANNEL LEFT CHANNEL Figure 26 4 TX FIFO Structure for BLC 00 or BLC 01 LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 0 15 7 BLC 00 BLC 01 16 31 BLC 0...

Page 680: ...t to the serial bit clock SCLK and word select clock LRCLK The TXCHPAUSE in the I2SCON Register I2S Control Register can stop the serial data transmission on the I2SSDO The transmission is stopped once the current Left Right channel is transmitted If the control registers in the I2SCON Register I2S Control Register and I2SMOD Register I2S Mode Register are to be reprogrammed then it is advisable t...

Page 681: ...and CLKAUDIO are coming correctly to the I2S controller and FLUSH the RX FIFO using the RFLUSH bit in the I2SFIC Register I2S FIFO Control Register and the I2S controller is configured in any of the modes Receive only Receive Transmit simultaneous mode This can be done by Programming the TXR bit in the I2SMOD Register I2S Mode Register 1 Then Program the following parameters according to the need ...

Page 682: ...rrata are not yet available Specifications and information herein are subject to change without notice The Data is aligned in the RX FIFO for 8 bits channel or 16 bits channel BLC as shown RIGHT CHANNEL LEFT CHANNEL Figure 26 6 RX FIFO Structure for BLC 00 or BLC 01 LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 0 15 7 BLC 00 BLC 01 16 31 BLC ...

Page 683: ...SE in the I2SCON register can stop the serial data reception on the I2SSDI The reception is stopped once the current Left Right channel is received If the control registers in the I2SCON Register I2S Control Register and I2SMOD Register I2S Mode Register are to be reprogrammed then it is advisable to disable the RX channel The Status of RX FIFO can be checked by checking the bits in the I2SFIC Reg...

Page 684: ...S Table 26 3 Register summary of IIS interface Register Address R W Description Reset Value IISCON 0x55000000 R W IIS interface control register 0xC600 IISMOD 0x55000004 R W IIS interface mode register 0x0 IISFIC 0x55000008 R W IIS interface FIFO control register 0x0 IISPSR 0x5500000C R W IIS interface clock divider control register 0x0 IISTXD 0x55000010 W IIS interface transmit data register 0x0 ...

Page 685: ...ot empty Ready to transmit Data 1 TX FIFO2 is empty Not Ready to transmit Data FTX1EMPT 14 R TX FIFO1 empty Status Indication 0 TX FIFO1 is not empty Ready to transmit Data 1 TX FIFO1 is empty Not Ready to transmit Data FTX2FULL 13 R TX FIFO2 full Status Indication 0 TX FIFO2 is not full 1 TX FIFO2 is full FTX1FULL 12 R TX FIFO1 full Status Indication 0 TX FIFO1 is not full 1 TX FIFO1 is full LRI ...

Page 686: ...ommand Note that when this bit is activated at any time the channel operation will be halted after left right channel data transfer is completed 0 No pause operation 1 Pause operation RXCHPAUSE 3 R W Rx channel operation pause command Note that when this bit is activated at any time the channel operation will be halted after left right channel data transfer is completed 0 No pause operation 1 Paus...

Page 687: ...t mode 00 No Discard 01 I2STXD 15 0 Discard 10 I2STXD 31 16 Discard 11 Reserved DCE 17 16 R W Data Channel Enable 17 SD2 channel enable 16 SD1 channel enable 15 R W Reserved Program to Zero BLC 14 13 R W Bit Length Control Bit Which decides transmission of 8 16 bits per audio channel 00 16 Bits per channel 01 8 Bits Per Channel 10 24 Bits Per Channel 11 Reserved CDCLKCON 12 R W Determine direction...

Page 688: ... R W Left Right channel clock polarity select 0 Low for left channel and high for right channel 1 High for left channel and low for right channel SDF 6 5 R W Serial data format 00 IIS format 01 MSB justified left justified format 10 LSB justified right justified format 11 Reserved RFS 4 3 R W IIS root clock codec clock frequency select 00 256 fs where fs is sampling frequency 01 512 fs 10 384 fs 1...

Page 689: ...h command 0 No flush 1 Flush 14 13 R W Reserved Program to zero FTX0CNT 12 8 R TX FIFO0 data count 0 16 RFLUSH 7 R W RX FIFO flush command 0 No flush 1 Flush 6 5 R W Reserved Program to zero FRXCNT 4 0 R RX FIFO data count 0 16 NOTES Tx FIFOs Rx FIFO has 32 bit width and 16 depth structure so FIFO data count value ranges from 0 to 16 IIS PRESCALER CONTROL REGISTER IISPSR Register Address Descripti...

Page 690: ...mit data register 0x0000_0000 IISTXD Bit R W Description IISTXD 31 0 W TX FIFO write data Note that the left right channel data is allocated as the following bit fields R 23 0 L 23 0 when 24 bit BLC R 31 16 L 15 0 when 16 bit BLC R 23 16 L 7 0 when 8 bit BLC IIS RECEIVE REGISTER IISRXD Register Address Description Reset Value IISRXD 0x55000014 IIS interface receive data register 0x0000_0000 IISRXD...

Page 691: ...form Also Controller receives the stereo PCM data and the mono Mic data from Codec then store in memories This chapter describes the programming model for the AC97 Controller Unit The information in this chapter requires an understanding of the AC97 revision 2 0 specifications FEATURE Independent channels for stereo PCM In Slot3 Slot4 mono MIC In Slot 6 stereo PCM Out Slot3 Slot4 DMA based operati...

Page 692: ...er operation Also it says to program guide You must study AC Link Power down sequence and Wake up sequence BLOCK DIAGRAM Figure 27 1 shows the functional block diagram of S3C2451 AC97 Controller The AC97 signals form the AC link which is a point to point synchronous serial inter connecting that supports full duplex data transfers All digital audio streams and command status information are communi...

Page 693: ...451 AC97 Controller It has stereo Pulse Code Modulated PCM In Stereo PCM Out and mono Mic in buffers which consist of 16 bit 16 entries buffer It also has 20 bit I O shift register via AC link Command Addr Register Slot 1 Command Data Register Slot 2 PCM Out Buffer Regfile 16 bit x 2 x 16 Entry Slot 3 Slot4 PWDATA Response Data Register Slot 2 Mic In Buffer RegFile 16 bit x16 Entry Slot 6 PCM In B...

Page 694: ...dy Then you make codec ready interrupt enable You can check codec ready interrupt by polling or interrupt When interrupt is occurred you must de assert codec ready interrupt Now then you can transmit data from memory to register or from register to memory by using DMA or PIO directly to write data to register If internal FIFOs TX FIFO or RX FIFO is not empty then let data be transmitted In additio...

Page 695: ...gure 27 4 shows the slot definitions that the S3C2451 AC97 Controller supports The S3C2451 AC97 Controller provides synchronization for all data transaction on the AC link A data transaction is made up of 256 bits of information broken up into groups of 13 time slots and is called a frame Time slot 0 is called the Tag Phase and is 16 bits long The other 12 time slots are called the Data Phase The ...

Page 696: ...res the frame as follows In slot 0 the valid bit for 1 2 slots are set In slot 1 bit 19 is set read or clear write Bits 18 12 of slot 1 are configured to specify the index to the CODEC register Others are filled with 0 s reserved In slot 2 it configured with the data which is for writing because of output frame Slot 2 Command Data Port In slot 2 this is the write data with 16 bit resolution 19 4 i...

Page 697: ...atus data if the accompanying status address matches the last valid command address issued during the most recent read command For multiple sample rate output the CODEC examines its sample rate control registers its FIFOs states and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits to set active low SLOTREQ bits asserted during the current ...

Page 698: ... non valid bit positions in the slot with zeroes Slot 4 PCM Right channel audio Slot 4 which is audio input frame is the right channel audio output of the AC97 Codec If a sample has a resolution that is less than 16 bits the AC97 Codec fills all training non valid bit positions in the slot with zeroes Slot 6 Microphone Record Data The AC97 Controller only supports 16 bit resolution for the MIC in ...

Page 699: ...C link Set up the AC97 Controller so that it does not transmit data to slots 3 12 when it writes to the Power down register bit PR4 data 0x1000 and it does not require the Codec to process other data when it receives a power down request When the Codec processes the request it immediately transitions BITCLK and SDATA_IN to a logic low level The AC97 Controller drives SYNC and SDATA_OUT to a logic ...

Page 700: ...ugh the AC_GLBCTRL Asserting and deasserting nRESET activates BITCLK and SDATA_OUT All AC97 control registers are initialized to their default power on reset values nRESET is an asynchronous AC97 input Warm AC97 Reset A Warm AC97 reset reactivates the AC link without altering the current AC97 register values A warm reset is generated when BITCLK is absent and SYNC is driven high In normal audio fr...

Page 701: ...tice AC97 CONTROLLER STATE DIAGRAM IDLE INIT READY ACTIVE LP WARM 1 2 ACLINK_ON CODEC_READY TRANS_DATA NORMAL_SYNC PCLK rising 1 CODEC_READY TRANS_DATA POWER_DOWN WARM_RESET ACLINK_ON 5 CODEC_WAKEUP 5 4 3 6 8 7 6 7 8 2 3 4 9 9 9 9 9 9 COLD_RESET PRESETn Figure 27 9 AC97 State Diagram This is the state diagram of AC97 controller It is helpful to understand AC97 controller state machine State above ...

Page 702: ...Description Reset Value AC_GLBCTRL 0x5B000000 R W AC97 Global Control Register 0x00000000 AC_GLBSTAT 0x5B000004 R AC97 Global Status Register 0x00000001 AC_CODEC_CMD 0x5B000008 R W AC97 Codec Command Register 0x00000000 AC_CODEC_STAT 0x5B00000C R AC97 Codec Status Register 0x00000000 AC_PCMADDR 0x5B000010 R AC97 PCM Out In Channel FIFO Address Register 0x00000000 AC_MICADDR 0x5B000014 R AC97 Mic I...

Page 703: ...channel overrun interrupt enable 19 0 Disable 1 Enable FIFO is full 0 PCM out channel threshold interrupt enable 18 0 Disable 1 Enable FIFO is half empty 0 PCM in channel threshold interrupt enable 17 0 Disable 1 Enable FIFO is half full 0 MIC in channel threshold interrupt enable 16 0 Disable 1 Enable FIFO is half full 0 15 14 Reserved 00 PCM out channel transfer mode 13 12 00 Off 01 PIO 10 DMA 1...

Page 704: ...nterrupt 19 0 Not requested 1 Requested 0 PCM out channel threshold interrupt 18 0 Not requested 1 Requested 0 PCM in channel threshold interrupt 17 0 Not requested 1 Requested 0 MIC in channel threshold interrupt 16 0 Not requested 1 Requested 0 15 3 Reserved 0x000 Controller main state 2 0 000 Idle 001 Init 010 Ready 011 Active 100 LP 101 Warm 001 AC97 CODEC COMMAND REGISTER AC_CODEC_CMD When yo...

Page 705: ...us data 0x0000 NOTES If you want to read data from AC97 codec register via the AC_CODDEC_STAT register you should follow the steps 1 Write command address and data on the AC_CODEC_CMD register with Bit 23 1 2 Have a delay time 3 Read command address and data from AC_CODEC_STAT register AC97 PCM OUT IN CHANNEL FIFO ADDRESS REGISTER AC_PCMADDR To index the internal PCM FIFOs address Register Address...

Page 706: ... address 3 0 MIC in channel FIFO write address 0000 AC97 PCM OUT IN CHANNEL FIFO DATA REGISTER AC_PCMDATA This is PCM out in channel FIFO data register Register Address R W Description Reset Value AC_PCMDATA 0x5B000018 R W AC97 PCM Out In Channel FIFO Data Register 0x00000000 AC_PCMDATA Bit Description Initial State Right data 31 16 PCM out in right channel FIFO data Read PCM in right channel Writ...

Page 707: ...directional serial interface to an external Codec FEATURE Mono 16bit PCM 2 ports audio interface Master mode only this block always sources the main serial clock The sources of PCM clock are based on an internal PCLK or an External Clock Input 16bit 32depth and output 16bit 32depth FIFOs to buffer data DMA interface for Tx and or Rx SIGNALS Name Direction Description PCM0_SCLK PCM1_SCLK Output Ser...

Page 708: ...ta will be a undefined after the 16 bit word has completed The next PCMFSYNC will signal the start of the next PCM data word The TX FIFO provides the 16 bit data word to be serially shifted out This data is serially shifted out MSB first one bit per PCMSCLK The PCM serial output data PCMSOUT is clocked out using the rising edge of the PCMSCLK The MSB bit position relative to the PCMFSYNC is progra...

Page 709: ...ith the MSB configured one shift clock after the PCMFSYNC This MSB positioning corresponds to setting the TX_MSB_POS and RX_MSB_POS bits in PCMCTL register to be 1 PCMSYNC PCMSOUT 15 14 1 0 dont care 15 output output output PCMSCLK input pcm_irq sync to DSP clk 15 14 1 0 dont care 15 input internal PCMSIN PCMSOURCE_CLK datain_reg_valid Figure 28 2 PCM timing TX_MSB_POS RX_MSB_POS 1 Note In all cas...

Page 710: ...rata are not yet available Specifications and information herein are subject to change without notice PCM Input Clock Diagram 1 N PCLK External Clock CTL_SERCLK_SEL PCM PCMn_CDCLK Clock Divider PCM SOURCE_ CLK Figure 28 3 Input Clock Diagram for PCM S3C2451X PCM is able to select clock either PCLK or External Clock Refer figure 28 3 To enable clock gating please refer to the SYSCON part SCLKCON PC...

Page 711: ...000 PCM_CTL1 0x5C000100 R W PCM1 Main Control 0x00000000 PCM_CLKCTL0 0x5C000004 R W PCM0 Clock and Shift control 0x00000000 PCM_CLKCTL1 0x5C000104 R W PCM1 Clock and Shift control 0x00000000 PCM_TXFIFO0 0x5C000008 R W PCM0 TxFIFO write port 0x00010000 PCM_TXFIFO1 0x5C000108 R W PCM1 TxFIFO write port 0x00010000 PCM_RXFIFO0 0x5C00000C R W PCM0 RxFIFO read port 0x00010000 PCM_RXFIFO1 0x5C00010C R W ...

Page 712: ...XFIFO_DIPSTICK 18 13 Determines when the almost_full almost_empty flags go active for the TXFIFO TXFIFO_ALMOST_EMPTY txfifo_depth txfifo_dipstick TXFIFO_ALMOST_FULL txfifo_depth 32 txfifo_dipstick NOTE If txfifo_dipstick is 0 Almost_empty Almost_full are invalid For DMA loading of TX fifo Txfifo_dipstick should be equal to 2 or greater than 2 txfifo_dipstick 2 This is required since the PCM_TXDMA ...

Page 713: ...RXFIFO_ALMOST_FULL acting as a rx_fifo_not_empty flag as a not RXFIFO_EMPTY 0 PCM_TX_DMA_EN 6 Enable the DMA interface for the TXFIFO DMA must operate in the demand mode DMA_TX request will occur whenever the TXFIFO is not almost full 0 PCM_RX_DMA_EN 5 Enable the DMA interface for the RXFIFO DMA must operate in the demand mode DMA_RX request will occur whenever the RXFIFO is not empty 0 TX_MSB_POS...

Page 714: ...ABLE 0 PCM enable signal 1 Enables the serial shift state machines 2 The enable must be set HIGH for the PCM to operate 0 The PCMSOUT will not toggle The internal divider counters serial shift register s counter are held in reset 3 0 NOTE 1 To flush FIFO first set PCM_TX RXFIFO_EN 0x0 then set PCM_TX RXFIFO_EN 0x1 2 To Start PCM operation please refer the following steps PCM_TXFIFO_EN 0x1 PCM_TX_D...

Page 715: ...scription Initial State Reserved 31 20 Reserved CTL_SERCLK_EN 19 Enable the serial clock division logic Must be HIGH for the PCM to operate if it is high PCMSCLK and PCMFSYNC is operated 1 0 CTL_SERCLK_SEL 18 Select the source of the PCMSOURCE_CLK 0 External clock 1 PCLK 0 SCLK_DIV 17 9 Controls the divider used to create the PCMSCLK based on the PCMSOURCE_CLK 1 2 1 1024 PCMSLCK will be PCMSOURCE_...

Page 716: ...TXFIFO0 0x5C000008 R W PCM0 interface Transmit FIFO data register 0x00010000 PCM_TXFIFO1 0x5C000108 R W PCM1 interface Transmit FIFO data register 0x00010000 The bit definitions for the PCM_TXFIFO Register are shown below PCM_TXFIFOn Bit Description Initial State Reserved 31 17 Reserved TXFIFO_DVALID 16 TXFIFO data is valid Write don t care Read TXFIFO read data valid 1 valid 0 invalid probably re...

Page 717: ..._RXFIFO0 0x5C00000C R W PCM0 interface Receive FIFO data register 0x00010000 PCM_RXFIFO1 0x5C00010C R W PCM1 interface Receive FIFO data register 0x00010000 The bit definitions for the PCM_RXFIFO Register are shown below PCM_RXFIFOn Bit Description Initial State Reserved 31 17 Reserved RXFIFO_DVALID 16 RXFIFO data is valid Write don t care Read TXFIFO read data valid 1 valid 0 invalid probably rea...

Page 718: ... Reserved EN_IRQ_TO_ARM 14 Controls whether the PCM interrupt is sent to the ARM or not 1 PCM IRQ is forwarded to the ARM subsystem 0 PCM IRQ is NOT forwarded to the ARM subsystem 0 Reserved 13 Reserved 0 TRANSFER_DONE 12 Interrupt is generated every time the serial shift for a 16bit PCM Data word completes 1 IRQ source enabled 0 IRQ source disabled 0 TXFIFO_EMPTY 11 Interrupt is generated wheneve...

Page 719: ...ll This is considered an ERROR and will have unexpected results 1 IRQ source enabled 0 IRQ source disabled 0 RXFIFO_EMPTY 5 Interrupt is generated whenever the RxFIFO is empty 1 IRQ source enabled 0 IRQ source disabled 0 RXFIFO_ALMOST_ EMPTY 4 Interrupt is generated whenever the RxFIFO is ALMOST_EMPTY which is defined as RX_FIFO_DEPTH RX_FIFO_DIPSTICK 1 IRQ source enabled 0 IRQ source disabled 0 R...

Page 720: ...iated errata are not yet available Specifications and information herein are subject to change without notice PCM_IRQ_CTLn Bit Description Initial State RXFIFO_ERROR_ OVERFLOW 0 Interrupt is generated for RxFIFO overflow ERROR This occurs whenever the RxFIFO is written when it is already full This is considered an ERROR and will have unexpected results 1 IRQ source enabled 0 IRQ source disabled 0 ...

Page 721: ...13 Monitoring PCM IRQ 1 PCM IRQ is occurred 0 PCM IRQ is not occurred 0 TRANSFER_DONE 12 Interrupt is generated every time the serial shift for a word completes 1 IRQ is occurred 0 IRQ is not occurred 0 TXFIFO_EMPTY 11 Interrupt is generated whenever the TX FIFO is empty 1 IRQ is occurred 0 IRQ is not occurred 0 TXFIFO_ALMOST _EMPTY 10 Interrupt is generated whenever the TxFIFO is ALMOST empty 1 I...

Page 722: ...curred 0 IRQ is not occurred 0 RX_FIFO_FULL 3 Interrupt is generated whenever the RX FIFO is full 1 IRQ is occurred 0 IRQ is not occurred 0 RX_FIFO_ALMOST _FULL 2 Interrupt is generated whenever the RX FIFO is ALMOST full 1 IRQ is occurred 0 IRQ is not occurred 0 RXFIFO_ERROR _STARVE 1 Interrupt is generated for RX FIFO starve ERROR This occurs whenever the RX FIFO is read when it is still empty T...

Page 723: ...it definitions for the PCM_FIFO_STATUS Register are shown below PCM_FIFO_STATn Bit Description Initial State Reserved 31 20 Reserved TXFIFO_COUNT 19 14 TX FIFO data count 0 32 0 TXFIFO_EMPTY 13 1 TXFIFO is empty 0 TXFIFO is not empty 0 TXFIFO_ALMOST_EMPTY 12 1 TXFIFO is ALMOST_EMPTY 0 TXFIFO is not ALMOST_EMPTY 0 TXFIFO_FULL 11 1 TXFIFO is full 0 TXFIFO is not full 0 TXFIFO_ALMOST_FULL 10 1 TXFIFO...

Page 724: ... routine is responsible for clearing interrupt asserted Writing any values on this register clears interrupts for ARM Reading this register is not allowed Clearing interrupt must be prior to resolving the interrupt condition otherwise another interrupt that would occur after this interrupt may be ignored Register Address R W Description Reset Value PCM_CLRINT0 0x5C000020 W PCM0 INTERRUPT CLEAR PCM...

Page 725: ...rmation herein are subject to change without notice 29 ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 29 1 Absolute Maximum Rating Parameter Symbol Min Max Unit VDDi VDDiarm VDDalive VDDA_MPLL VDDA_EPLL VDDI_UDEV 0 5 1 8 DC Supply Voltage VDD_OP1 VDD_OP2 VDD_RTC VDD_SDRAM VDD_SRAM VDD_CAM VDD_SD VDDA_ADC V DDA33x 0 5 4 8 DC Input Voltage VIN 0 5 4 8 DC Output Voltage VOUT 0 5 4 8 V DC Input Curren...

Page 726: ..._EPLL TBD DC Supply Voltage for Core Block 66 66 MHz VDDiarm VDDi VDDA_MPLL VDDA_EPLL TBD DC Supply Voltage for I O Block1 VDD_OP1 2 3 2 5 3 3 3 6 DC Supply Voltage for I O Block2 VDD_OP2 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for Memory Interface VDD_SRAM VDD_SDRAM 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for RTC VDD_RTC 2 5 3 0 3 6 VDD_CAM VDD_SD 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for CAM SD LCD ...

Page 727: ...rm TBD DC Supply Voltage for Core Block 66 66 MHz VDDi VDDA_MPLL VDDA_EPLL TBD DC Supply Voltage for I O Block1 VDD_OP1 2 3 2 5 3 3 3 6 DC Supply Voltage for I O Block2 VDD_OP2 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for Memory Interface VDD_SRAM VDD_SDRAM 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for RTC VDD_RTC 2 5 3 0 3 6 VDD_CAM VDD_SD 1 7 1 8 2 5 3 3 3 6 DC Supply Voltage for CAM SD LCD VDD_LCD 2 3...

Page 728: ...533MHz TBD V Temp Ambient Temperature 40 25 85 C Vih dc Input Logic High 0 7 VDD_OP V Vil dc Input Logic Low 0 3 VDD_OP V VT Switching threshold 0 5 VDD_OP V VT Schmitt trigger positive going threshold 0 7 VDD_OP V VT Schmitt trigger negative going threshold 0 3 VDD_OP V Iih High Level Input Current 10 10 uA Iil Low Level Input Current 10 10 uA Vext 3 3V 10 33 72 Vext 2 5V 5 18 40 Iih High Level I...

Page 729: ...Current 10 10 uA Iil Low Level Input Current 10 10 uA Iih High Level Input Current with Pull Down 20 60 uA Iil Low Level Input Current with Pull Up 60 20 uA Voh Output High Voltage Ioh 100uA VDDsdram 0 2 V Vol Output Low Voltage Iol 100uA 0 2 V Table 29 5 USB DC Electrical Characteristics Symbol Parameter Condition Min Max Unit VIH High level input voltage 2 5 V VIL Low level input voltage 0 8 V I...

Page 730: ...ons and information herein are subject to change without notice A C ELECTRICAL CHARACTERISTICS 1 2 VDD_OP1 1 2 VDD_OP1 tXTALCYC NOTE The clock input from the XTIpll pin Figure 29 1 XTIpll Clock Timing tEXTHIGH 1 2 VDD_OP1 VIL VIL VIH VIH 1 2 VDD_OP1 tEXTLOW tEXTCYC NOTE The clock input from the EXTCLK pin Figure 29 2 EXTCLK Clock Input Timing HCLK internal EXTCLK tEX2HC Figure 29 3 EXTCLK HCLK in ...

Page 731: ...in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice HCLK internal SCLK CLKOUT HCLK tHC2CK tHC2SCLK Figure 29 4 HCLK CLKOUT SCLK in case that EXTCLK is used EXTCLK tRESW nRESET Figure 29 5 Manual Reset Input Timing ...

Page 732: ...errata are not yet available Specifications and information herein are subject to change without notice nRESET XTIpll or EXTCLK VCO output MCU operates by XTIpll or EXTCLK clcok Clock Disable tPLL FCLK is new frequency Power PLL can operate after OM 3 2 is latched PLL is configured by S W first time VCO is adapted to new clock frequency FCLK tRST2RUN Figure 29 6 Power On Oscillation Setting Timing...

Page 733: ...for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice XTIpll VCO Output Clock Disable FCLK Several slow clocks XTIpll or EXTCLK Sleep mode is initiated tOSC2 EXTCLK Wake up from sleep mode Figure 29 7 Sleep Mode Return Oscillation Setting Timing ...

Page 734: ...t information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 29 8 SMC Synchronous Read Timing Figure 29 9 SMC Asynchronous Read Timing ...

Page 735: ...n development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice tCSD_A tADDRD_A tWED tDOD_A Asynchronous Write SMCLK RADDR RDATA nRCS nRWE A D A Figure 29 10 SMC Asynchronous Write Timing Figure 29 11 SMC Synchronous Write Timing ...

Page 736: ...formation describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice RADDR 26 0 RDATA 31 0 nRCS nROE nW AIT A D A SMCLK tW S tHS Figure 29 12 SMC Wait Timing ...

Page 737: ...rein are subject to change without notice TACLS TWRPH0 TWRPH1 COMMAND TWRPH0 TWRPH1 ADDRESS RDATA 15 0 HCLK FCLE nFWE tCLED tCLED tWED tWED tWDD tWDD tALED tWED tALED tWED tWDD TACLS tWDD TWRPH0 TWRPH1 ADDRESS tWDD tALED tWED tALED tWED tWDD TACLS Nand booting After Nand booting HCLK nFWE TWRPH0 TWRPH1 HCLK nFRE TWRPH0 TWRPH1 RDATA tWED tWED tWDD tRED tRED tRDS tRDH tWDD WDATA RDATA 15 0 HCLK FALE...

Page 738: ...y product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 29 14 SDRAM READ WRITE Timing Trp 2 Trcd 2 Tcl 2 DW 16 bit ...

Page 739: ...that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice SCLK nSRAS tSAD nSCAS SDATA SADDR DQMx tSRD SCKE A10 AP nSCSx tSCSD nSWE tSAD tSCD tSWD 1 tSAD tSCSD tSRD HZ 1 tSWD Figure 29 15 SDRAM MRS Timing ...

Page 740: ...on data and associated errata are not yet available Specifications and information herein are subject to change without notice SCLK nSRAS tSAD Trp nSCAS SDATA SADDR DQMx tSRD SCKE A10 AP nSCSx tSCSD nSWE tSAD tSCD tSWD 1 tSAD tSCSD tSRD 1 1 HZ Trc NOTE Before executing auto self refresh command all banks must be in idle state Figure 29 16 SDRAM Auto Refresh Timing Trp 2 Trc 4 ...

Page 741: ...d errata are not yet available Specifications and information herein are subject to change without notice HCLK tXRS tXRS tCADL tCADH tXAD nXDREQ nXDACK Read Write Min 3SCLK Figure 29 17 External DMA Timing Handshake Single transfer VSYNC HSYNC VDEN Tf2hsetup Tf2hhold Tvspw Tvbpd Tvfpd HSYNC VCLK VD VDEN Tl2csetup Tvclkh Tvclk Tvclkl Tvdhold Tvdsetup Tve2hold Figure 29 18 TFT LCD Controller Timing ...

Page 742: ... yet available Specifications and information herein are subject to change without notice I2SLRCLK Output I2SSCLK Output I2SSDO Output TLRId TDS TDH Figure 29 19 IIS Interface Timing I2S Master Mode Only I2SLRCLK Input I2SSCLK Input I2SSDI Input TLRId TDS TDH Figure 29 20 IIS Interface Timing I2S Slave Mode Only tSTOPH tSTARTS tSDAS tSDAH tBUF tSCLHIGH tSCLLOW fSCL IICSCL IICSDA Figure 29 21 IIC I...

Page 743: ...nt for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 29 22 SD MMC Interface Timing SD0_CLK tHSDCD SD0_CMD out tHSDCH tHSDCS tHSDDD SD0_CMD in tHSDDH tHSDDS SD0_DAT 7 0 out SD0_DAT 7 0 in Figure 29 23 High Speed SDMMC Interface Timing ...

Page 744: ...ta are not yet available Specifications and information herein are subject to change without notice tSPIMOD tSPISIH tSPISIS tSPISOD tSPIMIH tSPIMIS SPIMOSI MO SPIMOSI SI SPIMISO SO SPIMISO MI SPICLK Figure 29 24 SPI Interface Timing CPHA 1 CPOL 1 SPICLK tSPIMIH tSPIMIS SPIMOSI MO SPIMOSI SI SPIMISO MI tSPIMOD tSPISIS tSPISIH SPIMISO SO tSPISOD Figure 29 25 High Speed SPI Interface Timing CPHA 0 CP...

Page 745: ...t are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice VCRS Differential Data Lines TR TF 90 10 90 10 Rise Time Fall Time Figure 29 26 USB Timing Data signal rise fall time Figure 29 27 PCM Interface Timing ...

Page 746: ... MHz External clock input cycle time 1 tEXTCYC 7 5 100 ns External clock input low level pulse width tEXTLOW 3 5 ns External clock input high level pulse width tEXTHIGH 3 5 ns External clock to HCLK without PLL tEX2HC 5 13 ns HCLK internal to CLKOUT tHC2CK 3 3 8 8 ns HCLK internal to SCLK tHC2SCLK 1 9 5 8 ns Reset assert time after clock stabilization tRESW 4 XTIpll or EXTCLK PLL Lock Time tPLL 30...

Page 747: ... 9 SMC Chip Select Delay tCSD bank5 2 4 7 1 SMC Output Enable Delay tOED 2 1 6 3 ns SMC Write Enable Delay tWED 2 2 6 3 ns SMC Address Delay tADDRD 2 5 7 3 ns SMC Data Output Delay tDOD 3 1 8 9 ns SMC nWAIT setup time tWS 2 3 5 ns SMC nWAIT hold time tWH 0 0 ns Table 29 14 NFCON Bus Timing Constants VDDi 1 3V 0 05V 400MHz VDDi TBD V 0 05V 533MHz TA 40 to 85 C VDD_SRAM 1 8V 0 1V Parameter Symbol Mi...

Page 748: ...MHz CL 25pF Parameter Symbol Min Max Unit SDRAM Address Delay tSAD 1 58 5 61 ns SDRAM Chip Select Delay tSCSD 1 98 5 27 ns SDRAM Row active Delay tSRD 1 88 4 67 ns SDRAM Column active Delay tSCD 1 63 3 96 ns SDRAM Byte Enable Delay tSBED 1 80 4 58 ns SDRAM Write enable Delay tSWD 2 13 5 51 ns SDRAM read Data Setup time tSDS 1 50 ns SDRAM read Data Hold time tSDH 1 50 ns SDRAM output Data Delay tSD...

Page 749: ..._LCD 3 3V 0 3V Parameter Symbol Min Typ Max Units VCLK pulse width Tvclk 18 200 ns VCLK pulse width high Tvclkh 0 3 Pvclk 1 VCLK pulse width low Tvclkl 0 3 Pvclk Vertical sync pulse width Tvspw VSPW 1 Phclk 2 Vertical back porch delay Tvbpd VBPD 1 Phclk Vertical front porch dealy Tvfpd VFPD 1 Phclk Hsync setup to VCLK falling edge Tl2csetup 0 3 Pvclk VDEN set up to VCLK falling edge Tde2csetup 0 3...

Page 750: ... 3V 0 05V 400MHz VDDi TBD V 0 05V 533MHz TA 40 to 85 C VDD_OP2 3 3V 0 3V Parameter Symbol Min Typ Max Unit SCL clock frequency fSCL std 100 fast 400 kHz SCL high level pulse width tSCLHIGH std 4 0 fast 0 6 μs SCL low level pulse width tSCLLOW std 4 7 fast 1 3 μs Bus free time between STOP and START tBUF std 4 7 fast 1 3 μs START hold time tSTARTS std 4 0 fast 0 6 μs SDA hold time tSDAH std 0 fast ...

Page 751: ...Timing Constants VDDi 1 3V 0 05V 400MHz VDDi TBD V 0 05V 533MHz TA 40 to 85 C VDD_SD 3 3V 0 3V Parameter Symbol Min Typ Max Unit SPI MOSI Master Output Delay time tSPIMOD 0 1 3 ns SPI MOSI Slave Input Setup time tSPISIS 0 0 0 0 ns SPI MOSI Slave Input Hold time tSPISIH 0 0 0 0 ns SPI MISO Slave output Delay time tSPISOD 4 4 15 0 ns SPI MISO Master Input Setup time tSPIMIS 0 13 0 ns SPI MISO Master...

Page 752: ...ifications VDD12V 1 2V 5 TA 40 to 85 C VDDA33x 3 3V 0 3V Parameter Symbol Condition Min Max Unit Supply Current Suspend Device ICCS µA Leakage Current Hi Z state Input Leakage ILO 0V VIN 3 3V 10 10 µA Input Levels Differential Input Sensitivity VDI D D 0 2 V Differential Common Mode Range VCM Includes VDI range 0 8 2 5 Single Ended Receiver Threshold VSE 0 8 2 0 Output Levels Static Output Low VOL...

Page 753: ...over Voltage VCRS 1 3 2 0 V Drive Output Resistance ZDRV Steady state drive 28 43 ohm Table 29 26 USB High Speed Output Buffer Electrical Characteristics VDDi 1 3V 0 05V 400MHz VDDi TBD V 0 05V 533MHz TA 40 to 85 C VDDA33x 3 3V 0 3V Parameter Symbol Condition Min Max Unit Driver Characteristics Transition Time Rising Time Falling Time TR TF 500 500 ps ps Drive Output Resistance ZDRV Steady state d...

Page 754: ...ions and information herein are subject to change without notice Table 29 28 PCM Interface Timing VDDI 1 0V 0 05V TA 40 to 85 C VDD 3 3V 0 3V 2 5V 0 2V 1 8V 0 1V Parameter Symbol Min Typ Max Unit PCMSCLK clock width 1 tCW 0 128 8 192 MHz PCMSCLK to PCMFSYNC delay tdFSYNC 0 5 ns PCMSCLK to PCMSOUT delay tdSOUT 0 5 ns PCMSIN setup time tsetupSIN 15 ns PCMSIN hold time tholdSIN 10 ns NOTE This table ...

Page 755: ...rmation describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice 30 MECHANICAL DATA PACKAGE DIMENSIONS Figure 30 1 380 FBGA 1414 Package Dimension 1 Top View ...

Page 756: ...nary product information describe products that are in development for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice Figure 30 2 380 FBGA 1414 Package Dimension 2 Bottom View ...

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