Preliminary
S3C2451X RISC MICROPROCESSOR
HS_SPI
CONTROLLER
20-9
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
0 ~ 7’h40 byte
RxOverrun [5]
R
Rx Fifo overrun error
0: no error, 1: overrun error
1’b0
RxUnderrun [4]
R
Rx Fifo underrun error
0: no error, 1: underrun error
1’b0
TxOverrun [3]
R
Tx Fifo overrun error
0: no error, 1: overrun error
1’b0
TxUnderrun [2]
R
Tx Fifo underrun error
0: no error, 1: underrun error
*If TX fifo empty, always occur at slave mode
1’b0
RxFifoRdy [1]
R
0 : data in FIFO less than trigger level
1 : data in FIFO more than trigger level
1’b0
TxFifoRdy [0]
R
0 : data in FIFO more than trigger level
1 : data in FIFO less than trigger level
1’b0
Register Address
R/W
Description
Reset
Value
HS_SPI_TX_DATA(Ch0)
0x52000018
W HS_SPI TX DATA register
0x0
HS_SPI_TX_DATA(Ch1)
0x59000018
W HS_SPI TX DATA register
0x0
HS_SPI_TX_DATA Bit
Description
Initial
State
TX_DATA [31:0]
W
This field contains the data to be transmitted over
the HS_SPI channel.
32’b0
Register Address
R/W
Description
Reset
Value
HS_SPI_RX_DATA(Ch0)
0x5200001C R
HS_SPI RX DATA register
0x0
HS_SPI_RX_DATA(Ch1)
0x5900001C R
HS_SPI RX DATA register
0x0
HS_SPI_RX_DATA Bit
Description
Initial
State
RX_DATA [31:0]
R
This field contains the data to be received over
32’b0
