Preliminary
S3C2451X RISC MICROPROCESSOR
HS_SPI
CONTROLLER
20-7
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
RxTrigger [16:11]
R/W
Rx FIFO trigger level in INT mode.
Trigger level is from 0 to 63. The value means
byte number in RX FIFO
6’b0
TxTrigger [10:5]
R/W
Tx FIFO trigger level in INT mode
Trigger level is from 0 to 63. The value means
byte number in TX FIFO
6’b0
reserved [4:3]
-
- -
RxDMA On
[2]
R/W
DMA mode on/off
0 : DMA mode off 1 : DMA mode on
1’b0
TxDMA On
[1]
R/W
DMA mode on/off
0 : DMA mode off 1 : DMA mode on
1’b0
DMA transfer
[0]
R/W
DMA transfer type, single or 4 bust.
0 : single 1 : 4 burst
DMA transfer size should be set as the same
size in DMA as it in HS_SPI.
1’b0
** Channel Transfer size must be smaller than Bus Transfer size or the same as.
Register Address
R/W
Description
Reset
Value
Slave_slection_reg(Ch0)
0x5200000C
R/W
Slave selection signal
0x1
Slave_slection_reg(Ch1)
0x5900000C
R/W
Slave selection signal
0x1
Slave_slection_reg
Bit
Description
Initial State
nCS_time_count [9:4]
R/W
nSSout inactive time =
((nCS_tim3)/2) x HS_SPICLKout)
6’b0
reserved [3:2]
-
reserved -
Auto_n_Manual [1]
R/W
Chip select toggle manual or auto selection
0: manual 1: Auto
1’b0
nSSout [0]
R/W
Slave selection signal( manual only)
0: active 1: inactive
1’b1
Register Address
R/W
Description
Reset
Value
HS_SPI_INT_EN(Ch0) 0x52000010
R/W
HS_SPI Interrupt Enable register
0x0
HS_SPI_INT_EN(Ch1) 0x59000010
R/W
HS_SPI Interrupt Enable register
0x0
