Preliminary
UART
S3C2451 RISC MICROPROCESSOR
15-14
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
UART TX/RX STATUS REGISTER
There are four UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1, UTRSTAT2 and UTRSTAT3 in
the UART block.
Register Address
R/W
Description
Reset
Value
UTRSTAT0
0x50000010
R
UART channel 0 Tx/Rx status register
0x6
UTRSTAT1
0x50004010
R
UART channel 1 Tx/Rx status register
0x6
UTRSTAT2
0x50008010
R
UART channel 2 Tx/Rx status register
0x6
UTRSTAT3 0x5000C010
R
UART
channel
3 Tx/Rx status register
0x6
UTRSTATn Bit
Description
Initial
State
Transmitter
empty
[2]
Set to 1 automatically when the transmit buffer register has no
valid data to transmit and the transmit shift register is empty.
0 = Not empty
1 = Transmitter (transmit buffer & shifter register) empty
1
Transmit buffer
empty
[1]
Set to 1 automatically when transmit buffer register is empty.
0 =The buffer register is not empty
1 = Empty
(In Non-FIFO mode, Interrupt or DMA is requested.
In FIFO mode, Interrupt or DMA is requested, when Tx
FIFO Trigger Level is set to 00 (Empty))
If the UART uses the FIFO, users should check Tx FIFO Count
bits and Tx FIFO Full bit in the UFSTAT register instead of this
bit.
1
Receive buffer
data ready
[0]
Set to 1 automatically whenever receive buffer register contains
valid data, received over the RXDn port.
0 = Empty
1 = The buffer register has a received data
(In Non-FIFO mode, Interrupt or DMA is requested)
If the UART uses the FIFO, users should check Rx FIFO Count
bits and Rx FIFO Full bit in the UFSTAT register instead of this
bit.
0