Preliminary
SYSTEM CONTROLLER
S3C2451X RISC MICROPROCESSOR
2-8
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
PLL (PHASE-LOCKED-LOOP)
The PLL (Phase-Locked Loop) frequency synthesizer is constructed in CMOS on single monolithic structure. The
PLL provides frequency multiplication capabilities.
MPLL generates the clock sources for ARMCLK, HCLK, PCLK, DDRCLK and SSMCCLK and EPLL generates
clock sources for USBHOSTCLK, CAMCLK and so forth.
The following sections describe the operation of the PLL, that includes the phase difference detector, charge
pump, VCO (Voltage controlled oscillator), and loop filter.
Refer to MPLLCON and EPLLCON registers to change PLL output frequency.
Fout
Off-chip loop filter
Fin
Pre-Divider
Main
Divider
PFD
Charge
Pump
VCO
Post
Scaler
Figure 2-5. PLL(Phase-Locked Loop) Block Diagram
CHANGE PLL SETTINGS IN NORMAL OPERATION
During the operation of S3C2451X in NORMAL mode, if the user wants to change the frequency by writing the
PMS value, the PLL lock time is automatically inserted. During the lock time, the clock is not supplied to the
internal blocks in S3C2451X. The timing diagram is as follow.
MPLL_clk
PMS setting
PLL Locktime
SYSCLK
It changes to new PLL clock
after lock time automatically
It changes to LOW value during
lock time automatically
Figure 2-6. The case that changes slow clock by setting PMS value
