Preliminary
HSMMC CONTROLLER
S3C2451X RISC MICROPROCESSOR
21-8
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
TIMEOUT SETTING FOR DAT LINE
Calculate a Divisor for detecting Timeout
(1)
START
Set Timeout Detection Timer
(2)
END
Figure 21-8 Timeout Setting Sequence
In order to detect timeout errors on DAT line, the Host Driver shall execute the following two steps before any SD
transaction.
(1) Calculate a divisor to detect timeout errors by reading Timeout Clock Frequency and Timeout Clock Unit in the
Capabilities register. If Timeout Clock Frequency is 00 0000b, the Host System shall provide this information to
the Host Driver by another method.
(2) Set Data Timeout Counter Value(TIMEOUTCON) in the Timeout Control register in accordance with the value
from step (1) above.
SD TRANSACTION GENERATION
This section describes the sequences how to generate and control various kinds of SD transactions. SD
transactions are classified into three cases:
(1) Transactions that do not use the DAT line.
(2) Transactions that use the DAT line only for the busy signal.
(3) Transactions that use the DAT line for transferring data.
In this specification the first and the second case’s transactions are classified as “Transaction Control without
Data Transfer using DAT Line,” the third case’s transaction is classified as “Transaction Control with Data
Transfer using DAT Line.”
Please refer to the specifications below for the detailed specifications on the SD Command itself:
• SD Memory Card Specification Part 1
PHYSICAL LAYER SPECIFICATION Version 1.01
• SD Card Specification PART E1
Secure Digital Input/Output (SDIO) Specification Version 1.00
