Preliminary
USB2.0 DEVICE
S3C2451X RISC MICROPROCESSOR
17-20
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
ESR Bit
R/W
Description
Initial
State
FFS [6]
R/C
FIFO
Flushed.
FFS informs that FIFO is flushed.
This bit is an interrupt source.
This bit is cleared when the MCU clears FLUSH bit in
Endpoint Control Register.
0
FSC
[5]
R/C
Function Stall Condition.
FSC informs that STALL handshake due to functional stall
condition is sent to Host.
This bit is set when endpoint stall set bit is set by the MCU.
This bit is cleared when the MCU writes 1 on it.
0
LWO
[4]
R
Last Word Odd.
LWO informs that the lower byte of last word is only valid.
This bit is automatically cleared after the MCU reads packet
data received Host.
0
PSIF
[3:2]
R
Packet Status In FIFO.
00 = No packet in FIFO
01 = One packet in FIFO
10 = Two packet in FIFO
11 = Invalid value
0
TPS
[1]
R/C
Tx Packet Success
TPS is used for Single or Dual transfer mode.
TPS is activated when one packet data in FIFO was
successfully transferred to Host and received ACK from
Host. This bit should be cleared by writing 1 on it after being
read by the MCU.
0
RPS
[0]
R
Rx Packet Success.
RPS is used for Single or Dual transfer mode.
RPS is activated when the FIFO has a packet data to
receive. RPS is automatically cleared when MCU reads all
packets (one or two) from FIFO. MCU can identify the
packet size through BYTE READ COUNT REGISTER
(BRCR).
0
