Preliminary
S3C2451X RISC MICROPROCESSOR
MOBILE DRAM CONTROLLER
6-
7
Supported programmable timing parameters
Figure 6-3 DRAM Timing diagram
Figure 6-3 shows a timing diagram of DRAM. There are many timing parameters provided by DRAM. And
DRAMC only provides some timing parameters to support various DRAM memories, like SDR, mobile DDR and
DDR2.
tARFC and tRP are programmable, so you can also control the tRAS period by using these parameters. And the
delay from RAS to CAS is determined by tRCD. And CL(CAS Latency) is also programmable. The timing diagram
of CL (CAS Latency) is like figure 6-4.
Figure 6-4 CL (CAS Latency) timing diagram
DRAMC also needs tARFC timing parameter to control of the timing for auto-refresh to CMD and self-refresh to
CMD period. The figure 6-5 shows the tARFC timing diagram.
