Samsung S3C2451X, User Manual, Page: 55 / 756

Preliminary
S3C2451X RISC MICROPROCESSOR PRODUCT OVERVIEW
1-51
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Register Name Address Reset Value
Acc.
Unit
Read/
Write
Function
EP0CR 0x4980_0028 0x0 R/W EP0 Control Register
SCR2 0x4980_005C 0x1F W System Control Register2
EP0BR 0x4980_0060 0x0 R/W EP0 Buffer Register
EP1BR 0x4980_0064 0x0 R/W EP1 Buffer Register
EP2BR 0x4980_0068 0x0 R/W EP2 Buffer Register
EP3BR 0x4980_006C 0x0 R/W EP3 Buffer Register
EP4BR 0x4980_0070 0x0 R/W EP4 Buffer Register
EP5BR 0x4980_0074 0x0 R/W EP5 Buffer Register
EP6BR 0x4980_0078 0x0 R/W EP6 Buffer Register
EP7BR 0x4980_007C 0x0 R/W EP7 Buffer Register
EP8BR 0x4980_0080 0x0 R/W EP8 Buffer Register
FCON 0x4980_0100 0x0 R/W Burst FIFO-DMA Control
FSTAT 0x4980_0104 0x0 R Burst FIFO status
ESR 0x4980_002C 0x0 R/W Endpoints Status Register
ECR 0x4980_0030 0x0 R/W Endpoints Control Register
BRCR 0x4980_0034 0x0 R Byte Read Count Register
BWCR 0x4980_0038 0x0 R/W Byte Write Count Register
MPR 0x4980_003C 0x0 R/W Max Packet Register
DCR 0x4980_0040 0x0 R/W DMA Control Register
DTCR 0x4980_0044 0x0 R/W DMA Transfer Counter Register
DFCR 0x4980_0048 0x0 R/W DMA FIFO Counter Register
DTTCR1 0x4980_004C
0x0 R/W DMA Total Transfer Counter1
Register
DTTCR2 0x4980_0050
0x0 R/W DMA Total Transfer Counter2
Register
ESR2 0x4980_0058 0x0 R Endpoint Status Register2
MICR 0x4980_0084 0x0 R/W Master Interface Control Register
MBAR 0x4980_0088 0x0 R/W Memory Base Address Register
MCAR 0x4980_008C 0x0 R Memory Current Address Register
Watchdog Timer
WTCON 0x53000000 0x0000_8021 W R/W Watchdog timer mode
WTDAT 0x53000004 0x0000_8000 Watchdog timer data
WTCNT 0x53000008 0x0000_8000 Watchdog timer count
IIC
IICCON0 0x54000000 W R/W IIC0 control
IICSTAT0 0x54000004 IIC0 status
IICADD0 0x54000008 IIC0 address