Preliminary
S3C2451 RISC MICROPROCESSOR AC97 CONTROLLER
27-7
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
AC-LINK INPUT FRAME (SDATA_IN)
Slot 0: Tag Phase
In slot 0, the first bit is a bit (SDATA_OUT, bit 15) that indicates whether the AC97 controller is in the CODEC
ready state. If the CODEC Ready bit is a 0, the AC97 controller is not ready for normal operation. This condition is
normal after the power is de-asserted on reset and the AC97 controller voltage references are settling.
Slot 1: Status Address Port/SLOTREQ bits
The status port monitors the status for the AC97 controller functions including, but not limited to, mixer settings
and power management. Audio input frame slot 1s stream echoes the control register index for the data to be
returned in slot 2, if the controller tags slots 1 and 2 as valid during slot 0. The controller only accepts status data
if the accompanying status address matches the last valid command address issued during the most recent read
command. For multiple sample rate output, the CODEC examines its sample-rate control registers, its FIFOs’
states, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to determine which
SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current audio input frame indicate which
output slots require data from the controller in the next audio output frame. For fixed 48 kHz operation, the
SLOTREQ bits are set active (low), and a sample is transferred each frame. For multiple sample-rate input, the
“tag” bit for each input slot indicates whether valid data is present.
Bit Description
19
RESERVED (Filled with zero)
18-12
Control register index (Filled with zeroes if AC97 tags is invalid)
11
Slot 3 request : PCM Left channel
10
Slot 4 request : PCM Right channel
9
Slot 5 request : NA
8
Slot 6 request : MIC channel
7
Slot 7 request : NA
6
Slot 8 request : NA
5
Slot 9 request : NA
4
Slot 10 request : NA
3
Slot 11 request : NA
2
Slot 12 request : NA
1, 0
RESERVED (Filled with zero)
Table 27-1. Input Slot 1 Bit Definitions
Slot 2: Status Data Port
In slot 2, this is the status data with 16-bit resolution.([19:4] is valid data)
