Preliminary
SYSTEM CONTROLLER
S3C2451X RISC MICROPROCESSOR
2-12
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Figure 2-9 shows EPLL and special clocks for various peripherals
Figure 2-9. EPLL Based clock domain
ESYSCLK CONTROL
Clocks of the EPLL can be used for various peripherals. Each divider value is configured in CLKDIV1 register and
all clocks are enabled or disabled by accessing SCLKCON register. According to USB host interface, If you want
to get the clock with exact 50% duty cycle, then make EPLL generate 96MHz and divide the clock.
EPLL will be turned off during STOP and SLEEP mode automatically. Also, EPLL will be generated clock to
ESYSCLK, after exiting STOP and SLEEP mode if corresponding bits are enabled in SCLKCON register.
Table 2-6. ESYSCLK Control
Condition
ESYSCLK state
EPLL state
After reset
EPLL reference clock
off
After configuring EPLL
During PLL lock time: LOW
After PLL lock time: EPLL output
on
