Preliminary
S3C2451X RISC MICROPROCESSOR
HSMMC CONTROLLER
21-31
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
RDTR
ANAC
T
[9]
Read Transfer Active
(ROC)
This status is used for detecting completion of a read transfer.
This bit is set to 1 for either of the following conditions:
(1) After the end bit of the read command.
(2) When writing a 1 to
Continue Request
in the
Block Gap Control
register to
restart a read transfer.
This bit is cleared to 0 for either of the following conditions::
(1) When the last data block as specified by block length is transferred to the
System.
(2) When all valid data blocks have been transferred to the System and no current
block transfers are being sent as a result of the
Stop At Block Gap Request
being
set to 1.
A Transfer Complete
interrupt is generated when this bit changes to 0.
1 = Transferring data
0 = No valid data
0
WTTR
ANAC
T
[8]
Write Transfer Active
(ROC)
This status indicates a write transfer is active. If this bit is 0, it means no valid write
data exists in the Host Controller.
This bit is set in either of the following cases:
(1) After the end bit of the write command.
(2) When writing a 1 to
Continue Request
in the
Block Gap Control
register to
restart a write transfer.
This bit is cleared in either of the following cases:
(1) After getting the CRC status of the last data block as specified by the transfer
count (Single and Multiple)
(2) After getting the CRC status of any block where data transmission is about to be
stopped by a
Stop At Block Gap Request
.
During a write transaction, a
Block Gap Event
interrupt is generated when this bit
is changed to 0, as result of the
Stop At Block Gap Request
being set. This status
is useful for the Host Driver in determining when to issue commands during write
busy.
1 = Transferring data
0 = No valid data
0
[7:3]
Reserved
0
DATLI
NEAC
T
[2]
DAT Line Active
(ROC)
This bit indicates whether one of the
DAT
line on SD Bus is in use.
(a) In the case of read transactions
This status indicates if a read transfer is executing on the SD Bus. Changes in this
value from 1 to 0 between data blocks generate a
Block Gap Event
interrupt in the
Normal Interrupt Status
register.
This bit shall be set in either of the following cases:
(1) After the end bit of the read command.
(2) When writing a 1 to
Continue Request
in the
Block Gap Control
register to
restart a read transfer.
This bit shall be cleared in either of the following cases:
0