
Preliminary
S3C2451X RISC MICROPROCESSOR
PRODUCT OVERVIEW
1-55
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Register Name
Address
Reset Value
Acc.
Unit
Read/
Write
Function
CH_CFG
0x52000000
0x40
R/W
SPI configuration register
Clk_CFG 0x52000004 0x0
R/W
Clock
configuration register
MODE_CFG
0x52000008
0x0
R/W
SPI FIFO control register
Slave_slection_reg 0x5200000C
0x1
R/W
Slave selection signal
SPI_INT_EN
0x52000010
0x0
R/W
SPI Interrupt Enable register
SPI_STATUS 0x52000014
0x0
R
SPI status register
SPI_TX_DATA 0x52000018
0x0
W
SPI TX DATA register
SPI_RX_DATA
0x5200001C
0x0
R
SPI RX DATA register
Packet_Count_reg 0x52000020
0x0
R/W Count how many data master gets
Pending_clr_reg
0x52000024 0x0
R/W Pending
clear
register
SWAP_CFG
0x52000028
0x0
R/W
SWAP config register
FB_Clk_sel
0x5200002C 0x3
R/W
Feedback
clock selecting register.
HSSPI(SPI Channel 1)
CH_CFG
0x59000000
0x40
R/W
SPI configuration register
Clk_CFG 0x59000004 0x0
R/W
Clock
configuration register
MODE_CFG
0x59000008
0x0
R/W
SPI FIFO control register
Slave_slection_reg 0x5900000C
0x1
R/W
Slave selection signal
SPI_INT_EN
0x59000010
0x0
R/W
SPI Interrupt Enable register
SPI_STATUS 0x59000014
0x0
R
SPI status register
SPI_TX_DATA 0x59000018
0x0
W
SPI TX DATA register
SPI_RX_DATA
0x5900001C
0x0
R
SPI RX DATA register
Packet_Count_reg 0x59000020
0x0
R/W Count how many data master gets
Pending_clr_reg
0x59000024 0x0
R/W Pending
clear
register
SWAP_CFG
0x59000028
0x0
R/W
SWAP config register
FB_Clk_sel
0x5900002C 0x3
R/W
Feedback
clock selecting register.
Register
Name
Address Reset
Value
Acc.
Unit
Read/
Write
Function
HSMMC Channel 0
SYSAD
0x4AC00000
0x00000000
W
R/W
SDI control register
BLKSIZE
0x4AC00004
0x00000000
HW
R/W
Host DMA Buffer Boundary and
Transfer Block Size Register
BLKCNT 0x4AC00006
0x00000000
HW
R/W
Blocks Count For Current Transfer
ARGUMENT
0x4AC00008 0x00000000 HW
R/W Command Argument Register
TRNMOD 0x4AC0000C
0x00000000
HW
R/W
Transfer Mode Setting Register
CMDREG
0x4AC0000E 0x00000000 HW
R/W Command
Register
RSPREG0
0x4AC00010
0x00000000
W
ROC
Response Register 0
RSPREG1
0x4AC00014
0x00000000
W
ROC
Response Register 1