Preliminary
ELECTRICAL DATA
S3C2451X RISC MICROPROCESSOR
29-24
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Table 29-15. Memory Interface Timing Constants (SDRAM)
(VDDi= 1.3V
±
0.05V (400MHz), VDDi= TBD V
±
0.05V (533MHz), TA = -40 to 85
°
C, VDD_SDRAM = 1.8V
±
0.1V,
133MHz, CL = 25pF)
Parameter Symbol
Min
Max
Unit
SDRAM Address Delay
t
SAD
1.58 5.61 ns
SDRAM Chip Select Delay
t
SCSD
1.98 5.27 ns
SDRAM Row active Delay
t
SRD
1.88 4.67 ns
SDRAM Column active Delay
t
SCD
1.63 3.96 ns
SDRAM Byte Enable Delay
t
SBED
1.80 4.58 ns
SDRAM Write enable Delay
t
SWD
2.13 5.51 ns
SDRAM read Data Setup time
t
SDS
1.50 - ns
SDRAM read Data Hold time
t
SDH
1.50 - ns
SDRAM output Data Delay
t
SDD
1.59 5.65 ns
SDRAM Clock Enable Delay
t
CKED
1.62 4.11 ns
NOTE:
If CL increase over the 25pF, operation conditions follow the guide table
Load Capacitance (CL)
Bus clock
Voltage
< 25 pF
133MHz
25 pF < CL < 50 pF
100MHz
50 pF < CL < 70 pF
90MHz
1.8V
±
0.1V