Samsung S3C2451X, User Manual, Page: 100 / 756

Preliminary
SYSTEM CONTROLLER S3C2451X RISC MICROPROCESSOR
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Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SYSTEM CONTROLLER STATUS REGISTERS (WKUPSTAT AND RSTSTAT)
Software must know the status of the system controller after wakeup or reset. WKUPSTAT and RSTSTAT
registers store the information.
Register Address R/W Description Reset Value
RSTSTAT 0x4C00_0068 R Reset status register 0x0000_0001
WKUPSTAT 0x4C00_006C R/W Wake-up status register 0x0000_0000
After S3C2451X is re-set or woken-up, the following two registers store the source of the activation. The value of
RSTSTAT register is cleared by the other reset. If each bit has ‘1’ value, resets or wakeup events are occurred.
The reset priority is as follows: nRESET > WDTRST > SLEEP > DEEP-STOP > SW Reset
RSTSTAT Bit Description Initial Value
RESERVED [31:6] - 0x0000_000
SWRST [5] Reset by software (see SWRST register) 0
DEEP-STOP [4] Wakeup from DEEP-STOP (ARM Reset only) 0
SLEEP [3]
Wakeup from RTC_TICK, RTC_ALARM, EINT and battery fault
from power-down mode.
(Reset by waking-up from SLEEP mode)
0
WDTRST [2] Reset by Watch-dog reset 0
RESERVED [1] - 0
EXTRST [0] External reset by nRESET pin 1
WKUPSTAT register indicates that which source was used for changing system state into normal mode from idle,
stop and sleep mode. The value of WKUPSTAT register can be cleared by writing ‘1’.
WKUPSTAT Bit Description Initial Value
RESERVED [31:6] - 0x0000_000
BATF [5]
Waked-up by BATT_FLT assertion. This field is valid when
PWRCFG[1:0] = 2’b01
0
RTC_TICK [4] Waked-up by RTC tick 0
RESERVED [3:2] - 0x0
RTC [1] Waked-up by RTC alarm 0
EINT [0] Waked-up by external interrupts 0