![background image](http://html1.mh-extra.com/html/omron/cj1g-cpu-series/cj1g-cpu-series_programming-manual_742489082.webp)
61
Precautions
Section 2-2
Instructions Not Available
in Step Ladder Program
Sections
Note
1.
A step ladder program section can be used in an interlock section (be-
tween IL and ILC). The step ladder section will be completely reset when
the interlock is ON.
2.
A step ladder program section can be used between MULTIPLE JUMP
(JMP0) and MULTIPLE JUMP END (JME0).
Function
Mnemonic
Instruction
Sequence Control
FOR(512), NEXT(513), and
BREAK(514)
FOR, NEXT, and BREAK
LOOP
END(001)
END
IL(002) and ILC(003)
INTERLOCK and INTER-
LOCK CLEAR
JMP(004) and JME(005)
JUMP and JUMP END
CJP(510) and CJPN(511)
CONDITIONAL JUMP and
CONDITIONAL JUMP NOT
JMP0(515) and JME0(516)
MULTIPLE JUMP and MULTI-
PLE JUMP END
Subroutines
SBN(092) and RET(093)
SUBROUTINE ENTRY and
SUBROUTINE RETURN
Block Programs
IF(802) (NOT), ELSE(803),
and IEND(804)
Branching instructions
BPRG(096) and BEND(801)
BLOCK PROGRAM BEGIN/
END
EXIT(806) (NOT)
CONDITIONAL BLOCK EXIT
(NOT)
LOOP(809) and LEND(810)
(NOT)
Loop control
WAIT(805) (NOT)
ONE CYCLE WAIT (NOT)
TIMW(813)
TIMER WAIT
TMHW(815)
HIGH-SPEED TIMER WAIT
CNTW(814)
COUNTER WAIT
BPPS(811) and BPRS(812)
BLOCK PROGRAM PAUSE
and RESTART
Summary of Contents for CJ1G-CPU series
Page 3: ...iv...
Page 5: ...vi...
Page 21: ...xxii Conformance to EC Directives 6...
Page 169: ...148 Task Control Instructions Section 3 32...
Page 203: ...182 Programming Device Operations for Tasks Section 4 4...
Page 253: ...232 Using File Memory Section 5 3...
Page 337: ...316 Other Functions Section 6 11...
Page 347: ......
Page 369: ......
Page 373: ......
Page 379: ......
Page 381: ...360 Revision History...