![background image](http://html1.mh-extra.com/html/omron/cj1g-cpu-series/cj1g-cpu-series_programming-manual_742489264.webp)
243
Cycle Time/High-speed Processing
Section 6-1
Using DLNK(226)
The following diagram illustrates the data flow that will produce the maximum
data link I/O response time when DLNK(226) is used.
There are three points shown in the diagram above where processing is
delayed, increasing the data link I/O response time.
Note In this example, it is assumed that DNLK(226) is placed after other instruc-
tions in the program in both CPU Units
1,2,3...
1.
The input arrives in the PLC (CPU Unit #1) just after I/O refreshing, caus-
ing a delay of one cycle before the input is read into the PLC. CPU Bus
Units are refreshed during program execution, reducing the total delay to
approximately 1.5 cycle times.
2.
Data exchange occurs just after the PLC passes the token that makes it
the polling node, causing a delay of up to one communications cycle time
before the data is transferred in data link processing. There will also be a
delay of up to one communications cycle time after receiving the token,
causing a total delay of up to two communications cycle times.
3.
The data transferred in data link processing arrives at the PLC (CPU Unit
#2) after the I/O refresh, but DLNK(226) refreshes the data, so the data will
be read into the PLC without causing a delay of up to one cycle. The Basic
I/O Units are refreshed after program execution, causing a total delay of
approximately one cycle time.
Output ON delay
15 ms
Total (data link I/O response time)
126.5 ms
×
×
×
▼
DLNK
▼
DLNK
▼
DLNK
▼
DLNK
▼
DLNK
▼
DLNK
▼
Input Unit
Input
Input ON delay
(1) Delay of 1.5 cycle times
Basic I/O Units refreshed.
CPU Bus Units refreshed
(including data links)
One cycle time
Data transfer to
Controller Link Unit
Processing in
CPU Unit #1
(2) Delay of two communications cycle times
One com-
munica-
tions cycle
Data link transmissions
(3) Delay of approx one cycle time
Data received from Controller Link Unit
Output Unit
Output ON delay
Processing in
CPU Unit #2
Maximum data link I/O response time
DLNK(226) execution
One cycle time max
Program
execution
Program
execution
Summary of Contents for CJ1G-CPU series
Page 3: ...iv...
Page 5: ...vi...
Page 21: ...xxii Conformance to EC Directives 6...
Page 169: ...148 Task Control Instructions Section 3 32...
Page 203: ...182 Programming Device Operations for Tasks Section 4 4...
Page 253: ...232 Using File Memory Section 5 3...
Page 337: ...316 Other Functions Section 6 11...
Page 347: ......
Page 369: ......
Page 373: ......
Page 379: ......
Page 381: ...360 Revision History...