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175
Interrupt Tasks
Section 4-3
number), the Board will request execution of an external interrupt task in the
CPU Unit after it receives data from its serial port and writes that data into the
CPU Unit’s I/O memory.
Note
1.
When the response notification method is set for interrupt notification (fixed
number), the Board requests execution of the interrupt task with the preset
task number.
2.
When the response notification method is set for interrupt notification (re-
ception case number), the external interrupt task number is calculated with
the specified formula and the Board requests execution of the interrupt
task with that task number.
3.
If an external interrupt task (0 to 255) has the same number as a power
OFF task (task 1), scheduled interrupt task (task 2 or 3), or I/O interrupt
task (100 to 131), the interrupt task will be executed for either interrupt con-
dition (external interrupt or the other interrupt condition). As a rule, task
numbers should not be duplicated.
4-3-2
Interrupt Task Priority
Execution of another interrupt task will be ended to allow the power OFF inter-
rupt task to execute. The CPU will reset but the terminated interrupt task will
not be executed following execution of the power OFF interrupt task.
CPU Unit
Serial Communications Board
Data
Cyclic task
Interrupt task
I/O memory
Specifies exter-
nal interrupt task
number and re-
quests interrupt
processing.
Summary of Contents for CJ1G-CPU series
Page 3: ...iv...
Page 5: ...vi...
Page 21: ...xxii Conformance to EC Directives 6...
Page 169: ...148 Task Control Instructions Section 3 32...
Page 203: ...182 Programming Device Operations for Tasks Section 4 4...
Page 253: ...232 Using File Memory Section 5 3...
Page 337: ...316 Other Functions Section 6 11...
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Page 381: ...360 Revision History...