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CHAPTER 14 SERIAL INTERFACE UART0

Preliminary User’s Manual U17260EJ3V1UD

341

(e) Reception

error

Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error

flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data

reception, a reception error interrupt (INTSR0) is generated.

Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception

error interrupt (INTSR0) servicing (see

Figure 14-3

The contents of ASIS0 are cleared to 0 when ASIS0 is read.

Table 14-3. Cause of Reception Error

Reception Error

Cause

Parity error

The parity specified for transmission does not match the parity of the receive data.

Framing error

Stop bit is not detected.

Overrun error

Reception of the next data is completed before data is read from receive buffer

(f) Noise filter of receive data

The R

D0 signal is sampled using the base clock output by the prescaler block.

If two sampled values are the same, the output of the match detector changes, and the data is sampled as

input data.

Because the circuit is configured as shown in Figure 14-10, the internal processing of the reception operation

is delayed by two clocks from the external signal status.

Figure 14-10. Noise Filter Circuit

Internal signal B

Internal signal A

Match detector

Base clock

D0/SI10/P11

LD_EN

Summary of Contents for 78K/0 Series

Page 1: ...F0537 µPD78F0537D 78K0 KE2 8 Bit Single Chip Microcontrollers Preliminary User s Manual The µPD78F0537D has an on chip debug function Do not use this product for mass production because its reliability cannot be guaranteed after the on chip debug function has been used due to issues with respect to the number of times the flash memory can be rewritten NEC Electronics ...

Page 2: ...Preliminary User s Manual U17260EJ3V1UD 2 MEMO ...

Page 3: ... tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turne...

Page 4: ...C Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to pro...

Page 5: ...oul Branch Seoul Korea Tel 02 558 3737 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 5888 5400 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 J05 6 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65030 Sucursal en España Madrid Spain Tel 091 504 27 87 Vélizy Villacoublay France Tel 01 30 67 58 00 ...

Page 6: ...rnal block functions Interrupts Other on chip peripheral functions Electrical specifications target CPU functions Instruction set Explanation of each instruction How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To gain a general understanding of functions Read this manual in the order of the C...

Page 7: ...Preliminary User s Manual U17260EJ3V1UD 7 Conventions Data significance Higher digits on the left and lower digits on the right Active low representations overscore over pin and signal name Note ...

Page 8: ...r Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Note See the Semiconductor Device Mount Manual website http www necel com pkg en mount index html Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each docum...

Page 9: ...P60 to P63 port 6 39 2 2 8 P70 to P77 port 7 39 2 2 9 P120 to P124 port 12 40 2 2 10 P130 port 13 40 2 2 11 P140 P141 port 14 41 2 2 12 AVREF 41 2 2 13 AVSS 41 2 2 14 RESET 41 2 2 15 REGC 41 2 2 16 VDD and EVDD 42 2 2 17 VSS and EVSS 42 2 2 18 FLMD0 42 2 3 Pin I O Circuits and Recommended Connection of Unused Pins 43 CHAPTER 3 CPU ARCHITECTURE 47 3 1 Memory Space 47 3 1 1 Internal program memory s...

Page 10: ......

Page 11: ...rdware and source clocks 169 CHAPTER 7 16 BIT TIMER EVENT COUNTERS 00 AND 01 170 7 1 Functions of 16 Bit Timer Event Counters 00 and 01 170 7 2 Configuration of 16 Bit Timer Event Counters 00 and 01 171 7 3 Registers Controlling 16 Bit Timer Event Counters 00 and 01 176 7 4 Operation of 16 Bit Timer Event Counters 00 and 01 188 7 4 1 Interval timer operation 188 7 4 2 Square wave output operation ...

Page 12: ... Timer 292 CHAPTER 11 WATCHDOG TIMER 293 11 1 Functions of Watchdog Timer 293 11 2 Configuration of Watchdog Timer 294 11 3 Register Controlling Watchdog Timer 295 11 4 Operation of Watchdog Timer 296 11 4 1 Controlling operation of watchdog timer 296 11 4 2 Setting overflow time of watchdog timer 297 11 4 3 Setting window open period of watchdog timer 298 CHAPTER 12 CLOCK OUTPUT BUZZER OUTPUT CON...

Page 13: ... UART mode 364 15 4 3 Dedicated baud rate generator 377 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 384 16 1 Functions of Serial Interfaces CSI10 and CSI11 384 16 2 Configuration of Serial Interfaces CSI10 and CSI11 385 16 3 Registers Controlling Serial Interfaces CSI10 and CSI11 388 16 4 Operation of Serial Interfaces CSI10 and CSI11 393 16 4 1 Operation stop mode 393 16 4 2 3 wire serial I O mo...

Page 14: ...terrupt Function Types 486 19 2 Interrupt Sources and Configuration 486 19 3 Registers Controlling Interrupt Functions 491 19 4 Interrupt Servicing Operations 499 19 4 1 Maskable interrupt acknowledgement 499 19 4 2 Software interrupt request acknowledgement 501 19 4 3 Multiple interrupt servicing 502 19 4 4 Interrupt request hold 505 CHAPTER 20 KEY INTERRUPT FUNCTION 506 20 1 Functions of Key Int...

Page 15: ... 4 1 When used as reset 541 24 4 2 When used as interrupt 546 24 5 Cautions for Low Voltage Detector 551 CHAPTER 25 OPTION BYTE 554 25 1 Functions of Option Bytes 554 25 2 Format of Option Byte 555 CHAPTER 26 FLASH MEMORY 558 26 1 Internal Memory Size Switching Register 558 26 2 Internal Expansion RAM Size Switching Register 560 26 3 Writing with Flash Programmer 561 26 4 Programming Environment 5...

Page 16: ...tware Package 622 A 2 Language Processing Software 622 A 3 Control Software 623 A 4 Flash Memory Writing Tools 623 A 5 Debugging Tools Hardware 624 A 5 1 When using in circuit emulator QB 78K0KX2 624 A 5 2 When using on chip debug emulator QB 78K0MINI 625 A 6 Debugging Tools Software 625 APPENDIX B NOTES ON TARGET SYSTEM DESIGN 626 APPENDIX C REGISTER INDEX 628 C 1 Register Index In Alphabetical O...

Page 17: ...S and the internal expansion RAM size switching register IXS For IMS and IXS see 26 1 Memory Size Switching Register and 26 2 Internal Expansion RAM Size Switching Register On chip single power supply flash memory Self programming with boot swap function On chip debug function µPD78F0537D only Note On chip power on clear POC circuit and low voltage detector LVI On chip watchdog timer operable with...

Page 18: ...te2 1 channel I 2 C 1 channel Notes 1 Select either of the functions of these alternate function pins 2 µPD78F0534 78F0535 78F0536 78F0537 78F0537D only 10 bit resolution A D converter AVREF 2 3 to 5 5 V 8 channels Power supply voltage VDD 1 8 to 5 5 V Operating ambient temperature TA 40 to 85 C T S R products TA 40 to 125 C T2 product 1 2 Applications Automotive equipment A A1 A2 grade products u...

Page 19: ...EV A 64 pin plastic TQFP 7x7 µ PD78F0531FC T AA1 A 64 pin plastic FLGA 5x5 µ PD78F0531FC S AA1 A 64 pin plastic FLGA 5x5 µ PD78F0531FC R AA1 A 64 pin plastic FLGA 5x5 µ PD78F0532GB T UEU A 64 pin plastic LQFP 10x10 µ PD78F0532GB T2 UEU A 64 pin plastic LQFP 10x10 µ PD78F0532GB S UEU A 64 pin plastic LQFP 10x10 µ PD78F0532GB R UEU A 64 pin plastic LQFP 10x10 µ PD78F0532GC T UBS A 64 pin plastic LQF...

Page 20: ...lastic TQFP 7x7 µ PD78F0533FC T AA1 A 64 pin plastic FLGA 5x5 µ PD78F0533FC S AA1 A 64 pin plastic FLGA 5x5 µ PD78F0533FC R AA1 A 64 pin plastic FLGA 5x5 µ PD78F0534GB T UEU A 64 pin plastic LQFP 10x10 µ PD78F0534GB T2 UEU A 64 pin plastic LQFP 10x10 µ PD78F0534GB S UEU A 64 pin plastic LQFP 10x10 µ PD78F0534GB R UEU A 64 pin plastic LQFP 10x10 µ PD78F0534GC T UBS A 64 pin plastic LQFP 14x14 µ PD7...

Page 21: ...lastic TQFP 7x7 µ PD78F0535FC T AA1 A 64 pin plastic FLGA 5x5 µ PD78F0535FC S AA1 A 64 pin plastic FLGA 5x5 µ PD78F0535FC R AA1 A 64 pin plastic FLGA 5x5 µ PD78F0536GB T UEU A 64 pin plastic LQFP 10x10 µ PD78F0536GB T2 UEU A 64 pin plastic LQFP 10x10 µ PD78F0536GB S UEU A 64 pin plastic LQFP 10x10 µ PD78F0536GB R UEU A 64 pin plastic LQFP 10x10 µ PD78F0536GC T UBS A 64 pin plastic LQFP 14x14 µ PD7...

Page 22: ...ic TQFP 7x7 µ PD78F0537GA R 9EV A 64 pin plastic TQFP 7x7 µ PD78F0537FC T AA1 A 64 pin plastic FLGA 5x5 µ PD78F0537FC S AA1 A 64 pin plastic FLGA 5x5 µ PD78F0537FC R AA1 A 64 pin plastic FLGA 5x5 µ PD78F0537DGB T UEU A Note 64 pin plastic LQFP 10x10 µ PD78F0537DGC T UBS A Note 64 pin plastic LQFP 14x14 µ PD78F0537DGK T UET A Note 64 pin plastic LQFP 12x12 µ PD78F0537DGA T 9EV A Note 64 pin plastic...

Page 23: ... P70 KR0 P06 TO01 Note2 TI011 Note2 P05 SSI11 Note2 TI001 Note2 P32 INTP3 OCD1B Note1 AVSS AVREF P10 SCK10 TxD0 P11 SI10 RxD0 P12 SO10 P13 TxD6 P14 RxD6 P15 TOH0 P16 TOH1 INTP5 P17 TI50 TO50 P30 INTP1 P53 P52 P51 P50 P31 INTP2 OCD1ANote1 P120 INTP0 EXLVI P43 P42 P41 P40 RESET P124 XT2 EXCLKS P123 XT1 FLMD0 P122 X2 EXCLK OCD0BNote1 P121 X1 OCD0ANote1 REGC VSS EVSS VDD EVDD 64 63 62 61 60 59 58 57 5...

Page 24: ...CHAPTER 1 OUTLINE Preliminary User s Manual U17260EJ3V1UD 24 64 pin plastic FLGA 5 5 Top View Bottom View Index mark ...

Page 25: ... 1 P20 to P27 Port 2 P30 to P33 Port 3 P40 to P43 Port 4 P50 to P53 Port 5 P60 to P63 Port 6 P70 to P77 Port 7 P120 to P124 Port 12 P130 Port 13 P140 P141 Port 14 PCL Programmable clock output REGC Regulator capacitance RESET Reset RxD0 RxD6 Receive data SCK10 SCK11Note2 SCL0 Serial clock input output SDA0 Serial data input output SI10 SI11Note2 Serial data input SO10 SO11Note2 Serial data output ...

Page 26: ...PD78F0537 µPD78F0547 96 KB 5 KB µPD78F0526 µPD78F0536 µPD78F0546 µPD78F0515D Note 60 KB 3 KB µPD78F0515 µPD78F0525 µPD78F0535 µPD78F0545 48 KB 2 KB µPD78F0514 µPD78F0524 µPD78F0534 µPD78F0544 µPD78F0503D Note µPD78F0513D Note 32 KB 1 KB µPD78F0503 µPD78F0513 µPD78F0513 µPD78F0523 µPD78F0533 24 KB 1 KB µPD78F0502 µPD78F0512 µPD78F0522 µPD78F0532 16 KB 768 B µPD78F0501 µPD78F0511 µPD78F0521 µPD78F05...

Page 27: ... to 5 5 V Clock Internal low speed oscillation 240 kHz TYP VDD 1 8 to 5 5 V Total 23 37 41 Port N ch O D 6 V tolerance 2 4 4 16 bits TM0 1 ch 8 bits TM5 2 ch 8 bits TMH 2 ch Watch 1 ch Timer WDT 1 ch 3 wire CSI Automatic transmit receive 3 wire CSI UART 3 wire CSI Note 1 ch UART supporting LIN bus 1 ch Serial interface I 2 C bus 1 ch 10 bit A D 4 ch 8 ch External 6 7 8 Interrupt Internal 14 16 Key...

Page 28: ...nal low speed oscillation 240 kHz TYP VDD 1 8 to 5 5 V Total 45 55 71 Port N ch O D 6 V tolerance 4 4 4 16 bits TM0 1 ch 2 ch 8 bits TM5 2 ch 8 bits TMH 2 ch Watch 1 ch Timer WDT 1 ch 3 wire CSI 1 ch Automatic transmit receive 3 wire CSI 1 ch UART 3 wire CSI Note 1 ch UART supporting LIN bus 1 ch Serial interface I 2 C bus 1 ch 10 bit A D 8 ch External 8 9 Interrupt Internal 16 19 20 Key interrupt...

Page 29: ...1 P16 TI50 TO50 P17 8 bit TIMER EVENT COUNTER 50 RxD0 P11 TxD0 P10 SERIAL INTERFACE UART0 WATCHDOG TIMER RxD6 P14 TxD6 P13 SERIAL INTERFACE UART6 TI51 TO51 P33 8 bit TIMER EVENT COUNTER 51 WATCH TIMER SERIAL INTERFACE CSI10 SI10 P11 SO10 P12 SCK10 P10 16 bit TIMER EVENT COUNTER 00 TO00 TI010 P01 TI000 P00 LINSEL SERIAL INTERFACE CSI11Note2 SI11Note2 P03 SO11Note2 P02 SCK11Note2 P04 SSI11Note2 P05 ...

Page 30: ... Minimum instruction execution time 122 µs subsystem clock fSUB 32 768 kHz operation Instruction set 8 bit operation 16 bit operation Multiply divide 8 bits 8 bits 16 bits 8 bits Bit manipulate set reset test and Boolean operation BCD adjust etc I O ports Total 55 CMOS I O 50 CMOS output 1 N ch open drain I O 6 V tolerance 4 Timers 16 bit timer event counter 1 channel 8 bit timer event counter 2 c...

Page 31: ...lastic LQFP 10 10 64 pin plastic LQFP 14 14 64 pin plastic LQFP 12 12 64 pin plastic TQFP 7 7 64 pin plastic FLGA 5 5 Note Select either of the functions of these alternate function pins Caution The operating voltage range may be changed after evaluation of the device An outline of the timer is shown below 16 Bit Timer Event Counters 00 and 01 Note 1 8 Bit Timer Event Counters 50 and 51 8 Bit Time...

Page 32: ... output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input port TI011 Note1 TO01 Note1 P10 SCK10 TxD0 P11 SI10 RxD0 P12 SO10 P13 TxD6 P14 RxD6 P15 TOH0 P16 TOH1 INTP5 P17 I O Port 1 8 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input port TI50 TO50 P2...

Page 33: ...in output 6 V tolerance Input output can be specified in 1 bit units Input port P70 to P77 I O Port 7 8 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input port KR0 to KR7 P120 INTP0 EXLVI P121 X1 OCD0A Note P122 X2 EXCLK OCD0B Note P123 XT1 P124 I O Port 12 5 bit I O port Input output can be specified in 1 bit u...

Page 34: ...put port P05 TI001 RxD0 P11 SI10 RxD6 Input Serial data input to asynchronous serial interface Input port P14 TxD0 P10 SCK10 TxD6 Output Serial data output from asynchronous serial interface Input port P13 TI000 External count clock input to 16 bit timer event counter 00 Capture trigger input to capture registers CR000 CR010 of 16 bit timer event counter 00 P00 TI001 Note1 External count clock inp...

Page 35: ...on capacitance for internal operation Connect to VSS via a capacitor 0 47 µF target RESET Input System reset input EXLVI Input Potential input for external low voltage detection Input port P120 INTP0 X1 Input P121 OCD0A Note X2 Connecting resonator for main system clock Input port P122 EXCLK OCD0B Note EXCLK Input External clock input for main system clock Input port P122 X2 OCD0B Note XT1 Input I...

Page 36: ...p select input a TI000 TI001Note These are the pins for inputting an external count clock to 16 bit timer event counters 00 and 01 and are also for inputting a capture trigger signal to the capture registers CR000 CR010 or CR001 CR011 of 16 bit timer event counters 00 and 01 b TI010 TI011Note These are the pins for inputting a capture trigger signal to the capture register CR000 or CR001 of 16 bit...

Page 37: ... O and timer I O a SI10 This is a serial data input pin of serial interface CSI10 b SO10 This is a serial data output pin of serial interface CSI10 c SCK10 This is a serial clock I O pin of serial interface CSI10 d RxD0 This is a serial data input pin of serial interface UART0 e RxD6 This is a serial data input pin of serial interface UART6 f TxD0 This is a serial data output pin of serial interfa...

Page 38: ...n be specified in 1 bit units 1 Port mode P30 to P33 function as a 4 bit I O port P30 to P33 can be set to input or output port in 1 bit units using port mode register 3 PM3 Use of an on chip pull up resistor can be specified by pull up resistor option register 3 PU3 2 Control mode P30 to P33 function as external interrupt request input and timer I O a INTP1 to INTP4 These are the external interru...

Page 39: ...rt P60 to P63 can be set to input port or output port in 1 bit units using port mode register 6 PM6 Output of P60 to P63 is N ch open drain output 6 V tolerance 2 Control mode P60 to P63 function as serial interface data I O clock I O and external clock input a SDA0 This is a serial data I O pin for serial interface IIC0 b SCL0 This is a serial clock I O pin for serial interface IIC0 c EXSCL0 This...

Page 40: ...or main system clock and external clock input for subsystem clock a INTP0 This functions as an external interrupt request input INTP0 for which the valid edge rising edge falling edge or both rising and falling edges can be specified b EXLVI This is a potential input pin for external low voltage detection c X1 X2 These are the pins for connecting a resonator for main system clock d EXCLK This is a...

Page 41: ...ge falling edge or both rising and falling edges can be specified b PCL This is a clock output pin c BUZ This is a buzzer output pin 2 2 12 AVREF This is the A D converter reference voltage input pin and the positive power supply pin of P20 to P27 and A D converter When the A D converter is not used connect this pin directly to EVDD or VDD Note Note Make the AVREF pin the same potential as the VDD...

Page 42: ...other than P20 to P27 and P121 to P124 2 2 17 VSS and EVSS VSS is the ground potential pin for other than P121 to P124 and ports EVSS is the ground potential pin for ports other than P20 to P27 and P121 to P124 2 2 18 FLMD0 This is a pin for setting flash memory programming mode Connect FLMD0 to EVSS or VSS in the normal operation mode In flash memory programming mode connect this pin to the flash...

Page 43: ... P15 TOH0 5 AG P16 TOH1 INTP5 P17 TI50 TO50 5 AH Input Independently connect to EVDD or EVSS via a resistor Output Leave open P20 ANI0 to P27 ANI7 Note 2 11 G Analog setting Connect to AVREF or AVSS Digital setting Input Independently connect to EVDD or EVSS via a resistor Output Leave open P30 INTP1 P31 INTP2 P32 INTP3 P33 TI51 TO51 INTP4 5 AH P40 to P43 P50 to P53 5 AG Input Independently connec...

Page 44: ...eave open P130 3 C Output Leave open P140 PCL INTP6 P141 BUZ INTP7 5 AH I O Input Independently connect to EVDD or EVSS via a resistor Output Leave open RESET 2 Input FLMD0 38 Input Connect to EVSS or VSS AVREF Connect directly to EVDD or VDD Note 2 AVSS Connect directly to EVSS or VSS Notes 1 Use recommended connection above in I O port mode see Figure 6 2 Format of Clock Operation Mode Select Re...

Page 45: ...e Data Output disable Input enable EVDD P ch EVDD P ch IN OUT N ch EVSS Type 3 C Type 11 G EVDD P ch N ch Data OUT EVSS Data Output disable AVREF P ch IN OUT N ch P ch N ch Series resistor string voltage Comparator Input enable _ AVSS AVSS Type 5 AG Type 13 P Pull up enable Data Output disable Input enable EVDD P ch EVDD P ch IN OUT N ch EVSS Data Output disable Input enable IN OUT N ch EVSS ...

Page 46: ...igure 2 1 Pin I O Circuit List 2 2 Type 13 AD Type 38 Data Output disable Input enable IN OUT N ch EVSS Input enable IN Type 37 Data Output disable Input enable EVDD P ch X1 XT1 N ch EVSS RESET Data Output disable Input enable EVDD P ch N ch EVSS RESET P ch N ch X2 XT2 ...

Page 47: ...rnal expansion RAM areas do not overlap Table 3 1 Set Values of Internal Memory Size Switching Register IMS and Internal Expansion RAM Size Switching Register IXS Flash Memory Version 78K0 KE2 IMS IXS ROM Capacity Internal High Speed RAM Capacity Internal Expansion RAM Capacity µPD78F0531 04H 16 KB 768 bytes µPD78F0532 C6H 24 KB µPD78F0533 C8H 0CH 32 KB µPD78F0534 CCH 0AH 48 KB 1 KB µPD78F0535 CFH...

Page 48: ...048 x 8 bits Program area Program area Option byte areaNote1 5 x 8 bits Boot cluster 0Note2 Boot cluster 1 F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F C 0 0 H F B F F H 4 0 0 0 H 3 F F F H 0 0 0 0 H 0 0 4 0 H 0 0 3 F H 0 0 0 0 H 0 0 8 0 H 0 0 7 F H 0 8 0 0 H 0 7 F F H 1 0 0 0 H 0 F F F H 1 0 8 5 H 1 0 8 4 H 1 0 8 0 H 1 0 7 F H 0 0 8 5 H 0 0 8 4 H 3 F F F H 1 F F F H Notes 1 When boot swap ...

Page 49: ...048 x 8 bits Program area Program area Option byte areaNote1 5 x 8 bits Boot cluster 0Note2 Boot cluster 1 F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F B 0 0 H F A F F H 6 0 0 0 H 5 F F F H 0 0 0 0 H 0 0 4 0 H 0 0 3 F H 0 0 0 0 H 0 0 8 0 H 0 0 7 F H 0 8 0 0 H 0 7 F F H 1 0 0 0 H 0 F F F H 1 0 8 5 H 1 0 8 4 H 1 0 8 0 H 1 0 7 F H 0 0 8 5 H 0 0 8 4 H 5 F F F H 1 F F F H Notes 1 When boot swap ...

Page 50: ...048 x 8 bits Program area Program area Option byte areaNote1 5 x 8 bits Boot cluster 0Note2 Boot cluster 1 F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F B 0 0 H F A F F H 8 0 0 0 H 7 F F F H 0 0 0 0 H 0 0 4 0 H 0 0 3 F H 0 0 0 0 H 0 0 8 0 H 0 0 7 F H 0 8 0 0 H 0 7 F F H 1 0 0 0 H 0 F F F H 1 0 8 5 H 1 0 8 4 H 1 0 8 0 H 1 0 7 F H 0 0 8 5 H 0 0 8 4 H 7 F F F H 1 F F F H Notes 1 When boot swap ...

Page 51: ...8 bits CALLF entry area 2048 x 8 bits Program area Program area Option byte areaNote1 5 x 8 bits Boot cluster 0Note2 Boost cluster 1 Reserved F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F B 0 0 H F A F F H C 0 0 0 H B F F F H 0 0 0 0 H 0 0 4 0 H 0 0 3 F H 0 0 0 0 H 0 0 8 0 H 0 0 7 F H 0 8 0 0 H 0 7 F F H 1 0 0 0 H 0 F F F H 1 0 8 5 H 1 0 8 4 H 1 0 8 0 H 1 0 7 F H 0 0 8 5 H 0 0 8 4 H B F F F ...

Page 52: ... areaNote1 5 x 8 bits CALLF entry area 2048 x 8 bits Program area Program area Option byte areaNote1 5 x 8 bits Boot cluster 0Note2 Boot cluster 1 F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F B 0 0 H F A F F H F 0 0 0 H E F F F H 0 0 0 0 H 0 0 4 0 H 0 0 3 F H 0 0 0 0 H 0 0 8 0 H 0 0 7 F H 0 8 0 0 H 0 7 F F H 1 0 0 0 H 0 F F F H 1 0 8 5 H 1 0 8 4 H 1 0 8 0 H 1 0 7 F H 0 0 8 5 H 0 0 8 4 H E F...

Page 53: ...CHAPTER 3 CPU ARCHITECTURE Preliminary User s Manual U17260EJ3V1UD 53 Figure 3 6 Memory Map µPD78F0536 ...

Page 54: ...2 Boot cluster 1 Reserved F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F B 0 0 H F A F F H C 0 0 0 H B F F F H 0 0 4 0 H 0 0 3 F H 0 0 0 0 H 0 0 8 0 H 0 0 7 F H 0 8 0 0 H 0 7 F F H 1 0 0 0 H 0 F F F H 1 0 8 5 H 1 0 8 4 H 1 0 8 0 H 1 0 7 F H 0 0 8 5 H 0 0 8 4 H 7 F F F H 1 F F F H F 8 0 0 H F 7 F F H E 0 0 0 H D F F F H 8 0 0 0 H 7 F F F H Flash memory 16384 x 8 bits memory bank 0 Memory bank ...

Page 55: ... F H 1 0 8 5 H 1 0 8 4 H 1 0 8 0 H 1 0 7 F H 0 0 8 5 H 0 0 8 4 H 7 F F F H 1 F F F H F 8 0 0 H F 7 F F H E 0 0 0 H D F F F H 8 0 0 0 H 7 F F F H Flash memory 16384 x 8 bits memory bank 0 Memory bank 1 Memory bank 2 Memory bank 3 0 0 0 0 H Memory bank 5 Memory bank 4 Data memory space RAM spcae in which instruction can be fetched Program RAM area Program memory space Bank area Common area 1 0 8 F H...

Page 56: ...ts 0000H to 7FFFH µPD78F0534 49152 8 bits 0000H to BFFFH µPD78F0535 61440 8 bits 0000H to EFFFH µPD78F0536 98304 8 bits 0000H to 7FFFH common area 8000H to BFFFH bank area 4 µPD78F0537 78F0537D Flash memory 131072 8 bits 0000H to 7FFFH common area 8000H to BFFFH bank area 6 The internal program memory space is divided into the following areas 1 Vector table area The 64 byte area 0000H to 003FH is ...

Page 57: ... table area The 64 byte area 0040H to 007FH can store the subroutine entry address of a 1 byte call instruction CALLT 3 Option byte area A 5 byte area of 0080H to 0084H and 1080H to 1084H can be used as an option byte area Set the option byte at 0080H to 0084H when the boot swap is not used and at 0080H to 0084H and 1080H to 1084H when the boot swap is used For details see CHAPTER 25 OPTION BYTE 4...

Page 58: ... access between different memory banks via the common area 3 Allocate interrupt servicing in the common area 4 An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0 3 1 3 Internal data memory space 78K0 KE2 products incorporate the following RAMs 1 Internal high speed RAM Table 3 4 Internal High Speed RAM Capacity Part Number Internal High Speed RAM µPD78F0531 768 8...

Page 59: ...SFRs are allocated in the area FF00H to FFFFH see Table 3 6 Special Function Register List in 3 2 3 Special function registers SFRs Caution Do not access addresses to which SFRs are not assigned 3 1 5 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructi...

Page 60: ... addressing Based addressing Based indexed addressing Special function registers SFR 256 x 8 bits Internal high speed RAM 768 x 8 bits General purpose registers 32 x 8 bits Reserved Flash memory 16384 x 8 bits F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F C 0 0 H F B F F H 4 0 0 0 H 3 F F F H 0 0 0 0 H F F 2 0 H F F 1 F H F E 2 0 H F E 1 F H Register addressing Short direct addressing ...

Page 61: ... addressing Based addressing Based indexed addressing Special function registers SFR 256 x 8 bits Internal high speed RAM 1024 x 8 bits General purpose registers 32 x 8 bits Reserved Flash memory 24576 x 8 bits F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F B 0 0 H F A F F H 6 0 0 0 H 5 F F F H 0 0 0 0 H F F 2 0 H F F 1 F H F E 2 0 H F E 1 F H Register addressing Short direct addressing ...

Page 62: ... addressing Based addressing Based indexed addressing Special function registers SFR 256 x 8 bits Internal high speed RAM 1024 x 8 bits General purpose registers 32 x 8 bits Reserved Flash memory 32768 x 8 bits F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F B 0 0 H F A F F H 8 0 0 0 H 7 F F F H 0 0 0 0 H F F 2 0 H F F 1 F H F E 2 0 H F E 1 F H Register addressing Short direct addressing ...

Page 63: ...addressing Special function registers SFR 256 x 8 bits Internal high speed RAM 1024 x 8 bits General purpose registers 32 x 8 bits Reserved Flash memory 49152 x 8 bits F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F B 0 0 H F A F F H C 0 0 0 H B F F F H 0 0 0 0 H F F 2 0 H F F 1 F H F E 2 0 H F E 1 F H Register addressing Short direct addressing Reserved F 8 0 0 H F 7 F F H F 4 0 0 H F 3 F F H...

Page 64: ... Based indexed addressing Special function registers SFR 256 x 8 bits Internal high speed RAM 1024 x 8 bits General purpose registers 32 x 8 bits Reserved Flash memory 61440 x 8 bits F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F B 0 0 H F A F F H 0 0 0 0 H F F 2 0 H F F 1 F H F E 2 0 H F E 1 F H Register addressing Short direct addressing F 8 0 0 H F 7 F F H F 0 0 0 H E F F F H Internal expa...

Page 65: ...memory 32768 x 8 bits F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F B 0 0 H F A F F H C 0 0 0 H B F F F H 0 0 0 0 H F F 2 0 H F F 1 F H F E 2 0 H F E 1 F H Register addressing Short direct addressing Reserved F 8 0 0 H F 7 F F H E 8 0 0 H E 7 F F H Internal expansion RAM 4096 x 8 bits F A 0 0 H F 9 F F H 8 0 0 0 H 7 F F F H Flash memory 16384 x 8 bits memory bank 0 Note 16384 x 8 bits memory...

Page 66: ... E D F H F B 0 0 H F A F F H C 0 0 0 H B F F F H 0 0 0 0 H F F 2 0 H F F 1 F H F E 2 0 H F E 1 F H Register addressing Short direct addressing Reserved F 8 0 0 H F 7 F F H E 0 0 0 H D F F F H Internal expansion RAM 6144 x 8 bits F A 0 0 H F 9 F F H 8 0 0 0 H 7 F F F H Flash memory 16384 x 8 bits memory bank 0 Note 16384 x 8 bits memory bank 2 Note 16384 x 8 bits memory bank 3 Note 16384 x 8 bits m...

Page 67: ...PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0 2 Program status word PSW The program status word is an 8 bit register consisting of various flags set reset by instruction execution Program status word contents are stored in the stack area upon interrupt request generation or PUSH PSW instruction execution and are restored upon execution of the RETB RETI and POP PSW instructions Reset signal g...

Page 68: ...3 Priority specification flag registers PR0L PR0H PR1L PR1H can not be acknowledged Actual request acknowledgement is controlled by the interrupt enable flag IE f Carry flag CY This flag stores overflow and underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution 3...

Page 69: ... rp instruction when SP FEE0H Register pair lower FEE0H SP SP FEE0H FEDFH FEDEH Register pair higher FEDEH b CALL CALLF CALLT instructions when SP FEE0H PC15 to PC8 FEE0H SP SP FEE0H FEDFH FEDEH PC7 to PC0 FEDEH c Interrupt BRK instructions when SP FEE0H PC15 to PC8 PSW FEDFH FEE0H SP SP FEE0H FEDEH FEDDH PC7 to PC0 FEDDH ...

Page 70: ...emory a POP rp instruction when SP FEDEH Register pair lower FEE0H SP SP FEE0H FEDFH FEDEH Register pair higher FEDEH b RET instruction when SP FEDEH PC15 to PC8 FEE0H SP SP FEE0H FEDFH FEDEH PC7 to PC0 FEDEH c RETI RETB instructions when SP FEDDH PC15 to PC8 PSW FEDFH FEE0H SP SP FEE0H FEDEH FEDDH PC7 to PC0 FEDDH ...

Page 71: ...bsolute names R0 to R7 and RP0 to RP3 Register banks to be used for instruction execution are set by the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank Figure 3 21 Configuration of General Purpose Registers a Function name Register bank...

Page 72: ...on instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved by the assembler for the 16 bit manipulation instruction operand sfrp When specifying an address describe an even address Table 3 6 gives a list of the special function registers The meanings of items in the table are as follows Symbol Symbol indicating the address of...

Page 73: ...er counter 00 TM00 R 0000H FF12H FF13H 16 bit timer capture compare register 000 CR000 R W 0000H FF14H FF15H 16 bit timer capture compare register 010 CR010 R W 0000H FF16H 8 bit timer counter 50 TM50 R 00H FF17H 8 bit timer compare register 50 CR50 R W 00H FF18H 8 bit timer H compare register 00 CMP00 R W 00H FF19H 8 bit timer H compare register 10 CMP10 R W 00H FF1AH 8 bit timer H compare regist...

Page 74: ...Input switch control register ISC R W 00H FF50H Asynchronous serial interface operation mode register 6 ASIM6 R W 01H FF53H Asynchronous serial interface reception error status register 6 ASIS6 R 00H FF55H Asynchronous serial interface transmission status register 6 ASIF6 R 00H FF56H Clock selection register 6 CKSR6 R W 00H FF57H Baud rate generator control register 6 BRGC6 R W FFH FF58H Asynchron...

Page 75: ...ation time counter status register OSTC R 00H FFA4H Oscillation stabilization time select register OSTS R W 05H FFA5H IIC shift register 0 IIC0 R W 00H FFA6H IIC control register 0 IICC0 R W 00H FFA7H Slave address register 0 SVA0 R W 00H FFA8H IIC clock selection register 0 IICCL0 R W 00H FFA9H IIC function expansion register 0 IICX0 R W 00H FFAAH IIC status register 0 IICS0 R 00H FFABH IIC flag ...

Page 76: ... specification flag register 0L PR0 PR0L R W FFH FFE9H Priority specification flag register 0H PR0H R W FFH FFEAH Priority specification flag register 1L PR1 PR1L R W FFH FFEBH Priority specification flag register 1H PR1H R W FFH FFF0H Internal memory size switching register Note 2 IMS R W CFH FFF3H Memory bank select register BANK R W 00H FFF4H Internal expansion RAM size switching register Note ...

Page 77: ...al U12326E 3 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In other words relative addressing consists o...

Page 78: ...L addr16 and BR addr16 instructions can be branched to the entire memory space However before branching to a memory bank that is not set by the memory bank select register BANK change the setting of the memory bank by using BANK The CALLF addr11 instruction is branched to the 0800H to 0FFFH area Illustration In the case of CALL addr16 and BR addr16 instructions 15 0 PC 8 7 7 0 CALL or BR Low Addr ...

Page 79: ...from 40H to 7FH and allows branching to the entire memory space However before branching to a memory bank that is not set by the memory bank select register BANK change the setting of the memory bank by using BANK Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective address 1 Effective address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 1 1 1 7 6 5 1 0 ta4 0 Operation code 3 3 4 Registe...

Page 80: ...ction Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values that become decimal correction targets ROR4 ROL4 A register for storage of digit data that undergoes digit rotation Operand format Because implied addressing can be automati...

Page 81: ...ing operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described by absolute names R0 to R7 and RP0 to RP3 as well as function names X A C B E D L H AX BC DE and HL Description example MOV A C when selecting C register as r Ope...

Page 82: ... out for all of the memory spaces However before addressing a memory bank that is not set by the memory bank select register BANK change the setting of the memory bank by using BANK Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH I...

Page 83: ...a allowing SFRs to be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 See the Illustration shown below Operand format Identifier Description saddr Immediate data that indicate label or FE20H to FF1FH saddrp Immediate data that indicate label or FE20H to FF1FH even add...

Page 84: ... FF00H to FFCFH and FFE0H to FFFFH However the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PM0 A when selecting PM0 FF20H as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H sfr offse...

Page 85: ... This addressing can be carried out for all of the memory spaces However before addressing a memory bank that is not set by the memory bank select register BANK change the setting of the memory bank by using BANK Operand format Identifier Description DE HL Description example MOV A DE when selecting DE as register pair Operation code 1 0 0 0 0 1 0 1 Illustration 16 0 8 D 7 E 0 7 7 0 A DE The conte...

Page 86: ...expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all of the memory spaces However before addressing a memory bank that is not set by the memory bank select register BANK change the setting of the memory bank by using BANK Operand format Identifier Description HL byte Description example MOV A HL 10H when setting b...

Page 87: ... is performed by expanding the B or C register contents as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all of the memory spaces However before addressing a memory bank that is not set by the memory bank select register BANK change the setting of the memory bank by using BANK Operand format Identifier Description HL B HL C Description exa...

Page 88: ...thod is automatically employed when the PUSH POP subroutine call and return instructions are executed or the register is saved reset upon generation of an interrupt request With stack addressing only the internal high speed RAM area can be accessed Description example PUSH DE when saving DE register Operation code 1 0 1 1 0 1 0 1 Illustration E FEE0H SP SP FEE0H FEDFH FEDEH D Memory 0 7 FEDEH ...

Page 89: ...ory banks 0 to 5 as shown below The memory banks are selected by using a memory bank select register BANK Figure 4 1 Internal ROM Flash Memory Configuration a µPD78F0536 8 0 0 0 H 7 F F F H 0 0 0 0 H Flash memory 32768 8 bits B F F F H Flash memory 16384 8 bits memory bank 0 Memory bank 1 Memory bank 2 Common area Bank area Memory bank 3 b µPD78F0537 78F0537D 8 0 0 0 H 7 F F F H 0 0 0 0 H Flash me...

Page 90: ...K2 BANK1 BANK0 Bank setting BANK2 BANK1 BANK0 µPD78F0536 µPD78F0537 78F0537D 0 0 0 Common area 32 K memory bank 0 16 K 0 0 1 Common area 32 K memory bank 1 16 K 0 1 0 Common area 32 K memory bank 2 16 K 0 1 1 Common area 32 K memory bank 3 16 K 1 0 0 Common area 32 K memory bank 4 16 K 1 0 1 Setting prohibited Common area 32 K memory bank 5 16 K Other than above Setting prohibited Caution Be sure ...

Page 91: ...r in that area Cautions 1 Instructions cannot be fetched between different memory banks 2 Branching and accessing cannot be directly executed between different memory banks Execute branching or accessing between different memory banks via the common area 3 Allocate interrupt servicing in the common area 4 An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0 4 3 1 R...

Page 92: ...stination MOVW R_BNKA DATA1 Stores the address at the reference destination CALL BNKRD Calls a subroutine for referencing between memory banks BNKC CSEG AT 7000H BNKRD Subroutine for referencing between memory banks PUSH HL Saves the contents of register HL MOV A R_BNKN XCH A BANK Swaps the memory bank number at the reference source for that at the reference destination MOV R_BNKRN A Saves the mem...

Page 93: ...not branch directly from one memory bank to another To branch an instruction from one memory bank to another branch once to the common area 0000H to 7FFFH change the setting of the BANK register there and then execute the branch instruction again Memory bank m Common area Bank area Memory bank n Instruction branch Common area Bank area Instruction branch Memory bank m Memory bank n ...

Page 94: ... DS 1 Secures RAM for specifying a memory bank number at the branch destination MOV R_BNKN BANKNUM TEST Stores the memory bank number at the branch destination in RAM MOVW R_BNKA TEST Stores the address at the branch destination in RAM BR BNKBR Branches to inter memory bank branch processing BNKC CSEG AT 7000H BNKBR MOV A R_BNKN MOV BANK A Specifies the memory bank number at the branch destination...

Page 95: ...the calling destination by using the BANK register there execute the CALL instruction and branch to the call destination by that instruction At this time save the current value of the BANK register to RAM Restore the value of the BANK register before executing the RET instruction Memory bank m Common area Bank area Memory bank n BR instruction Common area Bank area CALL instruction Memory bank m M...

Page 96: ...n in RAM MOVW R_BNKA TEST Stores the address at the calling destination in RAM CALL BNKCAL Branches to an inter memory bank calling processing routine BNKC CSEG AT 7000H BNKCAL Inter memory bank calling processing routine MOV A R_BNKN Acquires the memory bank number at the calling destination XCH A BANK Changes the bank and acquires the memory bank number at the calling source MOV R_BNKRN A Saves ...

Page 97: ... response in the common area Memory bank m Common area Bank area Memory bank n Instruction branch Save the original memory bank number Specify the address and memory bank at the destination and execute the call instruction Vector table Software example when using interrupt request of 16 bit timer event counter 00 VCTBL CSEG AT 0020H DW BNKITM000 Specifies an address at the timer interrupt destinat...

Page 98: ...a routine that is used often in the common area If a value that is planned to be referenced is placed in RAM it can be referenced from all of the areas If the reference destination and the branch destination of the routine placed in a memory bank are placed in the same memory bank then the code size and processing are more efficient Allocate interrupt servicing that requires a quick response in th...

Page 99: ...7 and P121 to P124 VDD P121 to P124 Non port pins 78K0 KE2 products are provided with the ports shown in Figure 5 1 which enable variety of control operations The functions of each port are shown in Table 5 2 In addition to the function as digital I O ports these ports have several alternate functions For details of the alternate functions see CHAPTER 2 PIN FUNCTIONS Figure 5 1 Port Types Port 2 P...

Page 100: ...NI0 to ANI7 P30 INTP1 P31 INTP2 OCD1A Note2 P32 INTP3 OCD1B Note2 P33 I O Port 3 4 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input port INTP4 TI51 TO51 P40 to P43 I O Port 4 4 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting In...

Page 101: ...3 1 bit output only port Output port P140 PCL INTP6 P141 I O Port 14 2 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input port BUZ INTP7 Note µPD78F0537D only 5 2 Port Configuration Ports include the following hardware Table 5 3 Port Configuration Item Configuration Control registers Port mode register PM0 to PM...

Page 102: ...ock I O and chip select input Reset signal generation sets port 0 to input mode Figures 5 2 to 5 7 show block diagrams of port 0 Caution To use P02 SO11Note and P04 SCK11 Note as general purpose ports set serial operation mode register 11 CSIM11 and serial clock selection register 11 CSIC11 to the default status 00H Note Available only in the µPD78F0534 78F0535 78F0536 78F0537 and 78F0537D Figure ...

Page 103: ...3 Block Diagram of P01 P01 TI010 TO00 WRPU RD WRPORT WRPM PU01 PM01 EVDD P ch PU0 PM0 P0 Internal bus Alternate function Output latch P01 Selector Alternate function P0 Port register 0 PU0 Pull up resistor option register 0 PM0 Port mode register 0 RD Read signal WR Write signal ...

Page 104: ...11Note WRPU RD WRPORT WRPM PU02 PM02 EVDD P ch PU0 PM0 P0 Internal bus Alternate functionNote Output latch P02 Selector P0 Port register 0 PU0 Pull up resistor option register 0 PM0 Port mode register 0 RD Read signal WR Write signal Note Available only in the µPD78F0534 78F0535 78F0536 78F0537 and 78F0537D ...

Page 105: ...03 PM05 EVDD P ch PU0 PM0 P0 Internal bus Output latch P03 P05 Selector b µPD78F0534 78F0535 78F0536 78F0537 78F0537D P03 SI11 P05 SSI11 TI001 WRPU RD WRPORT WRPM PU03 PU05 PM03 PM05 EVDD P ch PU0 PM0 P0 Internal bus Alternate function Output latch P03 P05 Selector P0 Port register 0 PU0 Pull up resistor option register 0 PM0 Port mode register 0 RD Read signal WR Write signal ...

Page 106: ...CHAPTER 5 PORT FUNCTIONS Preliminary User s Manual U17260EJ3V1UD 106 Figure 5 6 Block Diagram of P04 a µPD78F0531 78F0532 78F0533 ...

Page 107: ...6 EVDD P ch PU0 PM0 P0 Internal bus Output latch P06 Selector b µPD78F0534 78F0535 78F0536 78F0537 78F0537D P06 TI011 TO01 WRPU RD WRPORT WRPM PU06 PM06 EVDD P ch PU0 PM0 P0 Internal bus Alternate function Output latch P06 Selector Alternate function P0 Port register 0 PU0 Pull up resistor option register 0 PM0 Port mode register 0 RD Read signal WR Write signal ...

Page 108: ... request input serial interface data I O clock I O and timer I O Reset signal generation sets port 1 to input mode Figures 5 8 to 5 12 show block diagrams of port 1 Caution To use P10 SCK10 TxD0 and P12 SO10 as general purpose ports set serial operation mode register 10 CSIM10 and serial clock selection register 10 CSIC10 to the default status 00H Figure 5 8 Block Diagram of P10 P10 SCK10 TxD0 WRP...

Page 109: ...ck Diagram of P11 and P14 P11 SI10 RxD0 P14 RxD6 WRPU RD WRPORT WRPM PU11 PU14 Alternate function Output latch P11 P14 PM11 PM14 EVDD P ch Selector Internal bus PU1 PM1 P1 P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 110: ...Block Diagram of P12 and P15 P12 SO10 P15 TOH0 WRPU RD WRPORT WRPM PU12 PU15 Output latch P12 P15 PM12 PM15 Alternate function EVDD P ch Selector Internal bus PU1 PM1 P1 P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 111: ...11 Figure 5 11 Block Diagram of P13 P13 TxD6 WRPU RD WRPORT WRPM PU13 Output latch P13 PM13 Alternate function EVDD P ch Internal bus Selector PU1 PM1 P1 P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 112: ...f P16 and P17 P16 TOH1 INTP5 P17 TI50 TO50 WRPU RD WRPORT WRPM PU16 PU17 Alternate function Output latch P16 P17 PM16 PM17 Alternate function EVDD P ch Selector Internal bus PU1 PM1 P1 P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 113: ...2 Table 5 4 Setting Functions of P20 ANI0 to P27 ANI7 Pins ADPC PM2 ADS P20 ANI0 to P27 ANI7 Pin Selects ANI Setting prohibited Input mode Does not select ANI Digital input Selects ANI Setting prohibited Digital I O selection Output mode Does not select ANI Digital output Selects ANI Analog input to be converted Input mode Does not select ANI Analog input not to be converted Selects ANI Analog inp...

Page 114: ...or option register 3 PU3 This port can also be used for external interrupt request input and timer I O Reset signal generation sets port 3 to input mode Figures 5 14 and 5 15 show block diagrams of port 3 Caution In the µPD78F0537D be sure to pull the P31 pin down before a reset release to prevent malfunction Remark The P31 and P32 pins of the µPD78F0537D can be used as on chip debug mode setting ...

Page 115: ...Block Diagram of P33 P33 INTP4 TI51 TO51 WRPU RD WRPORT WRPM PU33 Alternate function Output latch P33 PM33 Alternate function EVDD P ch Selector Internal bus PU3 PM3 P3 P3 Port register 3 PU3 Pull up resistor option register 3 PM3 Port mode register 3 RD Read signal WR Write signal ...

Page 116: ...use of an on chip pull up resistor can be specified in 1 bit units by pull up resistor option register 4 PU4 Reset signal generation sets port 4 to input mode Figure 5 16 shows a block diagram of port 4 Figure 5 16 Block Diagram of P40 to P43 RD P40 to P43 P ch WRPU WRPORT WRPM PU40 to PU43 PM40 to PM43 EVDD PU4 PM4 P4 Internal bus Output latch P40 to P43 Selector P4 Port register 4 PU4 Pull up re...

Page 117: ...output latch Port 5 can be set to the input mode or output mode in 1 bit units using port mode register 5 PM5 When the P50 to P53 pins are used as an input port use of an on chip pull up resistor can be specified in 1 bit units by pull up resistor option register 5 PU5 Reset signal generation sets port 5 to input mode ...

Page 118: ... for serial interface data I O clock I O and external clock input Reset signal generation sets port 6 to input mode Figures 5 18 to 5 20 show block diagrams of port 6 Remark When using P62 EXSCL0 as an external clock input pin of the serial interface input a clock of 6 4 MHz to it Figure 5 18 Block Diagram of P60 and P61 P60 SCL0 P61 SDA0 RD WRPORT WRPM Alternate function Output latch P60 P61 PM60...

Page 119: ...RPM Alternate function Output latch P62 PM62 Internal bus Selector PM6 P6 P6 Port register 6 PM6 Port mode register 6 RD Read signal WR Write signal Figure 5 20 Block Diagram of P63 P63 RD WRPORT WRPM Output latch P63 PM63 Internal bus Selector PM6 P6 P6 Port register 6 PM6 Port mode register 6 RD Read signal WR Write signal ...

Page 120: ......

Page 121: ...m clock X1 X2 or subsystem clock XT1 XT2 or to input an external clock for the main system clock EXCLK or subsystem clock EXCLKS the X1 oscillation mode XT1 oscillation mode or external clock input mode must be set by using the clock operation mode select register OSCCTL for details see 6 3 1 Clock operation mode select register OSCCTL and 3 Setting of operation mode for subsystem clock pin The re...

Page 122: ...P12 RD WRPORT WRPM Output latch P121 P123 PM121 PM123 PM12 P12 EXCLK OSCSEL EXCLKS OSCSELS OSCCTL OSCSEL OSCSELS OSCCTL P121 X1 OCD0ANote P123 XT1 OSCSEL OSCSELS OSCCTL OSCSEL OSCSELS OSCCTL Internal bus Selector Selector P12 Port register 12 PU12 Pull up resistor option register 12 PM12 Port mode register 12 OSCCTL Clock operation mode select register RD Read signal WR Write signal Note µPD78F053...

Page 123: ...t 13 Figure 5 24 Block Diagram of P130 RD Output latch P130 WRPORT P130 Internal bus P13 P13 Port register 13 RD Read signal WR Write signal Remark When reset is effected P130 outputs a low level If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the CPU reset signal P130 Set by software Reset signal ...

Page 124: ...4 This port can also be used for external interrupt request input buzzer output clock output serial interface data I O clock I O busy input and strobe output Reset signal generation sets port 14 to input mode Figures 5 25 shows a block diagram of port 14 Figure 5 25 Block Diagram of P140 and P141 P140 PCL INTP6 P141 BUZ INTP7 WRPU RD WRPORT WRPM PU140 PU141 Alternate function Output latch P140 P14...

Page 125: ...0 PU1 PU3 to PU5 PU7 PU12 PU14 A D port configuration register ADPC 1 Port mode registers PM0 to PM7 PM12 and PM14 These registers specify input or output mode for the port in 1 bit units These registers can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets these registers to FFH When port pins are used as alternate function pins set the port mode register by ...

Page 126: ...4 PM23 PM22 PM21 PM20 FF22H FFH R W 1 PM3 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R W PM4 PM43 PM42 PM41 PM40 FF24H FFH R W PM5 PM53 PM52 PM51 PM50 FF25H FFH R W PM6 PM63 PM62 PM61 PM60 FF26H FFH R W PM77 PM7 PM76 PM75 PM74 PM73 PM72 PM71 PM70 FF27H FFH R W 1 PM12 1 1 PM124 PM123 PM122 PM121 PM120 FF2CH FFH R W 1 PM14 1 PM141 PM140 FF2EH FFH R W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PMmn Pmn pin I O mode se...

Page 127: ... FF00H After reset 00H output latch R W R W P17 P1 P16 P15 P14 P13 P12 P11 P10 FF01H 00H output latch R W R W P27 P2 P26 P25 P24 P23 P22 P21 P20 FF02H 00H output latch 0 P3 0 0 0 P33 P32 P31 P30 FF03H 00H output latch R W P4 P43 P42 P41 P40 FF04H 00H output latch R W P5 P53 P52 P51 P50 FF05H 00H output latch R W P6 P63 P62 P61 P60 FF06H 00H output latch R W P77 P7 P76 P75 P74 P73 P72 P71 P70 FF07H...

Page 128: ...been specified in PU0 PU1 PU3 to PU5 PU7 PU12 and PU14 On chip pull up resistors cannot be connected to bits set to output mode and bits used as alternate function output pins regardless of the settings of PU0 PU1 PU3 to PU5 PU7 PU12 and PU14 These registers can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets these registers to 00H Figure 5 28 Format of Pull...

Page 129: ...7 A A A A A A A A D P26 ANI6 A A A A A A A D D P25 ANI5 A A A A A A D D D P24 ANI4 A A A A A D D D D P23 ANI3 A A A A D D D D D P22 ANI2 A A A D D D D D D P21 ANI1 A A D D D D D D D P20 ANI0 A D D D D D D D D 0 0 0 0 0 0 0 0 1 ADPC2 0 0 0 0 1 1 1 1 0 ADPC1 0 0 1 1 0 0 1 1 0 ADPC0 0 1 0 1 0 1 0 1 0 Other than above Cautions 1 Set the channel used for A D conversion to the input mode by using port m...

Page 130: ...e output buffer is off the pin status does not change Once data is written to the output latch it is retained until data is written to the output latch again The data of the output latch is cleared when a reset signal is generated 5 4 2 Reading from I O port 1 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin statu...

Page 131: ...on Name I O PM P P00 TI000 Input 1 TI010 Input 1 P01 TO00 Output 0 0 P02 SO11 Note Output 0 0 P03 SI11 Note Input 1 Input 1 P04 SCK11 Note Output 0 1 SSI11 Note Input 1 P05 TI001 Note Input 1 TI011 Note Input 1 P06 TO01 Note Output 0 0 Input 1 SCK10 Output 0 1 P10 TxD0 Output 0 1 SI10 Input 1 P11 RxD0 Input 1 P12 SO10 Output 0 0 P13 TxD6 Output 0 1 P14 RxD6 Input 1 P15 TOH0 Output 0 0 TOH1 Output ...

Page 132: ... EXSCL0 Input 1 P70 to P77 KR0 to KR7 Input 1 INTP0 Input 1 P120 EXLVI Input 1 P121 X1 Note 2 X2 Note 2 P122 EXCLK Note 2 Input P123 XT1 Note 2 XT2 Note 2 P124 EXCLKS Note 2 Input PCL Output 0 0 P140 INTP6 Input 1 BUZ Output 0 0 P141 INTP7 Input 1 Remarks 1 Don t care PM Port mode register P Port output latch 2 The X1 X2 P31 and P32 pins of the µPD78F0537D can be used as on chip debug mode setting...

Page 133: ...ed Input mode Does not select ANI Digital input Selects ANI Setting prohibited Digital I O selection Output mode Does not select ANI Digital output 2 When using the P121 to P124 pins to connect a resonator for the main system clock X1 X2 or subsystem clock XT1 XT2 or to input an external clock for the main system clock EXCLK or subsystem clock EXCLKS the X1 oscillation mode XT1 oscillation mode or...

Page 134: ...CLK 1 to 20 MHz can also be supplied from the EXCLK X2 P122 pin An external main system clock input can be disabled by executing the STOP instruction or using RCM As the main system clock a high speed system clock X1 clock or external main system clock or internal high speed oscillation clock can be selected by using the main clock mode register MCM 2 Subsystem clock Subsystem clock oscillator Thi...

Page 135: ...wing hardware operates with the internal low speed oscillation clock Watchdog timer TMH1 when fRL fRL 2 7 or fRL 2 9 is selected Remark fRL Internal low speed oscillation clock frequency 6 2 Configuration of Clock Generator The clock generator includes the following hardware Table 6 1 Configuration of Clock Generator Item Configuration Control registers Clock operation mode select register OSCCTL ...

Page 136: ...h fXP Peripheral hardware clock switch X1 oscillation stabilization time counter OSTS1 OSTS0 OSTS2 Oscillation stabilization time select register OSTS 3 MOST 16 MOST 15 MOST 14 MOST 13 MOST 11 Oscillation stabilization time counter status register OSTC Controller MCM0 XSEL MCS MSTOP STOP EXCLK OSCSEL AMPH Clock operation mode select register OSCCTL 4 fXP 2 fXP 22 fXP 23 fXP 24 Main clock mode regi...

Page 137: ... Internal low speed oscillation clock frequency 6 3 Registers Controlling Clock Generator The following seven registers are used to control the clock generator Clock operation mode select register OSCCTL Processor clock control register PCC Internal oscillation mode register RCM Main OSC control register MOC Main clock mode register MCM Oscillation stabilization time counter status register OSTC O...

Page 138: ...autions 1 Be sure to set AMPH to 1 if the high speed system clock oscillation frequency exceeds 10 MHz 2 Set AMPH before setting the peripheral functions after a reset release The value of AMPH can be changed only once after a reset release The clock supply to the CPU is stopped for 5 µs MIN after AMPH has been set to 1 3 If the STOP instruction is executed with AMPH set to 1 when the internal hig...

Page 139: ...otes 1 Bit 5 is read only 2 XTSTART is used in combination with EXCLKS and OSCSELS bits 5 and 4 of the Clock operation mode select register OSCCTL See 3 Setting of operation mode for subsystem clock pin Caution Be sure to clear bits 3 and 7 to 0 Remarks 1 fXP Main system clock oscillation frequency 2 fSUB Subsystem clock oscillation frequency The fastest instruction can be executed in 2 clocks of ...

Page 140: ...µs 0 5 µs TYP fXP 2 2 0 8 µs 0 4 µs 1 0 µs TYP fXP 2 3 1 6 µs 0 8 µs 2 0 µs TYP fXP 2 4 3 2 µs 1 6 µs 4 0 µs TYP fSUB 2 122 1 µs Note The main clock mode register MCM is used to set the main system clock supplied to CPU clock high speed system clock internal high speed oscillation clock see Figure 6 6 3 Setting of operation mode for subsystem clock pin The operation mode for the subsystem clock pi...

Page 141: ...oscillating stopped 0 Internal low speed oscillator oscillating 1 Internal low speed oscillator stopped RSTOP Internal high speed oscillator oscillating stopped 0 Internal high speed oscillator oscillating 1 Internal high speed oscillator stopped Notes 1 The value of this register is 00H immediately after a reset release but automatically changes to 80H after internal high speed oscillator has bee...

Page 142: ...0 X1 oscillator operating External clock from EXCLK pin is enabled 1 X1 oscillator stopped External clock from EXCLK pin is disabled Cautions 1 When setting MSTOP to 1 be sure to confirm that the CPU operates with a clock other than the high speed system clock Specifically set under either of the following conditions When MCS 0 when CPU operates with the internal high speed oscillation clock When ...

Page 143: ...ternal high speed oscillation clock fRH 1 0 Internal high speed oscillation clock fRH 1 1 High speed system clock fXH High speed system clock fXH MCS Main system clock status 0 Operates with internal high speed oscillation clock 1 Operates with high speed system clock Note Bit 1 is read only Cautions 1 XSEL can be changed only once after a reset release 2 A clock other than fPRS is supplied to the...

Page 144: ...time status fX 10 MHz fX 20 MHz 1 0 0 0 0 2 11 fX min 204 8 µs min 102 4 µs min 1 1 0 0 0 2 13 fX min 819 2 µs min 409 6 µs min 1 1 1 0 0 2 14 fX min 1 64 ms min 819 2 µs min 1 1 1 1 0 2 15 fX min 3 27 ms min 1 64 ms min 1 1 1 1 1 2 16 fX min 6 55 ms min 3 27 ms min Cautions 1 After the above time has elapsed the bits are set to 1 in order from MOST11 and remain 1 2 The oscillation stabilization t...

Page 145: ...e selection fX 10 MHz fX 20 MHz 0 0 1 2 11 fX 204 8 µs 102 4 µs 0 1 0 2 13 fX 819 2 µs 409 6 µs 0 1 1 2 14 fX 1 64 ms 819 2 µs 1 0 0 2 15 fX 3 27 ms 1 64 ms 1 0 1 2 16 fX 6 55 ms 3 27 ms Other than above Setting prohibited Cautions 1 To set the STOP mode when the X1 clock is used as the CPU clock set OSTS before executing the STOP instruction 2 Do not change the value of the OSTS register during t...

Page 146: ...gure 6 9 Example of External Circuit of X1 Oscillator Crystal or Ceramic Oscillation VSS X1 X2 Crystal resonator or ceramic resonator Cautions are listed on the next page 6 4 2 XT1 oscillator The XT1 oscillator oscillates with a crystal resonator standard 32 768 kHz connected to the XT1 and XT2 pins Figure 6 10 shows an example of the external circuit of the XT1 oscillator Figure 6 10 Example of E...

Page 147: ...current flows Always make the ground point of the oscillator capacitor the same potential as VSS Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator Note that the XT1 oscillator is designed as a low amplitude circuit for reducing power consumption Figure 6 11 shows examples of incorrect resonator connection Figure 6 11 Example...

Page 148: ... of oscillator potential at points A B and C fluctuates VSS X1 X2 VSS X1 X2 A B C Pmn VDD High current High current e Signals are fetched VSS X1 X2 Remark When using the subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 side Cautions 2 When X2 and XT1 are wired in parallel the crosstalk noise of X2 may increase with XT1 resulting in malfunct...

Page 149: ...reset release the internal high speed oscillator automatically starts oscillation 8 MHz TYP 6 4 5 Internal low speed oscillator The internal low speed oscillator is incorporated in the 78K0 KE2 The internal low speed oscillation clock is only used as the watchdog timer and the clock of 8 bit timer H1 The internal low speed oscillation clock cannot be used as the CPU clock Can be stopped by softwar...

Page 150: ... following 1 Enhancement of security function When the X1 clock is set as the CPU clock by the default setting the device cannot operate if the X1 clock is damaged or badly connected and therefore does not operate after reset is released However the start clock of the CPU is the internal high speed oscillation clock so the device can be started by the internal high speed oscillation clock after a ...

Page 151: ... and regulator have elapsed and then reset processing is performed 4 Set the start of oscillation of the X1 or XT1 clock via software see 1 in 6 6 1 Example of controlling high speed system clock and 1 in 6 6 3 Example of controlling subsystem clock 5 When switching the CPU clock to the X1 or XT1 clock wait for the clock oscillation to stabilize and then set switching via software see 3 in 6 6 1 E...

Page 152: ...hen the power is turned on an internal reset signal is generated by the power on clear POC circuit 2 When the power supply voltage exceeds 2 7 V TYP the reset is released and the internal high speed oscillator automatically starts oscillation 3 After the reset is released and reset processing is performed the CPU starts operation on the internal high speed oscillation clock 4 Set the start of osci...

Page 153: ...edures for the following cases 1 When oscillating X1 clock 2 When using external main system clock 3 When using high speed system clock as CPU clock and peripheral hardware clock 4 When stopping high speed system clock 1 Example of setting procedure when oscillating the X1 clock 1 Setting frequency OSCCTL register Using AMPH set the gain of the on chip oscillator according to the frequency to be u...

Page 154: ...igh speed system clock oscillation frequency 2 Setting P121 X1 and P122 X2 EXCLK pins and selecting operation mode OSCCTL register When EXCLK and OSCSEL are set to 1 the mode is switched from port mode to external clock input mode EXCLK OSCSEL Operation Mode of High Speed System Clock Pin P121 X1 Pin P122 X2 EXCLK Pin 1 1 External clock input mode I O port External clock input 3 Controlling extern...

Page 155: ...tem clock fXH High speed system clock fXH Caution If the high speed system clock is selected as the main system clock a clock other than the high speed system clock cannot be set as the peripheral hardware clock 3 Setting the main system clock as the CPU clock and selecting the division ratio PCC register When CSS is cleared to 0 the main system clock is supplied to the CPU To select the CPU clock...

Page 156: ...speed oscillation clock The following describes examples of clock setting procedures for the following cases 1 When restarting oscillation of the internal high speed oscillation clock 2 When using internal high speed oscillation clock as CPU clock and internal high speed oscillation clock or high speed system clock as peripheral hardware clock 3 When stopping the internal high speed oscillation cl...

Page 157: ...in System Clock fXP Peripheral Hardware Clock fPRS 0 0 0 1 Internal high speed oscillation clock fRH 1 0 Internal high speed oscillation clock fRH High speed system clock fXH 3 Selecting the CPU clock division ratio PCC register When CSS is cleared to 0 the main system clock is supplied to the CPU To select the CPU clock division ratio use PCC0 PCC1 and PCC2 CSS PCC2 PCC1 PCC0 CPU Clock fCPU Selec...

Page 158: ...connected across the XT1 and XT2 pins External subsystem clock External clock is input to the EXCLKS pin When the subsystem clock is not used the XT1 P123 and XT2 EXCLKS P124 pins can be used as I O port pins Caution The XT1 P123 and XT2 EXCLKS P124 pins are in the I O port mode after a reset release The following describes examples of setting procedures for the following cases 1 When oscillating ...

Page 159: ...ubsystem clock Note The setting of 1 is not necessary when while the subsystem clock is operating 2 Switching the CPU clock PCC register When CSS is set to 1 the subsystem clock is supplied to the CPU CSS PCC2 PCC1 PCC0 CPU Clock fCPU Selection 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 fSUB 2 1 Other than above Setting prohibited 4 Example of setting procedure when stopping the subsystem clock 1 Confirming th...

Page 160: ...internal low speed oscillation clock 1 Clearing LSRSTOP to 0 RCM register When LSRSTOP is cleared to 0 the internal low speed oscillation clock is restarted Caution If Internal low speed oscillator cannot be stopped is selected by the option byte oscillation of the internal low speed oscillation clock cannot be controlled 6 6 5 Clocks supplied to CPU and peripheral hardware The following table sho...

Page 161: ...nal low speed oscillation Operable Internal high speed oscillation Operating X1 oscillation EXCLK input Operable XT1 oscillation EXCLKS input Operable CPU Operating with X1 oscillation or EXCLK input CPU X1 oscillation EXCLK input STOP CPU X1 oscillation EXCLK input HALT Internal low speed oscillation Operable Internal high speed oscillation Selectable by CPU X1 oscillation EXCLK input Operating X...

Page 162: ...cked 1 1 A B C X1 clock 10 MHz fXH 20 MHz 1 0 1 0 Must be checked 1 1 A B C external main clock 10 MHz fXH 20 MHz 1 1 1 0 Must not be checked 1 1 Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set see CHAPTER 29 ELECTRICAL SPECIFICATIONS TARGET 3 CPU operating with subsystem clock D after reset release A The CPU operates with the internal high sp...

Page 163: ... be changed only once after a reset release This setting is not necessary if it has already been set Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set see CHAPTER 29 ELECTRICAL SPECIFICATIONS TARGET 5 CPU clock changing from internal high speed oscillation clock B to subsystem clock D Setting sequence of SFR registers Setting Flag of SFR Registe...

Page 164: ...lation Stabilization CSS 0 0 1 C D XT1 clock 1 Necessary 1 C D external subsystem clock 0 1 1 Unnecessary 1 Unnecessary if the CPU is operating with the subsystem clock 8 CPU clock changing from subsystem clock D to internal high speed oscillation clock B Setting sequence of SFR registers Setting Flag of SFR Register Status Transition RSTOP RSTS MCM0 CSS D B 0 Confirm this flag is 1 0 0 Unnecessar...

Page 165: ...necessary if it has already been set Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set see CHAPTER 29 ELECTRICAL SPECIFICATIONS TARGET 10 HALT mode E set while CPU is operating with internal high speed oscillation clock B HALT mode F set while CPU is operating with high speed system clock C HALT mode G set while CPU is operating with subsystem c...

Page 166: ...ock XT1 clock Stabilization of XT1 oscillation XTSTART 0 EXCLKS 0 OSCSELS 1 or XTSTART 1 After elapse of oscillation stabilization time External main system clock input can be disabled MSTOP 1 Internal high speed oscillation clock Operating current can be reduced by stopping internal high speed oscillator RSTOP 1 X1 clock X1 oscillation can be stopped MSTOP 1 External main system clock External su...

Page 167: ... clocks 0 1 0 0 1 clock 1 clock 1 clock 1 clock fXP 8fSUB clocks 1 2 clocks 2 clocks 2 clocks 2 clocks 2 clocks Caution Selection of the main system clock cycle division factor PCC0 to PCC2 and switchover from the main system clock to the subsystem clock changing CSS from 0 to 1 should not be set simultaneously Simultaneous setting is possible however for selection of the main system clock cycle d...

Page 168: ...ock to the high speed system clock oscillation with fRH 8 MHz fXH 10 MHz 1 2fRH fXH 1 2 8 10 1 2 0 8 1 1 6 2 6 2 clocks 6 6 9 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation disabling external clock input and conditions before the clock oscillation is stopped Table 6 9 Conditions Before the Clock Oscillation Is Stoppe...

Page 169: ... counter 01 Y N N N Y TI001 pin Note 50 Y N N N Y TI50 pin Note 8 bit timer event counter 51 Y N N N Y TI51 pin Note H0 Y N N Y N 8 Bit timer H1 Y N Y N N Watch timer Y Y N N N Watchdog timer N N Y N N Buzzer output Y N N N N Clock output Y Y N N N A D converter Y N N N N UART0 Y N N Y N UART6 Y N N Y N CSI10 Y N N N Y SCK10 pin Note CSI11 Y N N N Y SCK11 pin Note Serial interface IIC0 Y N N N Y E...

Page 170: ...rval 2 Square wave output 16 bit timer event counters 00 and 01 can output a square wave with any selected frequency 3 External event counter 16 bit timer event counters 00 and 01 can measure the number of pulses of an externally input signal 4 One shot pulse output 16 bit timer event counters 00 and 01 can output a one shot pulse whose output pulse width can be set freely 5 PPG output 16 bit time...

Page 171: ...egister 0 PM0 Port register 0 P0 Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F0534 78F0535 78F0536 78F0537 78F0537D Figures 7 1 and 7 2 show the block diagrams Figure 7 1 Block Diagram of 16 Bit Timer Event Counter 00 Internal bus Capture compare control register 00 CRC00 TI010 TO00 P01 fPRS fPRS 22 fPRS 28 fPRS TI000 P00 Prescaler mode register 00 PRM00 2 PRM001 PRM000 CRC002 16 bit timer ca...

Page 172: ... bus TMC013 TMC012 TMC011OVF01 TOC014LVS01 LVR01 TOC011TOE01 Selector 16 bit timer capture compare register 001 CR001 Selector Selector Selector Noise elimi nator Noise elimi nator Output controller OSPE01 OSPT01 Output latch P06 PM06 To CR011 1 16 bit timer counter 0n TM0n TM0n is a 16 bit read only register that counts count pulses The counter is incremented in synchronization with the rising ed...

Page 173: ...CR01n 2 When TM0n is read input of the count clock is temporarily stopped and it is resumed after the timer has been read Therefore no clock miss occurs 2 16 bit timer capture compare register 00n CR00n 16 bit timer capture compare register 01n CR01n CR00n and CR01n are 16 bit registers that are used with a capture function or comparison function selected by using CRC0n Change the value of CR00n w...

Page 174: ...egister The count value of TM0n is captured to CR01n when a capture trigger is input It is possible to select the valid edge of the TI00n pin as the capture trigger The TI00n pin valid edge is set by PRM0n Cautions 1 To use this register as a compare register set a value other than 0000H to CR00n and CR01n 2 The valid edge of TI010 and timer output TO00 cannot be used for the P01 pin at the same t...

Page 175: ...tured 01 Rising 00 Falling TI00n pin input Note 11 Both edges Capture operation of CR01n Interrupt signal INTTM01n signal is generated each time value is captured Note The capture operation of CR01n is not affected by the setting of the CRC0n1 bit Caution To capture the count value of the TM0n register to the CR00n register by using the phase reverse to that input to the TI00n pin the interrupt re...

Page 176: ... that sets the 16 bit timer event counter 0n operation mode TM0n clear mode and output timing and detects an overflow Rewriting TMC0n is prohibited during operation when TMC0n3 and TMC0n2 other than 00 However it can be changed when TMC0n3 and TMC0n2 are cleared to 00 stopping operation and when OVF0n is cleared to 0 TMC0n can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal...

Page 177: ...entered upon a match between TM00 and CR000 TMC001 Condition to reverse timer output TO00 0 Match between TM00 and CR000 or match between TM00 and CR010 1 Match between TM00 and CR000 or match between TM00 and CR010 Trigger input of TI000 pin valid edge OVF00 TM00 overflow flag Clear 0 Clears OVF00 to 0 or TMC003 and TMC002 00 Set 1 Overflow occurs OVF00 is set to 1 when the value of TM00 changes ...

Page 178: ...entered upon a match between TM01 and CR001 TMC011 Condition to reverse timer output TO01 0 Match between TM01 and CR001 or match between TM01 and CR011 1 Match between TM01 and CR001 or match between TM01 and CR011 Trigger input of TI001 pin valid edge OVF01 TM01 overflow flag Clear 0 Clears OVF01 to 0 or TMC013 and TMC012 00 Set 1 Overflow occurs OVF01 is set to 1 when the value of TM01 changes ...

Page 179: ...register 1 Operates as capture register CRC001 CR000 capture trigger selection 0 Captures on valid edge of TI010 pin 1 Captures on valid edge of TI000 pin by reverse phase Note The valid edge of the TI010 and TI000 pin is set by PRM00 If ES001 and ES000 are set to 11 both edges when CRC001 is 1 the valid edge of the TI000 pin cannot be detected CRC000 CR000 operating mode selection 0 Operates as c...

Page 180: ...1 Captures on valid edge of TI001 pin by reverse phase Note The valid edge of the TI011 and TI001 pin is set by PRM01 If ES011 and ES010 are set to 11 both edges when CRC011 is 1 the valid edge of the TI001 pin cannot be detected CRC010 CR001 operating mode selection 0 Operates as compare register 1 Operates as capture register If TMC013 and TMC012 are set to 11 clear start mode entered upon a mat...

Page 181: ...bits is prohibited during operation However TOC0n4 can be rewritten during timer operation as a means to rewrite CR01n see 7 5 1 Rewriting CR01n during TM0n operation TOC0n can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears TOC0n to 00H Caution Be sure to set TOC0n using the following procedure 1 Set TOC0n4 and TOC0n1 to 1 2 Set only TOE0n to 1 3 Set eith...

Page 182: ...errupt signal INTTM010 is generated even when TOC004 0 LVS00 LVR00 Setting of TO00 pin output status 0 0 No change 0 1 Initial value of TO00 pin output is low level TO00 pin output is cleared to 0 1 0 Initial value of TO00 pin output is high level TO00 pin output is set to 1 1 1 Setting prohibited LVS00 and LVR00 can be used to set the initial value of the output level of the TO00 pin If the initi...

Page 183: ...rrupt signal INTTM011 is generated even when TOC014 0 LVS01 LVR01 Setting of TO01 pin output status 0 0 No change 0 1 Initial value of TO01 pin output is low level TO01 pin output is cleared to 0 1 0 Initial value of TO01 pin output is high level TO01 pin output is set to 1 1 1 Setting prohibited LVS01 and LVR01 can be used to set the initial value of the output level of the TO01 pin If the initia...

Page 184: ... valid edge Setting the TI00n pin as a capture trigger 2 If the operation of the 16 bit timer event counter 0n is enabled when the TI00n or TI01n pin is at high level and when the valid edge of the TI00n or TI01n pin is specified to be the rising edge or both edges the high level of the TI00n or TI01n pin is detected as a rising edge Note this when the TI00n or TI01n pin is pulled up However the r...

Page 185: ...hibited 1 1 Both falling and rising edges ES001 ES000 TI000 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges Count clock selection PRM001 PRM000 fPRS 2 MHz fPRS 5 MHz fPRS 10 MHz fPRS 20 MHz 0 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz 0 1 fPRS 2 2 500 kHz 1 25 MHz 2 5 MHz 5 MHz 1 0 fPRS 2 8 7 81 kHz 19 53 kHz 39 06 kHz 78 12 kHz 1 1 TI000 va...

Page 186: ...ted 1 1 Both falling and rising edges ES011 ES010 TI001 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges Count clock selection PRM011 PRM010 fPRS 2 MHz fPRS 5 MHz fPRS 10 MHz fPRS 20 MHz 0 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz 0 1 fPRS 2 4 125 kHz 312 5 kHz 625 kHz 1 25 MHz 1 0 fPRS 2 6 31 25 kHz 78 125 kHz 156 25 kHz 312 5 kHz 1 1 TI001...

Page 187: ...0 P01 TO00 TI010 P05 TI001 SSI11 and P06 TO01 TI011 pins for timer input set PM00 PM01 PM05 and PM06 to 1 At this time the output latches of P00 P01 P05 and P06 may be 0 or 1 PM0 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets PM0 to FFH Figure 7 15 Format of Port Mode Register 0 PM0 7 1 6 PM06 5 PM05 4 PM04 3 PM03 2 PM02 1 PM01 0 PM00 Symbol PM0 Address...

Page 188: ...TM00n is generated This INTTM00n signal enables TM0n to operate as an interval timer Remarks 1 For the setting of I O pins see 7 3 5 Port mode register 0 PM0 2 For how to enable the INTTM00n interrupt see CHAPTER 19 INTERRUPT FUNCTIONS Figure 7 16 Block Diagram of Interval Timer Operation 16 bit counter TM0n CR00n register Operable bits TMC0n3 TMC0n2 Count clock Clear Match signal INTTM00n signal ...

Page 189: ...aler mode register 0n PRM0n 0 0 0 0 0 3 2 PRM0n1 PRM0n0 ES1n1 ES1n0 ES0n1 ES0n0 Selects count clock 0 0 1 0 1 e 16 bit timer counter 0n TM0n By reading TM0n the count value can be read f 16 bit capture compare register 00n CR00n If M is set to CR00n the interval time is as follows Interval time M 1 Count clock cycle Setting CR00n to 0000H is prohibited g 16 bit capture compare register 01n CR01n U...

Page 190: ... 11 TMC0n3 TMC0n2 bits 00 Register initial setting PRM0n register CRC0n register CR00n register port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 11 Starts count operation The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00 START STOP 1 Count operation start flow 2 Count operation stop flow Remark n...

Page 191: ... pin output that is inverted at fixed intervals enables TO0n to output a square wave Remarks 1 For the setting of I O pins see 7 3 5 Port mode register 0 PM0 2 For how to enable the INTTM00n signal interrupt see CHAPTER 19 INTERRUPT FUNCTIONS Figure 7 20 Block Diagram of Square Wave Output Operation 16 bit counter TM0n CR00n register Operable bits TMC0n3 TMC0n2 Count clock Clear Match signal INTTM...

Page 192: ...tween TM0n and CR00n 0 1 1 d Prescaler mode register 0n PRM0n 0 0 0 0 0 3 2 PRM0n1 PRM0n0 ES1n1 ES1n0 ES0n1 ES0n0 Selects count clock 0 0 1 0 1 e 16 bit timer counter 0n TM0n By reading TM0n the count value can be read f 16 bit capture compare register 00n CR00n If M is set to CR00n the interval time is as follows Square wave frequency 1 2 M 1 Count clock cycle Setting CR00n to 0000H is prohibited...

Page 193: ... setting PRM0n register CRC0n register TOC0n registerNote CR00n register port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 11 Starts count operation The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00 START STOP 1 Count operation start flow 2 Count operation stop flow Note Care must be exercised whe...

Page 194: ...Number of times of detection of valid edge of external event Set value of CR00n 1 However the first match interrupt immediately after the timer event counter has started operating is generated with the following timing Timing of generation of INTTM00n signal first time only Number of times of detection of valid edge of external event input Set value of CR00n 2 To detect the valid edge the signal i...

Page 195: ...n1 ES0n0 Selects count clock specifies valid edge of TI00n 00 Falling edge detection 01 Rising edge detection 10 Setting prohibited 11 Both edges detection 0 1 1 e 16 bit timer counter 0n TM0n By reading TM0n the count value can be read f 16 bit capture compare register 00n CR00n If M is set to CR00n the interrupt signal INTTM00n is generated when the number of external events reaches M 1 Setting ...

Page 196: ...3 TMC0n2 bits 11 TMC0n3 TMC0n2 bits 00 Register initial setting PRM0n register CRC0n register CR00n register port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 11 Starts count operation The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00 START STOP 1 Count operation start flow 2 Count operation stop ...

Page 197: ...ers and capture registers a When CR00n and CR01n are used as compare registers Signals INTTM00n and INTTM01n are generated when the value of TM0n matches the value of CR00n and CR01n b When CR00n and CR01n are used as capture registers The count value of TM0n is captured to CR00n and the INTTM00n signal is generated when the valid edge is input to the TI01n pin or when the phase reverse to that of...

Page 198: ...m of Clear Start Mode Entered by TI00n Pin Valid Edge Input CR00n Compare Register CR01n Compare Register Timer counter TM0n Clear Output controller Edge detection Compare register CR01n Match signal TO0n pin Match signal Interrupt signal INTTM00n Interrupt signal INTTM01n TI00n pin Compare register CR00n Operable bits TMC0n3 TMC0n2 Count clock Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F053...

Page 199: ...b TOC0n 13H PRM0n 10H CRC0n 00H TMC0n 0AH TM0n register 0000H Operable bits TMC0n3 TMC0n2 Count clear input TI00n pin input Compare register CR00n Compare match interrupt INTTM00n Compare register CR01n Compare match interrupt INTTM01n TO0n pin output M 10 M N N N N M M M 00 N a and b differ as follows depending on the setting of bit 1 TMC0n1 of the 16 bit timer mode control register 0n TMC0n a Th...

Page 200: ... of Clear Start Mode Entered by TI00n Pin Valid Edge Input CR00n Compare Register CR01n Capture Register Timer counter TM0n Clear Output controller Edge detector Capture register CR01n Capture signal TO0n pin Match signal Interrupt signal INTTM00n Interrupt signal INTTM01n TI00n pin Compare register CR00n Operable bits TMC0n3 TMC0n2 Count clock Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F053...

Page 201: ... match interrupt INTTM00n Capture register CR01n Capture interrupt INTTM01n TO0n pin output 0001H 10 Q P N M S 00 0000H M N S P Q This is an application example where the output level of the TO0n pin is inverted when the count value has been captured cleared The count value is captured to CR01n and TM0n is cleared to 0000H when the valid edge of the TI00n pin is detected When the count value of TM...

Page 202: ...put 0003H 0003H 10 Q P N M S 00 0000H M 4 4 4 4 N S P Q This is an application example where the width set to CR00n 4 clocks in this example is to be output from the TO0n pin when the count value has been captured cleared The count value is captured to CR01n a capture interrupt signal INTTM01n is generated TM0n is cleared to 0000H and the output level of the TO0n pin is inverted when the valid edg...

Page 203: ... of Clear Start Mode Entered by TI00n Pin Valid Edge Input CR00n Capture Register CR01n Compare Register Timer counter TM0n Clear Output controller Edge detection Capture register CR00n Capture signal TO0n pin Match signal Interrupt signal INTTM01n Interrupt signal INTTM00n TI00n pin Compare register CR01n Operable bits TMC0n3 TMC0n2 Count clock Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F05...

Page 204: ... is an application example where the output level of the TO0n pin is to be inverted when the count value has been captured cleared TM0n is cleared at the rising edge detection of the TI00n pin and it is captured to CR00n at the falling edge detection of the TI00n pin When bit 1 CRC0n1 of capture compare control register 0n CRC0n is set to 1 the count value of TM0n is captured to CR00n in the phase...

Page 205: ...n pin when the count value has been captured cleared TM0n is cleared to 0000H at the rising edge detection of the TI00n pin and captured to CR00n at the falling edge detection of the TI00n pin The output level of the TO0n pin is inverted when TM0n is cleared to 0000H because the rising edge of the TI00n pin has been detected or when the value of TM0n matches that of a compare register CR01n When b...

Page 206: ...e Register CR01n Capture Register Timer counter TM0n Clear Output controller Capture register CR00n Capture signal Capture signal TO0n pinNote Interrupt signal INTTM01n Interrupt signal INTTM00n Capture register CR01n Operable bits TMC0n3 TMC0n2 Count clock Edge detection TI00n pin Edge detection TI01n pinNote Selector Note The timer output TO0n cannot be used when detecting the valid edge of the ...

Page 207: ...register CR00n Capture interrupt INTTM00n Capture register CR01n Capture interrupt INTTM01n TO0n pin output 10 R S T O L M N P Q 00 L 0000H 0000H L M N O P Q R S T This is an application example where the count value is captured to CR01n TM0n is cleared and the TO0n pin output is inverted when the rising or falling edge of the TI00n pin is detected When the edge of the TI01n pin is detected an int...

Page 208: ...n2 Capture trigger input TI01n pin input Capture register CR00n Capture interrupt INTTM00n Capture count clear input TI00n Capture register CR01n Capture interrupt INTTM01n 10 R S T O L M N P Q 00 FFFFH L L 0000H 0000H L M N O P Q R S T This is a timing example where an edge is not input to the TI00n pin in an application where the count value is captured to CR00n when the rising or falling edge o...

Page 209: ...nput CR00n Capture Register CR01n Capture Register 3 3 c TOC0n 13H PRM0n 00H CRC0n 07H TMC0n 0AH TM0n register 0000H Operable bits TMC0n3 TMC0n2 Capture count clear input TI00n pin input Capture register CR00n Capture register CR01n Capture interrupt INTTM01n Capture input TI01n Compare match interrupt INTTM00n 0000H 10 P O M Q R T S W N L 00 L L L N R P T 0000H M O Q S W ...

Page 210: ...gister 0 CR01n used as compare register 1 CR01n used as capture register 0 TI01n pin is used as capture trigger of CR00n 1 Reverse phase of TI00n pin is used as capture trigger of CR00n c 16 bit timer output control register 0n TOC0n 0 0 0 0 1 0 1 LVR0n LVS0n TOC0n4 OSPE0n OSPT0n TOC0n1 TOE0n 0 Disables TO0n outputNote 1 Enables TO0n output 00 Does not invert TO0n output on match between TM0n and ...

Page 211: ...ter and when its value matches the count value of TM0n an interrupt signal INTTM00n is generated The count value of TM0n is not cleared To use this register as a capture register select either the TI00n or TI01n pinNote input as a capture trigger When the valid edge of the capture trigger is detected the count value of TM0n is stored in CR00n Note The timer output TO0n cannot be used when detectio...

Page 212: ...register CRC0n register TOC0n registerNote CR00n CR01n registers TMC0n TMC0n1 bit port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 10 Starts count operation When the valid edge is input to the TI00n pin the value of the TM0n register is cleared START 1 Count operation start flow 2 TM0n register clear start flow TMC0n3 TMC0n2 bits 00 The coun...

Page 213: ...and CR01n are used as compare registers One of CR00n or CR01n is used as a compare register and the other is used as a capture register Both CR00n and CR01n are used as capture registers Remarks 1 For the setting of the I O pins see 7 3 5 Port mode register 0 PM0 2 For how to enable the INTTM00n signal interrupt see CHAPTER 19 INTERRUPT FUNCTIONS 1 Free running timer mode operation CR00n compare r...

Page 214: ...e The output level of the TO0n pin is reversed each time the count value of TM0n matches the set value of CR00n or CR01n When the count value matches the register value the INTTM00n or INTTM01n signal is generated Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F0534 78F0535 78F0536 78F0537 78F0537D 2 Free running timer mode operation CR00n compare register CR01n capture register Figure 7 39 Bloc...

Page 215: ...OVF0n 01 M N S P Q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000H 0001H M N S P Q This is an application example where a compare register and a capture register are used at the same time in the free running timer mode In this example the INTTM00n signal is generated and the output level of the TO0n pin is reversed each time the count value of TM0n matches the set value of CR00n c...

Page 216: ...rupt signal INTTM01n Interrupt signal INTTM00n Capture register CR01n Operable bits TMC0n3 TMC0n2 Count clock Edge detection TI00n pin Edge detection TI01n pin Selector Remarks 1 If both CR00n and CR01n are used as capture registers in the free running timer mode the output level of the TO0n pin is not inverted However it can be inverted each time the valid edge of the TI00n pin is detected if bit...

Page 217: ...pture Register 1 2 a TOC0n 13H PRM0n 50H CRC0n 05H TMC0n 04H FFFFH TM0n register 0000H Operable bits TMC0n3 TMC0n2 Capture trigger input TI00n Capture register CR01n Capture interrupt INTTM01n Capture trigger input TI01n Capture register CR00n Capture interrupt INTTM00n Overflow flag OVF0n 01 M A B C D E N S P Q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000H ...

Page 218: ...rrupt INTTM00n Capture trigger input TI00n Capture register CR01n Capture interrupt INTTM01n 01 L M P S N O R Q T 00 0000H 0000H L M N O P Q R S T L L This is an application example where both the edges of the TI01n pin are detected and the count value is captured to CR00n in the free running timer mode When both CR00n and CR01n are used as capture registers and when the valid edge of only the TI0...

Page 219: ...1 CR00n used as capture register 0 CR01n used as compare register 1 CR01n used as capture register 0 TI01n pin is used as capture trigger of CR00n 1 Reverse phase of TI00n pin is used as capture trigger of CR00n c 16 bit timer output control register 0n TOC0n 0 0 0 0 1 0 1 LVR0n LVS0n TOC0n4 OSPE0n OSPT0n TOC0n1 TOE0n 0 Disables TO0n output 1 Enables TO0n output 00 Does not invert TO0n output on m...

Page 220: ...s register is used as a compare register and when its value matches the count value of TM0n an interrupt signal INTTM00n is generated The count value of TM0n is not cleared To use this register as a capture register select either the TI00n or TI01n pin input as a capture trigger When the valid edge of the capture trigger is detected the count value of TM0n is stored in CR00n g 16 bit capture compa...

Page 221: ...s 0 1 Register initial setting PRM0n register CRC0n register TOC0n registerNote CR00n CR01n register TMC0n TMC0n1 bit port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits to 01 Starts count operation START 1 Count operation start flow TMC0n3 TMC0n2 bits 0 0 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to...

Page 222: ... cycle Set value of CR00n 1 Count clock cycle Duty Set value of CR01n 1 Set value of CR00n 1 Caution To change the duty factor value of CR01n during operation see 7 5 1 Rewriting CR01n during TM0n operation Remarks 1 For the setting of I O pins see 7 3 5 Port mode register 0 PM0 2 For how to enable the INTTM00n signal interrupt see CHAPTER 19 INTERRUPT FUNCTIONS Figure 7 45 Block Diagram of PPG Ou...

Page 223: ...ables one shot pulse output Specifies initial value of TO0n output F F 0 1 1 1 d Prescaler mode register 0n PRM0n 0 0 0 0 0 3 2 PRM0n1 PRM0n0 ES1n1 ES1n0 ES0n1 ES0n0 Selects count clock 0 0 1 0 1 e 16 bit timer counter 0n TM0n By reading TM0n the count value can be read f 16 bit capture compare register 00n CR00n An interrupt signal INTTM00n is generated when the value of this register matches the...

Page 224: ...RM0n register CRC0n register TOC0n registerNote CR00n CR01n registers port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits Starts count operation START 1 Count operation start flow TMC0n3 TMC0n2 bits 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00 STOP 2 Count operation stop flow N 1 N 1 M 1 M 1 M ...

Page 225: ...ng the valid edge of the TI00n pin while the one shot pulse is output To output the one shot pulse again generate the trigger after the current one shot pulse output has completed 2 To use only the setting of OSPT0n to 1 as the trigger of one shot pulse output do not change the level of the TI00n pin or its alternate function port pin Otherwise the pulse will be unexpectedly output Remarks 1 For t...

Page 226: ...d as compare register CR01n used as compare register c 16 bit timer output control register 0n TOC0n 0 0 1 1 1 0 1 LVR0n LVS0n TOC0n4 OSPE0n OSPT0n TOC0n1 TOE0n Enables TO0n pin output Inverts TO0n output on match between TM0n and CR00n CR01n Specifies initial value of TO0n pin output Enables one shot pulse output Software trigger is generated by writing 1 to this bit operation is not affected eve...

Page 227: ...se is output When the value of TM0n matches that of CR00n an interrupt signal INTTM00n is generated and the output level of the TO0n pin is inverted g 16 bit capture compare register 01n CR01n This register is used as a compare register when a one shot pulse is output When the value of TM0n matches that of CR01n an interrupt signal INTTM01n is generated and the output level of the TO0n pin is inve...

Page 228: ...ompare register CR00n Compare match interrupt INTTM00n Compare register CR01n Compare match interrupt INTTM01n TO0n pin output TO0n output control bits TOE0n TOC0n4 TOC0n1 N M N M N M 01 or 10 00 00 N N N M M M M 1 M 1 1 2 2 3 TO0n output level is not inverted because no one shot trigger is input Time from when the one shot pulse trigger is input until the one shot pulse is output M 1 Count clock ...

Page 229: ...g the TMC0n3 and TMC0n2 bits Starts count operation START 1 Count operation start flow 2 One shot trigger input flow TMC0n3 TMC0n2 bits 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00 STOP 3 Count operation stop flow TOC0n OSPT0n bit 1 or edge input to TI00n pin Write the same value to the bits other than the OSTP0n bit Note Care must be exercised...

Page 230: ...Block Diagram of Pulse Width Measurement Free Running Timer Mode Timer counter TM0n Capture register CR00n Capture signal Capture signal Interrupt signal INTTM01n Interrupt signal INTTM00n Capture register CR01n Operable bits TMC0n3 TMC0n2 Count clock Edge detection TI00n pin Edge detection TI01n pin Selector Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F0534 78F0535 78F0536 78F0537 78F0537D F...

Page 231: ...g two input signals of the TI00n and TI01n pins free running timer mode Set the free running timer mode TMC0n3 and TMC0n2 01 When the valid edge of the TI00n pin is detected the count value of TM0n is captured to CR01n When the valid edge of the TI01n pin is detected the count value of TM0n is captured to CR00n Specify detection of both the edges of the TI00n and TI01n pins By this measurement met...

Page 232: ...Operable bits TMC0n3 TMC0n2 Capture trigger input TI00n Capture register CR01n Capture interrupt INTTM01n Capture trigger input TI01n Capture register CR00n Capture interrupt INTTM00n Overflow flag OVF0n 01 M A B C D E N S P Q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000H A B C D E 0000H M N S P Q Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F0534 78F0535 78F0536 78F0537 78F...

Page 233: ... By subtracting the value of one capture register from that of another a high level width low level width and cycle are calculated If an overflow occurs the value becomes negative if one captured value is simply subtracted from another and therefore a borrow occurs bit 0 CY of the program status word PSW is set to 1 If this happens ignore CY and take the calculated value as the pulse width In addi...

Page 234: ...stored in CR01n as a cycle Clear bit 0 OVF0n of 16 bit timer mode control register 0n TMC0n to 0 Figure 7 55 Timing Example of Pulse Width Measurement 3 TMC0n 08H PRM0n 10H CRC0n 07H FFFFH TM0n register 0000H Operable bits TMC0n3 TMC0n2 Capture count clear input TI00n Capture register CR00n Capture register CR01n Capture interrupt INTTM01n Overflow flag OVF0n Capture trigger input TI01n Capture in...

Page 235: ...n pin is used as capture trigger of CR00n 1 Reverse phase of TI00n pin is used as capture trigger of CR00n c 16 bit timer output control register 0n TOC0n 0 0 0 0 0 LVR0n LVS0n TOC0n4 OSPE0n OSPT0n TOC0n1 TOE0n 0 0 0 d Prescaler mode register 0n PRM0n 0 1 0 1 0 1 0 1 0 3 2 PRM0n1 PRM0n0 ES1n1 ES1n0 ES0n1 ES0n0 Selects count clock setting valid edge of TI00n is prohibited 00 Falling edge detection ...

Page 236: ...d as a capture register Either the TI00n or TI01n pin is selected as a capture trigger When a specified edge of the capture trigger is detected the count value of TM0n is stored in CR00n g 16 bit capture compare register 01n CR01n This register is used as a capture register The signal input to the TI00n pin is used as a capture trigger When the capture trigger is detected the count value of TM0n i...

Page 237: ...HAPTER 7 16 BIT TIMER EVENT COUNTERS 00 AND 01 Preliminary User s Manual U17260EJ3V1UD 237 Figure 7 57 Example of Software Processing for Pulse Width Measurement 1 2 a Example of free running timer mode ...

Page 238: ...ial setting PRM0n register CRC0n register port setting Initial setting of these registers is performed before setting the TMC0n3 and TMC0n2 bits Starts count operation START 1 Count operation start flow TMC0n3 TMC0n2 bits 00 The counter is initialized and counting is stopped by clearing the TMC0n3 and TMC0n2 bits to 00 STOP 3 Count operation stop flow Note The capture interrupt signal INTTM00n is ...

Page 239: ...2 Disable reversal of the timer output when the value of TM0n matches that of CR01n TOC0n4 0 3 Change the value of CR01n 4 Wait for one cycle of the count clock of TM0n 5 Enable reversal of the timer output when the value of TM0n matches that of CR01n TOC0n4 1 6 Clear the interrupt flag of INTTM01n TMIF01n 0 to 0 7 Enable interrupt INTTM01n TMMK01n 0 Remark For TMIF01n and TMMK01n see CHAPTER 19 I...

Page 240: ... bit TOC0n LVR0n bit Operable bits TMC0n3 TMC0n2 TO0n pin output INTTM00n signal 1 00 2 1 3 4 4 4 01 10 or 11 1 The TO0n pin output goes high when LVS0n and LVR0n 10 2 The TO0n pin output goes low when LVS0n and LVR0n 01 the pin output remains unchanged from the high level even if LVS0n and LVR0n are cleared to 00 3 The timer starts operating when TMC0n3 and TMC0n2 are set to 01 10 or 11 Because L...

Page 241: ...OC0n 00H As free running timer As PPG output Setting identical values or 0000H to CR00n and CP01n is prohibited As one shot pulse output As pulse width measurement TOC0n 00H 2 Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start This is because counting TM0n is started asynchronously to the count pulse Figure 7 60 Start ...

Page 242: ...lue of CR00n CR01n after INTTM00n INTTM01n is generated Figure 7 61 Timing of Holding Data by Capture Register N N 1 N 2 X N 1 M M 1 M 2 Count pulse TM0n count value Edge input INTTM01n Value captured to CR01n Capture read signal Capture operation is performed but read value is not guaranteed Capture operation b The values of CR00n and CR01n are not guaranteed after 16 bit timer event counter 0n s...

Page 243: ...FEH FFFFH FFFFH 0000H 0001H Count pulse TM0n INTTM00n OVF0n CR00n b Clearing OVF0n flag Even if the OVF0n flag is cleared to 0 after TM0n overflows and before the next count clock is counted before the value of TM0n becomes 0001H it is set to 1 again and clearing is invalid 8 One shot pulse output One shot pulse output operates correctly in the free running timer mode or the clear start mode enter...

Page 244: ...00n signal is generated as an external interrupt signal Mask the INTTM00n signal when the external interrupt is not used 10 Edge detection a Specifying valid edge after reset If the operation of the 16 bit timer event counter 0n is enabled after reset and while the TI00n or TI01n pin is at high level and when the rising edge or both the edges are specified as the valid edge of the TI00n or TI01n p...

Page 245: ...imer event counters 50 and 51 include the following hardware Table 8 1 Configuration of 8 Bit Timer Event Counters 50 and 51 Item Configuration Timer register 8 bit timer counter 5n TM5n Register 8 bit timer compare register 5n CR5n Timer input TI5n Timer output TO5n Control registers Timer clock selection register 5n TCL5n 8 bit timer mode control register 5n TMC5n Port mode register 1 PM1 or por...

Page 246: ...ART6 INTTM50 TO50 TI50 P17 Note 1 Note 2 Selector 8 bit timer counter 50 TM50 Selector Output latch P17 PM17 fPRS 22 fPRS 28 fPRS 26 Figure 8 2 Block Diagram of 8 Bit Timer Event Counter 51 Internal bus 8 bit timer compare register 51 CR51 TI51 TO51 P33 INTP4 fPRS 212 fPRS fPRS 2 Match Mask circuit OVF 3 Clear TCL512 TCL511 TCL510 Timer clock selection register 51 TCL51 Internal bus TCE51 TMC516 L...

Page 247: ... CR5n CR5n can be read and written by an 8 bit memory manipulation instruction Except in PWM mode the value set in CR5n is constantly compared with the 8 bit timer counter 5n TM5n count value and an interrupt request INTTM5n is generated if they match In the PWM mode the TO5n pin becomes inactive when the values of TM5n and CR5n match but no interrupt is generated The value of CR5n can be set with...

Page 248: ...tion instruction Reset signal generation sets TCL5n to 00H Remark n 0 1 Figure 8 5 Format of Timer Clock Selection Register 50 TCL50 Address FF6AH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 TCL50 0 0 0 0 0 TCL502 TCL501 TCL500 Count clock selection TCL502 TCL501 TCL500 fPRS 2 MHz fPRS 5 MHz fPRS 10 MHz fPRS 20 MHz 0 0 0 TI50 pin falling edge 0 0 1 TI50 pin rising edge 0 1 0 fPRS 2 MHz 5 MHz 10 MHz...

Page 249: ...z fPRS 20 MHz 0 0 0 TI51 pin falling edge 0 0 1 TI51 pin rising edge 0 1 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz 0 1 1 fPRS 2 1 MHz 2 5 MHz 5 MHz 10 MHz 1 0 0 fPRS 2 4 125 kHz 312 5 kHz 625 kHz 1 25 MHz 1 0 1 fPRS 2 6 31 25 kHz 78 13 kHz 156 25 kHz 312 5 kHz 1 1 0 fPRS 2 8 7 81 kHz 19 53 kHz 39 06 kHz 78 13 kHz 1 1 1 fPRS 2 12 0 49 kHz 1 22 kHz 2 44 kHz 4 88 kHz Cautions 1 When rewriting TCL51 to other d...

Page 250: ...Symbol 7 6 5 4 3 2 1 0 TMC50 TCE50 TMC506 0 0 LVS50 LVR50 TMC501 TOE50 TCE50 TM50 count operation control 0 After clearing to 0 count operation disabled counter stopped 1 Count operation start TMC506 TM50 operating mode selection 0 Mode in which clear start occurs on a match between TM50 and CR50 1 PWM free running mode LVS50 LVR50 Timer output F F status setting 0 0 No change 0 1 Timer output F F...

Page 251: ...1 1 Setting prohibited In other modes TMC516 0 In PWM mode TMC516 1 TMC511 Timer F F control Active level selection 0 Inversion operation disabled Active high 1 Inversion operation enabled Active low TOE51 Timer output control 0 Output disabled TM51 output is low level 1 Output enabled Note Bits 2 and 3 are write only Cautions 1 The settings of LVS5n and LVR5n are valid in other than PWM mode 2 Pe...

Page 252: ... and P33 at this time may be 0 or 1 PM1 and PM3 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets these registers to FFH Figure 8 9 Format of Port Mode Register 1 PM1 Address FF21H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I O mode selection n 0 to 7 0 Output mode output buffer on 1 Input mode outpu...

Page 253: ...et the registers TCL5n Select the count clock CR5n Compare value TMC5n Stop the count operation select the mode in which clear start occurs on a match of TM5n and CR5n TMC5n 0000 0B Don t care 2 After TCE5n 1 is set the count operation starts 3 If the values of TM5n and CR5n match INTTM5n is generated TM5n is cleared to 00H 4 INTTM5n is generated repeatedly at the same interval Set TCE5n to 0 to s...

Page 254: ...e 8 11 Interval Timer Operation Timing 2 2 b When CR5n 00H t Interval time Count clock TM5n CR5n TCE5n INTTM5n 00H 00H 00H 00H 00H c When CR5n FFH t Count clock TM5n CR5n TCE5n INTTM5n 01H FEH FFH 00H FEH FFH 00H FFH FFH FFH Interval time Interrupt acknowledged Interrupt acknowledged Remark n 0 1 ...

Page 255: ...to 1 TCL5n Select TI5n pin input edge TI5n pin falling edge TCL5n 00H TI5n pin rising edge TCL5n 01H CR5n Compare value TMC5n Stop the count operation select the mode in which clear start occurs on match of TM5n and CR5n disable the timer F F inversion operation disable timer output TMC5n 0000 00B Don t care 2 When TCE5n 1 is set the number of pulses input from the TI5n pin is counted 3 When the v...

Page 256: ... operation select the mode in which clear start occurs on a match of TM5n and CR5n LVS5n LVR5n Timer Output F F Status Setting 1 0 Timer output F F clear 0 default output value of TO50 pin low level 0 1 Timer output F F set 1 default output value of TO5n pin high level Timer output enabled TMC5n 00001011B or 00000111B 2 After TCE5n 1 is set the count operation starts 3 The timer output F F is inve...

Page 257: ...5n operates as a PWM output when bit 6 TMC5n6 of 8 bit timer mode control register 5n TMC5n is set to 1 The duty pulse determined by the value set to 8 bit timer compare register 5n CR5n is output from TO5n Set the active level width of the PWM pulse to CR5n the active level can be selected with bit 1 TMC5n1 of TMC5n The count clock can be selected with bits 0 to 2 TCL5n0 to TCL5n2 of timer clock ...

Page 258: ...operation Note 8 bit timer event counter 50 P17 PM17 8 bit timer event counter 51 P33 PM33 PWM output operation 1 PWM output output from TO5n outputs an inactive level until an overflow occurs 2 When an overflow occurs the active level is output The active level is output until CR5n matches the count value of 8 bit timer counter 5n TM5n 3 After the CR5n matches the count value the inactive level i...

Page 259: ...level 3 Inactive level 5 Inactive level t 2 Active level b CR5n 00H Count clock TM5n CR5n TCE5n INTTM5n 01H 00H FFH 00H 01H 02H 00H FFH 00H 01H 02H M 00H TO5n L Inactive level t c CR5n FFH TM5n CR5n TCE5n INTTM5n TO5n 01H 00H FFH 00H 01H 02H FFH 1 Inactive level 2 Active level FFH 00H 01H 02H M 00H 3 Inactive level 2 Active level 5 Inactive level t Remarks 1 1 to 3 and 5 in Figure 8 14 a correspon...

Page 260: ...lock TM5n CR5n TCE5n INTTM5n TO5n 1 CR5n change N M N N 1 N 2 FFH 00H 01H M M 1 M 2 FFH 00H 01H 02H M M 1 M 2 N 02H M H 2 t b CR5n value is changed from N to M after clock rising edge of FFH Value is transferred to CR5n at second overflow Count clock TM5n CR5n TCE5n INTTM5n TO5n N N 1 N 2 FFH 00H 01H N N 1 N 2 FFH 00H 01H 02H N 02H N H M M M 1 M 2 1 CR5n change N M 2 t Caution When reading from CR...

Page 261: ...er start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start This is because 8 bit timer counters 50 and 51 TM50 TM51 are started asynchronously to the count clock Figure 8 16 8 Bit Timer Counter 5n Start Timing Count clock TM5n count value 00H 01H 02H 03H 04H Timer start Remark n 0 1 ...

Page 262: ...s H0 and H1 include the following hardware Table 9 1 Configuration of 8 Bit Timers H0 and H1 Item Configuration Timer register 8 bit timer counter Hn Registers 8 bit timer H compare register 0n CMP0n 8 bit timer H compare register 1n CMP1n Timer output TOHn output controller Control registers 8 bit timer H mode register n TMHMDn 8 bit timer H carrier control register 1 TMCYC1 Note Port mode regist...

Page 263: ...PRS fPRS 2 fPRS 22 fPRS 26 fPRS 210 1 0 F F R 3 2 PM15 Match Internal bus 8 bit timer H mode register 0 TMHMD0 8 bit timer H compare register 10 CMP10 Decoder Selector Interrupt generator Output controller Level inversion PWM mode signal Timer H enable signal Clear 8 bit timer H compare register 00 CMP00 Output latch P15 8 bit timer event counter 50 output Selector 8 bit timer counter H0 ...

Page 264: ...5 P16 8 bit timer H carrier control register 1 TMCYC1 INTTMH1 INTTM51 Selector fPRS fPRS 22 fPRS 24 fPRS 26 fPRS 212 fRL fRL 27 fRL 29 Interrupt generator Output controller Level inversion PM16 Output latch P16 1 0 F F R PWM mode signal Carrier generator mode signal Timer H enable signal 3 2 8 bit timer H compare register 01 CMP01 8 bit timer counter H1 Clear RMC1 NRZB1 NRZ1 Reload interrupt contr...

Page 265: ... bit timer counter Hn and when the two values match inverts the output level of TOHn No interrupt request signal is generated In the carrier generator mode the CMP1n register always compares the value set to CMP1n with the count value of the 8 bit timer counter Hn and when the two values match generates an interrupt request signal INTTMHn At the same time the count value is cleared CMP1n can be re...

Page 266: ...H0 and H1 8 bit timer H mode register n TMHMDn 8 bit timer H carrier control register 1 TMCYC1 Note Port mode register 1 PM1 Port register 1 P1 Note 8 bit timer H1 only 1 8 bit timer H mode register n TMHMDn This register controls the mode of timer H This register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets this register to 00H Remark n 0 1 ...

Page 267: ...0 1 TMMD00 0 0 Timer operation mode Low level High level TOLEV0 0 1 Timer output level control in default mode Disables output Enables output TOEN0 0 1 Timer output control Other than above 7 6 5 4 3 2 1 0 fPRS 5 MHz 5 MHz 2 5 MHz 1 25 MHz 78 13 kHz 4 88 kHz fPRS 10 MHz 10 MHz 5 MHz 2 5 MHz 156 25 kHz 9 77 kHz fPRS 20 MHz 20 MHz 10 MHz 5 MHz 312 5 kHz 19 54 kHz Note Note the following points when ...

Page 268: ...utput mode be sure to set the 8 bit timer H compare register 10 CMP10 when starting the timer count operation TMHE0 1 after the timer count operation was stopped TMHE0 0 be sure to set again even if setting the same value to CMP10 Remarks 1 fPRS Peripheral hardware clock frequency 2 TMC506 Bit 6 of 8 bit timer mode control register 50 TMC50 TMC501 Bit 1 of TMC50 ...

Page 269: ... 0 0 0 0 1 1 1 1 CKS11 0 0 1 1 0 0 1 1 CKS10 0 1 0 1 0 1 0 1 fPRS 2 MHz 2 MHz 500 kHz 125 kHz 31 25 kHz 0 49 kHz 1 88 kHz TYP 0 47 kHz TYP 240 kHz TYP Count clock selection fPRS 5 MHz 5 MHz 1 25 MHz 312 5 kHz 78 13 kHz 1 22 kHz fPRS 10 MHz 10 MHz 2 5 MHz 625 kHz 156 25 kHz 2 44 kHz fPRS 20 MHz 20 MHz 5 MHz 1 25 MHz 312 5 kHz 4 88 kHz Cautions 1 When TMHE1 1 setting the other bits of TMHMD1 is proh...

Page 270: ...emote control output Carrier output disabled status low level status Carrier output enabled status RMC1 1 Carrier pulse output RMC1 0 High level status NRZ1 0 1 Carrier pulse output status flag 0 Note Bit 0 is read only 3 Port mode register 1 PM1 This register sets port 1 input output in 1 bit units When using the P15 TOH0 and P16 TOH1 INTP5 pins for timer output clear PM15 and PM16 and the output...

Page 271: ...etting During Interval Timer Square Wave Output Operation i Setting timer H mode register n TMHMDn 0 0 1 0 1 0 1 0 0 0 1 0 1 TMMDn0 TOLEVn TOENn CKSn1 CKSn2 TMHEn TMHMDn CKSn0 TMMDn1 Timer output setting Default setting of timer output level Interval timer mode setting Count clock fCNT selection Count operation stopped ii CMP0n register setting The interval time is as follows if N is set as a comp...

Page 272: ...n clear 3 1 1 The count operation is enabled by setting the TMHEn bit to 1 The count clock starts counting no more than 1 clock after the operation is enabled 2 When the value of the 8 bit timer counter Hn matches the value of the CMP0n register the value of the timer counter is cleared and the level of the TOHn output is inverted In addition the INTTMHn signal is output at the rising edge of the ...

Page 273: ... Wave Output Operation 2 2 b Operation when CMP0n FFH 00H Count clock Count start 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn 01H FEH Clear Clear FFH 00H FEH FFH 00H FFH Interval time c Operation when CMP0n 00H Count clock Count start 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn 00H 00H Interval time Remark n 0 1 ...

Page 274: ... TMMDn0 TOLEVn TOENn CKSn1 CKSn2 TMHEn TMHMDn CKSn0 TMMDn1 Timer output enabled Default setting of timer output level PWM output mode selection Count clock fCNT selection Count operation stopped ii Setting CMP0n register Compare value N Cycle setting iii Setting CMP1n register Compare value M Duty setting Remarks 1 n 0 1 2 00H CMP1n M CMP0n N FFH 2 The count operation starts when TMHEn 1 3 The CMP...

Page 275: ...this takes a duration of three operating clocks signal selected by the CKSn2 to CKSn0 bits of the TMHMDn register from when the value of the CMP1n register is changed until the value is transferred to the register 2 Be sure to set the CMP1n register when starting the timer count operation TMHEn 1 after the timer count operation was stopped TMHEn 0 be sure to set again even if setting the same valu...

Page 276: ...sking one count clock to count up At this time TOHn output remains the default 2 When the values of the 8 bit timer counter Hn and the CMP0n register match the TOHn output level is inverted the value of the 8 bit timer counter Hn is cleared and the INTTMHn signal is output 3 When the values of the 8 bit timer counter Hn and the CMP1n register match the TOHn output level is inverted At this time th...

Page 277: ... when CMP0n FFH CMP1n 00H Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 00H 01H FFH 00H 01H 02H FFH 00H FFH 00H 01H 02H CMP1n FFH 00H c Operation when CMP0n FFH CMP1n FEH Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H CMP1n FFH FEH Remark n 0 1 ...

Page 278: ...r s Manual U17260EJ3V1UD 278 Figure 9 12 Operation Timing in PWM Output Mode 3 4 d Operation when CMP0n 01H CMP1n 00H Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 01H 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP1n 00H Remark n 0 1 ...

Page 279: ...9 Figure 9 12 Operation Timing in PWM Output Mode 4 4 e Operation by changing CMP1n CMP1n 02H 03H CMP0n A5H Count clock 8 bit timer counter Hn CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H 1 4 3 2 CMP11 6 5 02H A5H 03H 02H 03H 2 ...

Page 280: ...d the carrier pulse is output from the TOH1 output 1 Carrier generation In carrier generator mode the 8 bit timer H compare register 01 CMP01 generates a low level width carrier pulse waveform and the 8 bit timer H compare register 11 CMP11 generates a high level width carrier pulse waveform Rewriting the CMP11 register during the 8 bit timer H1 operation is possible but rewriting the CMP01 regist...

Page 281: ...TTM51 signal is synchronized with the count clock of the 8 bit timer H1 and is output as the INTTM5H1 signal 2 The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the INTTM5H1 signal 3 Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the INTTM5H1 interrupt or after timing has been checked by polling ...

Page 282: ... of the 8 bit timer counter H1 and the CMP01 register value match the INTTMH1 signal is generated the 8 bit timer counter H1 is cleared At the same time the compare register to be compared with the 8 bit timer counter H1 is switched from the CMP01 register to the CMP11 register 5 When the count value of the 8 bit timer counter H1 and the CMP11 register value match the INTTMH1 signal is generated t...

Page 283: ...CHAPTER 9 8 BIT TIMERS H0 AND H1 Preliminary User s Manual U17260EJ3V1UD 283 10 By performing the procedures above an arbitrary carrier ...

Page 284: ...ode Operation Timing 1 3 a Operation when CMP01 N CMP11 N CMP01 CMP11 TMHE11 INTTMH1 Carrier clock 00H N 00H N 00H N 00H N 00H N 00H N N N 8 bit timer 51 count clock TM51 count value CR51 TCE51 TOH11 0 0 1 1 0 0 1 1 0 0 INTTM5n1 NRZB1 NRZ1 Carrier clock 00H 01H K 00H 01H L 00H 01H M 00H 01H 00H 01H N INTTM5H1 ...

Page 285: ...is inverted and the compare register to be compared with the 8 bit timer counter H1 is switched from the CMP01 register to the CMP11 register The 8 bit timer counter H1 is cleared to 00H 4 When the count value of the 8 bit timer counter H1 matches the CMP11 register value the INTTMH1 signal is generated the carrier clock signal is inverted and the compare register to be compared with the 8 bit tim...

Page 286: ...be changed while the 8 bit timer H1 is operating The new value L to which the value of the register is to be changed is latched When the count value of the 8 bit timer counter H1 matches the value M of the CMP11 register before the change the CMP11 register is changed 3 However it takes three count clocks or more since the value of the CMP11 register has been changed until the value is transferred...

Page 287: ... block diagram Figure 10 1 Block Diagram of Watch Timer fPRS 27 fW 24 fW 25 fW 26 fW 27 fW 28 fW 210 fW 211 fW 29 fSUB INTWT INTWTI WTM0 WTM1 WTM2 WTM3 WTM4 WTM5 WTM6 WTM7 fW Clear 11 bit prescaler Clear 5 bit counter Watch timer operation mode register WTM Internal bus Selector Selector Selector Selector fWX 24 fWX 25 fWX Remark fPRS Peripheral hardware clock frequency fSUB Subsystem clock freque...

Page 288: ...re generated at preset time intervals Table 10 2 Interval Timer Interval Time Interval Time When Operated at fSUB 32 768 kHz When Operated at fPRS 2 MHz When Operated at fPRS 5 MHz When Operated at fPRS 10 MHz When Operated at fPRS 20 MHz 2 4 fW 488 µs 1 02 ms 410 µs 205 µs 102 µs 2 5 fW 977 µs 2 05 ms 820 µs 410 µs 205 µs 2 6 fW 1 95 ms 4 10 ms 1 64 ms 820 µs 410 µs 2 7 fW 3 91 ms 8 20 ms 3 28 ms...

Page 289: ...r WTM Address FF6FH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 WTM WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 Watch timer count clock selection fW WTM7 fSUB 32 768 kHz fPRS 2 MHz fPRS 5 MHz fPRS 10 MHz fPRS 20 MHz 0 fPRS 2 7 15 625 kHz 39 062 kHz 78 125 kHz 156 25 kHz 1 fSUB 32 768 kHz WTM6 WTM5 WTM4 Prescaler interval time selection 0 0 0 2 4 fW 0 0 1 2 5 fW 0 1 0 2 6 fW 0 1 1 2 7 fW 1 0 0 2 8 fW 1 ...

Page 290: ...290 Caution Do not change the count clock and interval time by setting bits 4 to 7 WTM4 to WTM7 of WTM during watch timer operation Remarks 1 fW Watch timer clock frequency fPRS 2 7 or fSUB 2 fPRS Peripheral hardware clock frequency 3 fSUB Subsystem clock frequency ...

Page 291: ...5 ms 819 µs 410 µs 205 µs 1 1 2 4 fW 488 µs 1 02 ms 410 µs 205 µs 102 µs Remarks 1 fW Watch timer clock frequency fPRS 2 7 or fSUB 2 fPRS Peripheral hardware clock frequency 3 fSUB Subsystem clock frequency 10 4 2 Interval timer operation The watch timer operates as interval timer which generates interrupt request signals INTWTI repeatedly at an interval of the preset count value The interval time...

Page 292: ...peration of the watch timer and 5 bit counter is enabled by the watch timer mode control register WTM by setting bits 0 WTM0 and 1 WTM1 of WTM to 1 the interval until the first interrupt request signal INTWT is generated after the register is set does not exactly match the specification made with bits 2 and 3 WTM2 WTM3 of WTM Subsequently however the INTWT signal is generated at the specified inte...

Page 293: ...executed on the watchdog timer enable register WDTE If data other than ACH is written to WDTE If data is written to WDTE during a window close period If the instruction is fetched from an area not set by the IMS and IXS registers detection of an invalid check while the CPU hangs up If the CPU accesses an area that is not set by the IMS and IXS registers excluding FB00H to FFFFH by executing a read...

Page 294: ...080H Window open period Bits 6 and 5 WINDOW1 WINDOW0 Controlling counter operation of watchdog timer Bit 4 WDTON Overflow time of watchdog timer Bits 3 to 1 WDCS2 to WDCS0 Remark For the option byte see CHAPTER 25 OPTION BYTE Figure 11 1 Block Diagram of Watchdog Timer fRL 2 Clock input controller Reset output controller Internal reset signal Internal bus Selector 17 bit counter 210 fRL to 217 fRL...

Page 295: ...e WDTON setting value of the option byte 0080H To operate watchdog timer set WDTON to 1 WDTON Setting Value WDTE Reset Value 0 watchdog timer count operation disabled 1AH 1 watchdog timer count operation enabled 9AH Cautions 1 If a value other than ACH is written to WDTE an internal reset signal is generated If the source clock to the watchdog timer is stopped however an internal reset signal is g...

Page 296: ... the watchdog timer is cleared and starts counting again 4 After that write WDTE the second time or later after a reset release during the window open period If WDTE is written during a window close period an internal reset signal is generated 5 If the overflow time expires without ACH written to WDTE an internal reset signal is generated A internal reset signal is generated in the following cases...

Page 297: ...acknowledge time is delayed Set the overflow time and window size taking this delay into consideration 11 4 2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by using bits 3 to 1 WDCS2 to WDCS0 of the option byte 0080H If an overflow occurs an internal reset signal is generated The present count is cleared and the watchdog timer starts counting again by writing ...

Page 298: ... time Counting starts again when ACH is written to WDTE Internal reset signal is generated if ACH is written to WDTE Caution The first writing to WDTE after a reset release clears the watchdog timer if it is made before the overflow time regardless of the timing of the writing and the watchdog timer starts counting again The window open period to be set is as follows Table 11 4 Setting Window Open...

Page 299: ...indow close time 0 to 3 56 ms 0 to 2 37 ms 0 to 0 119 ms None Window open time 3 56 to 3 88 ms 2 37 to 3 88 ms 0 119 to 3 88 ms 0 to 3 88 ms When window open period is 25 Overflow time 210 fRL MAX 2 10 264 kHz MAX 3 88 ms Window close time 0 to 210 fRL MIN 1 0 25 0 to 2 10 216 kHz MIN 0 75 0 to 3 56 ms Window open time 210 fRL MIN 1 0 25 to 2 10 fRL MAX 2 10 216 kHz MIN 0 75 to 2 10 264 kHz MAX 3 ...

Page 300: ...ut during remote controlled transmission and clock output for supply to peripheral ICs The clock selected with the clock output selection register CKS is output In addition the buzzer output is intended for square wave output of buzzer frequency selected with CKS Figure 12 1 shows the block diagram of clock output buzzer output controller Figure 12 1 Block Diagram of Clock Output Buzzer Output Con...

Page 301: ...ion register CKS Port mode register 14 PM14 Port register 14 P14 12 3 Registers Controlling Clock Output Buzzer Output Controller The following two registers are used to control the clock output buzzer output controller Clock output selection register CKS Port mode register 14 PM14 1 Clock output selection register CKS This register sets output enable disable for clock output PCL and for the buzze...

Page 302: ...ration enabled PCL output enabled PCL output clock selection CCS3 CCS2 CCS1 CCS0 fSUB 32 768 kHz fPRS 10 MHz fPRS 20 MHz 0 0 0 0 fPRS Note 1 10 MHz Setting prohibited Note 2 0 0 0 1 fPRS 2 5 MHz 10 MHz 0 0 1 0 fPRS 2 2 2 5 MHz 5 MHz 0 0 1 1 fPRS 2 3 1 25 MHz 2 5 MHz 0 1 0 0 fPRS 2 4 625 kHz 1 25 MHz 0 1 0 1 fPRS 2 5 312 5 kHz 625 kHz 0 1 1 0 fPRS 2 6 156 25 kHz 312 5 kHz 0 1 1 1 fPRS 2 7 78 125 kH...

Page 303: ...on as clock output The clock pulse is output as the following procedure 1 Select the clock pulse output frequency with bits 0 to 3 CCS0 to CCS3 of the clock output selection register CKS clock pulse output in disabled status 2 Set bit 4 CLOE of CKS to 1 to enable clock output Remark The clock output controller is designed not to output pulses with a small width during output enable disable switchi...

Page 304: ...annel selected from ANI0 to ANI7 Each time an A D conversion operation ends an interrupt request INTAD is generated Figure 13 1 Block Diagram of A D Converter AVREF AVSS INTAD ADCS bit ADCS FR2 FR1 ADCE FR0 Sample hold circuit AVSS Voltage comparator A D converter mode register ADM Internal bus 3 ADS2 ADS1 ADS0 Analog input channel specification register ADS ANI0 P20 ANI1 P21 ANI2 P22 ANI3 P23 ANI...

Page 305: ...ed with the sampled voltage value Figure 13 2 Circuit Configuration of Series Resistor String ADCS Series resistor string AVREF P ch AVSS 4 Voltage comparator The voltage comparator compares the sampled voltage value and the output voltage of the series resistor string 5 Successive approximation register SAR This register converts the result of comparison by the voltage comparator starting from th...

Page 306: ...REF pin This pin inputs an analog power reference voltage to the A D converter Make this pin the same potential as the VDD pin when port 2 is used as a digital port The signal input to ANI0 to ANI7 is converted into a digital signal based on the voltage applied across AVREF and AVSS 10 AVSS pin This is the ground potential pin of the A D converter Always use this pin at the same potential as that ...

Page 307: ... 0 1 0 1 2 3 4 5 6 7 ADM Address FF28H After reset 00H R W Symbol Comparator operation controlNote 2 Stops comparator operation Enables comparator operation comparator 1 2AVREF operation ADCE 0 1 Notes 1 For details of FR2 to FR0 LV1 LV0 and A D conversion see Table 13 2 A D Conversion Time Selection 2 The operation of the comparator is controlled by ADCS and ADCE and it takes 1 µs from operation ...

Page 308: ...bilize the internal circuit the time from the rising of the ADCE bit to the falling of the ADCS bit must be 1 µs or longer Cautions 1 A D conversion must be stopped before rewriting bits FR0 to FR2 LV1 and LV0 to values other than the identical data 2 If data is written to ADM a wait cycle is generated Do not write data to ADM when the CPU is operating on the subsystem clock and the peripheral har...

Page 309: ... MHz fPRS 5 MHz Conversion Clock fAD SAR Clear Sampling Successive Conversion Time ADCR Transfer INTAD Generation 0 0 0 0 1 480 fPRS Setting prohibited fPRS 12 0 0 1 0 1 320 fPRS 64 0 µs fPRS 8 0 1 0 0 1 240 fPRS 48 0 µs fPRS 6 0 1 1 0 1 160 fPRS Setting prohibited 32 0 µs fPRS 4 1 0 0 0 1 120 fPRS 60 0 µs Setting prohibited fPRS 3 1 0 1 0 1 80 fPRS 40 0 µs Setting prohibited fPRS 2 2 fAD 24 fAD 1...

Page 310: ...FF09H and the lower 2 bits are stored in the higher 2 bits of FF08H ADCR can be read by a 16 bit memory manipulation instruction Reset signal generation sets this register to 0000H Figure 13 6 Format of 10 Bit A D Conversion Result Register ADCR Symbol Address FF08H FF09H After reset 0000H R FF09H FF08H 0 0 0 0 0 0 ADCR Cautions 1 When writing to the A D converter mode register ADM analog input ch...

Page 311: ...FF09H After reset 00H R 7 6 5 4 3 2 1 0 Cautions 1 When writing to the A D converter mode register ADM analog input channel specification register ADS and A D port configuration register ADPC the contents of ADCRH may become undefined Read the conversion result following conversion completion before writing to ADM ADS and ADPC Using timing other than the above may cause an incorrect conversion res...

Page 312: ... input channel specification ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ADS0 0 1 0 1 0 1 0 1 ADS1 0 0 1 1 0 0 1 1 ADS2 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 ADS Address FF29H After reset 00H R W Symbol Cautions 1 Be sure to clear bits 3 to 7 to 0 2 Set a channel to be used for A D conversion in the input mode by using port mode register 2 PM2 3 Do not set a pin to be used as a digital I O pin with ADPC wit...

Page 313: ...t 00H R W Symbol ANI7 P27 A A A A A A A A D ANI6 P26 A A A A A A A D D ANI5 P25 A A A A A A D D D ANI4 P24 A A A A A D D D D ANI3 P23 A A A A D D D D D ANI2 P22 A A A D D D D D D ANI1 P21 A A D D D D D D D ANI0 P20 A D D D D D D D D 0 0 0 0 0 0 0 0 1 ADPC2 0 0 0 0 1 1 1 1 0 ADPC1 0 0 1 1 0 0 1 1 0 ADPC0 0 1 0 1 0 1 0 1 0 Other than above Cautions 1 Set a channel to be used for A D conversion in th...

Page 314: ...27 P2n pin I O mode selection n 0 to 7 Output mode output buffer on Input mode output buffer off PM2n 0 1 0 1 2 3 4 5 6 7 PM2 Address FF22H After reset FFH R W Symbol ANI0 P20 to ANI7 P27 pins are as shown below depending on the settings of ADPC ADS and PM2 Table 13 3 Setting Functions of ANI0 P20 to ANI7 P27 Pins ADPC PM2 ADS ANI0 P20 to ANI7 P27 Pin Selects ANI Analog input to be converted Input...

Page 315: ...ator If the analog input is greater than 1 2 AVREF the MSB of SAR remains set to 1 If the analog input is smaller than 1 2 AVREF the MSB is reset to 0 10 Next bit 8 of SAR is automatically set to 1 and the operation proceeds to the next comparison The series resistor string voltage tap is selected according to the preset value of bit 9 as described below Bit 9 1 3 4 AVREF Bit 9 0 1 4 AVREF The vol...

Page 316: ... D conversion operations are performed continuously until bit 7 ADCS of the A D converter mode register ADM is reset 0 by software If a write operation is performed to the analog input channel specification register ADS during an A D conversion operation the conversion operation is initialized and if the ADCS bit is set 1 conversion starts again from the beginning Reset signal generation sets the ...

Page 317: ...turns integer part of value in parentheses VAIN Analog input voltage AVREF AVREF pin voltage ADCR A D conversion result register ADCR value SAR Successive approximation register Figure 13 12 shows the relationship between the analog input voltage and the A D conversion result Figure 13 12 Relationship Between Analog Input Voltage and A D Conversion Result 1023 1022 1021 3 2 1 0 FFC0H FF80H FF40H 0...

Page 318: ...f the A D conversion is stored in the A D conversion result register ADCR and an interrupt request signal INTAD is generated When one A D conversion has been completed the next A D conversion operation is immediately started If ADS is rewritten during A D conversion the A D conversion operation under execution is stopped and restarted from the beginning If 0 is written to ADCS during A D conversio...

Page 319: ...en completed an interrupt request signal INTAD is generated 7 Transfer the A D conversion data to the A D conversion result register ADCR ADCRH Change the channel 8 Change the channel using bits 2 to 0 ADS2 to ADS0 of ADS to start A D conversion 9 When one A D conversion has been completed an interrupt request signal INTAD is generated 10 Transfer the A D conversion data to the A D conversion resu...

Page 320: ... the overall error in the characteristics table 3 Quantization error When analog values are converted to digital values a 1 2LSB error naturally occurs In an A D converter an analog input voltage in a range of 1 2LSB is converted to the same digital code so a quantization error cannot be avoided Note that the quantization error is not included in the overall error zero scale error full scale error...

Page 321: ... value and the ideal value Figure 13 16 Zero Scale Error Figure 13 17 Full Scale Error 111 011 010 001 Zero scale error Ideal line 000 0 1 2 3 AVREF Digital output Lower 3 bits Analog input LSB 111 110 101 000 0 AVREF 3 Full scale error Ideal line Analog input LSB Digital output Lower 3 bits AVREF 2 AVREF 1 AVREF Figure 13 18 Integral Linearity Error Figure 13 19 Differential Linearity Error 0 AVR...

Page 322: ...rite and ADCR or ADCRH read by instruction upon the end of conversion ADCR or ADCRH read has priority After the read operation the new conversion result is written to ADCR or ADCRH 2 Conflict between ADCR or ADCRH write and A D converter mode register ADM write analog input channel specification register ADS or A D port configuration register ADPC write upon the end of conversion ADM ADS or ADPC w...

Page 323: ...ersion may not be obtained due to coupling noise Therefore do not apply a pulse to the pins adjacent to the pin undergoing A D conversion 6 Input impedance of ANI0 to ANI7 pins This A D converter charges a sampling capacitor for sampling during sampling time Therefore only a leakage current flows when sampling is not in progress and a current that charges the capacitor flows during sampling Conseq...

Page 324: ...ADIF ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm ADS rewrite start of ANIm conversion ADIF is set but ANIm conversion has not ended Remarks 1 n 0 to 7 2 m 0 to 7 9 Conversion results just after A D conversion start The first A D conversion value immediately after A D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 µs after the ADCE bit was set to 1 or if the...

Page 325: ...re 13 22 Internal Equivalent Circuit of ANIn Pin ANIn C1 C2 R1 Table 13 4 Resistance and Capacitance Values of Equivalent Circuit Reference Values AVREF R1 C1 C2 4 0 V AVREF 5 5 V 8 1 kΩ 8 pF 5 pF 2 7 V AVREF 4 0 V 31 kΩ 8 pF 5 pF 2 3 V AVREF 2 7 V 381 kΩ 8 pF 5 pF Remarks 1 The resistance and capacitance values shown in Table 13 4 are not guaranteed values 2 n 0 to 7 ...

Page 326: ...ex operation Fixed to LSB first communication Cautions 1 If clock supply to serial interface UART0 is not stopped e g in the HALT mode normal operation continues If clock supply to serial interface UART0 is stopped e g in the STOP mode each register stops operating and holds the value immediately before clock supply was stopped The TXD0 pin also holds the value immediately before clock supply was ...

Page 327: ...iguration of Serial Interface UART0 Item Configuration Registers Receive buffer register 0 RXB0 Receive shift register 0 RXS0 Transmit shift register 0 TXS0 Control registers Asynchronous serial interface operation mode register 0 ASIM0 Asynchronous serial interface reception error status register 0 ASIS0 Baud rate generator control register 0 BRGC0 Port mode register 1 PM1 Port register 1 P1 ...

Page 328: ...ft register 0 RXS0 Receive buffer register 0 RXB0 Asynchronous serial interface reception error status register 0 ASIS0 Asynchronous serial interface operation mode register 0 ASIM0 Baud rate generator control register 0 BRGC0 8 bit timer event counter 50 output Registers Selector Baud rate generator Baud rate generator Reception unit Reception control Filter Internal bus Transmission control Tran...

Page 329: ...e written to this register Reset signal generation and POWER0 0 set this register to FFH 2 Receive shift register 0 RXS0 This register converts the serial data input to the RXD0 pin into parallel data RXS0 cannot be directly manipulated by a program 3 Transmit shift register 0 TXS0 This register is used to set transmit data Transmission is started when data is written to TXS0 and serial data is tr...

Page 330: ...re 14 2 Format of Asynchronous Serial Interface Operation Mode Register 0 ASIM0 1 2 Address FF70H After reset 01H R W Symbol 7 6 5 4 3 2 1 0 ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1 POWER0 Enables disables operation of internal operation clock 0 Note 1 Disables operation of the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit Note 2 1 Enables o...

Page 331: ...0 to 1 and then set TXE0 to 1 To stop the transmission clear TXE0 to 0 and then clear POWER0 to 0 2 To start the reception set POWER0 to 1 and then set RXE0 to 1 To stop the reception clear RXE0 to 0 and then clear POWER0 to 0 3 Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input reception is start...

Page 332: ...ad 1 If the parity of transmit data does not match the parity bit on completion of reception FE0 Status flag indicating framing error 0 If POWER0 0 and RXE0 0 or if ASIS0 register is read 1 If the stop bit is not detected on completion of reception OVE0 Status flag indicating overrun error 0 If POWER0 0 and RXE0 0 or if ASIS0 register is read 1 If receive data is set to the RXB0 register and the n...

Page 333: ...3 250 kHz 625 kHz 1 25 MHz 2 5 MHz 1 1 fPRS 2 5 62 5 kHz 156 25 kHz 312 5 kHz 625 kHz MDL04 MDL03 MDL02 MDL01 MDL00 k Selection of 5 bit counter output clock 0 0 Setting prohibited 0 1 0 0 0 8 fXCLK0 8 0 1 0 0 1 9 fXCLK0 9 0 1 0 1 0 10 fXCLK0 10 1 1 0 1 0 26 fXCLK0 26 1 1 0 1 1 27 fXCLK0 27 1 1 1 0 0 28 fXCLK0 28 1 1 1 0 1 29 fXCLK0 29 1 1 1 1 0 30 fXCLK0 30 1 1 1 1 1 31 fXCLK0 31 Note Note the fo...

Page 334: ...MC501 Bit 1 of TMC50 4 Port mode register 1 PM1 This register sets port 1 input output in 1 bit units When using the P10 TxD0 SCK10 pin for serial interface data output clear PM10 to 0 and set the output latch of P10 to 1 When using the P11 RxD0 SI10 pin for serial interface data input set PM11 to 1 The output latch of P11 at this time may be 0 or 1 PM1 can be set by a 1 bit or 8 bit memory manipu...

Page 335: ...mbol 7 6 5 4 3 2 1 0 ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1 POWER0 Enables disables operation of internal operation clock 0 Note 1 Disables operation of the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit Note 2 TXE0 Enables disables transmission 0 Disables transmission synchronously resets the transmission circuit RXE0 Enables disables rece...

Page 336: ...P1 The basic procedure of setting an operation in the UART mode is as follows 1 Set the BRGC0 register see Figure 14 4 2 Set bits 1 to 4 SL0 CL0 PS00 and PS01 of the ASIM0 register see Figure 14 2 3 Set bit 7 POWER0 of the ASIM0 register to 1 4 Set bit 6 TXE0 of the ASIM0 register to 1 Transmission is enabled Set bit 5 RXE0 of the ASIM0 register to 1 Reception is enabled 5 Write data to the TXS0 r...

Page 337: ... LSB first Parity bit Even parity odd parity 0 parity or no parity Stop bit 1 or 2 bits The character bit length parity and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 0 ASIM0 Figure 14 7 Example of Normal UART Transmit Receive Data Waveform 1 Data length 8 bits Parity Even parity Stop bit 1 bit Communication data 55H 1 data frame Start ...

Page 338: ...e receive data including the parity bit is counted If it is odd a parity error occurs ii Odd parity Transmission Unlike even parity transmit data including the parity bit is controlled so that the number of bits that are 1 is odd If transmit data has an odd number of bits that are 1 0 If transmit data has an even number of bits that are 1 1 Reception The number of bits that are 1 in the receive da...

Page 339: ...tarting from the LSB When transmission is completed the parity and stop bits set by ASIM0 are appended and a transmission completion interrupt request INTST0 is generated Transmission is stopped until the data to be transmitted next is written to TXS0 Figure 14 8 shows the timing of the transmission completion interrupt request INTST0 This interrupt occurs as soon as the last stop bit has been out...

Page 340: ...eception completion interrupt INTSR0 is generated and the data of RXS0 is written to receive buffer register 0 RXB0 If an overrun error OVE0 occurs however the receive data is not written to RXB0 Even if a parity error PE0 occurs while reception is in progress reception continues to the reception position of the stop bit and an reception error interrupt INTSR0 is generated after completion of rece...

Page 341: ...of Reception Error Reception Error Cause Parity error The parity specified for transmission does not match the parity of the receive data Framing error Stop bit is not detected Overrun error Reception of the next data is completed before data is read from receive buffer register 0 RXB0 f Noise filter of receive data The RXD0 signal is sampled using the base clock output by the prescaler block If t...

Page 342: ...to 0 when bit 7 POWER0 or bit 6 TXE0 of asynchronous serial interface operation mode register 0 ASIM0 is 0 It starts counting when POWER0 1 and TXE0 1 The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 TXS0 Reception counter This counter stops operation cleared to 0 when bit 7 POWER0 or bit 5 RXE0 of asynchronous serial interface operation mode regi...

Page 343: ...Baud rate The baud rate can be calculated by the following expression Baud rate bps fXCLK0 Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register k Value set by the MDL04 to MDL00 bits of the BRGC0 register k 8 9 10 31 b Error of baud rate The baud rate error can be calculated by the following expression Error 1 100 Cautions 1 Keep the baud rate error during transmissio...

Page 344: ...4000 1 21 23810 0 79 2 13 24038 0 16 2 26 24038 0 16 3 13 24038 0 16 31250 1 16 31250 0 2 10 31250 0 2 20 31250 0 3 10 31250 0 33660 1 15 33333 0 79 2 9 34722 3 34 2 18 34722 3 34 3 9 34722 3 34 38400 1 13 38462 0 16 2 8 39063 1 73 2 16 39063 1 73 3 8 39063 1 73 56000 1 9 55556 0 79 1 22 56818 1 46 2 11 56818 1 46 2 22 56818 1 46 62500 1 8 62500 0 1 20 62500 0 2 10 62500 0 2 20 62500 0 76800 1 16 ...

Page 345: ...tart bit Bit 0 Bit 1 Bit 7 Parity bit Minimum permissible data frame length Maximum permissible data frame length Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Latch timing Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 14 12 the latch timing of the receive data is determined by the counter set by baud rate generator control register 0 BRGC0 after the start bit has b...

Page 346: ... permissible baud rate error between UART0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions as follows Table 14 6 Maximum Minimum Permissible Baud Rate Error Division Ratio k Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 3 53 3 61 16 4 14 4 19 24 4 34 4 38 31 4 44 4 47 Remarks 1 The permissible error of receptio...

Page 347: ... this function the reception side must be ready for reception of inverted data 2 If clock supply to serial interface UART6 is not stopped e g in the HALT mode normal operation continues If clock supply to serial interface UART6 is stopped e g in the STOP mode each register stops operating and holds the value immediately before clock supply was stopped The TXD6 pin also holds the value immediately ...

Page 348: ...ors and these are connected to the LIN master via the LIN network Normally the LIN master is connected to a network such as CAN Controller Area Network In addition the LIN bus uses a single wire method and is connected to the nodes via a transceiver that complies with ISO9141 In the LIN protocol the master transmits a frame with baud rate information and the slave receives it and corrects the baud...

Page 349: ...the SBF reception end interrupt servicing and measure the bit interval pulse width of the sync field see 7 4 8 Pulse width measurement operation Detection of errors OVE6 PE6 and FE6 is suppressed and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed The shift register holds the reset value FFH 4 Calculate the baud rate error from the...

Page 350: ...elector Selector Selector Selector Port mode PM00 Output latch P00 Remark ISC0 ISC1 Bits 0 and 1 of the input switch control register ISC see Figure 15 11 The peripheral functions used in the LIN communication operation are shown below Peripheral functions used External interrupt INTP0 wakeup signal detection Use Detects the wakeup signal edges and detects start of communication 16 bit timer event...

Page 351: ...egister 6 RXS6 Transmit buffer register 6 TXB6 Transmit shift register 6 TXS6 Control registers Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface transmission status register 6 ASIF6 Clock selection register 6 CKSR6 Baud rate generator control register 6 BRGC6 Asynchronous serial interfa...

Page 352: ...RT6 Preliminary User s Manual U17260EJ3V1UD 352 Figure 15 4 Block Diagram of Serial Interface UART6 Internal bus Asynchronous serial interface control register 6 ASICL6 Transmit buffer register 6 TXB6 Transmit shift register 6 TXS6 ...

Page 353: ...ansmit buffer register 6 TXB6 This buffer register is used to set transmit data Transmission is started when data is written to TXB6 This register can be read or written by an 8 bit memory manipulation instruction Reset signal generation sets this register to FFH Cautions 1 Do not write data to TXB6 when bit 1 TXBF6 of asynchronous serial interface transmission status register 6 ASIF6 is 1 2 Do no...

Page 354: ...when bit 7 POWER6 and bit 6 TXE6 of ASIM6 1 or bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Figure 15 5 Format of Asynchronous Serial Interface Operation Mode Register 6 ASIM6 1 2 Address FF50H After reset 01H R W Symbol 7 6 5 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 Enables disables operation of internal operation clock 0 Note 1 Disables operation of the internal operation clock ...

Page 355: ... does not occur Cautions 1 To start the transmission set POWER6 to 1 and then set TXE6 to 1 To stop the transmission clear TXE6 to 0 and then clear POWER6 to 0 2 To start the reception set POWER6 to 1 and then set RXE6 to 1 To stop the reception clear RXE6 to 0 and then clear POWER6 to 0 3 Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RXD6 pin If POWER6 is set to 1 and ...

Page 356: ...read 1 If the parity of transmit data does not match the parity bit on completion of reception FE6 Status flag indicating framing error 0 If POWER6 0 and RXE6 0 or if ASIS6 register is read 1 If the stop bit is not detected on completion of reception OVE6 Status flag indicating overrun error 0 If POWER6 0 and RXE6 0 or if ASIS6 register is read 1 If receive data is set to the RXB6 register and the...

Page 357: ... POWER6 0 or TXE6 0 or if data is transferred to transmit shift register 6 TXS6 1 If data is written to transmit buffer register 6 TXB6 if data exists in TXB6 TXSF6 Transmit shift register data flag 0 If POWER6 0 or TXE6 0 or if the next data is not transferred from transmit buffer register 6 TXB6 after completion of transfer 1 If data is transferred from transmit buffer register 6 TXB6 if data tr...

Page 358: ... 125 kHz 312 5 kHz 625 kHz 1 25 MHz 0 1 0 1 fPRS 2 5 62 5 kHz 156 25 kHz 312 5 kHz 625 kHz 0 1 1 0 fPRS 2 6 31 25 kHz 78 13 kHz 156 25 kHz 312 5 kHz 0 1 1 1 fPRS 2 7 15 625 kHz 39 06 kHz 78 13 kHz 156 25 kHz 1 0 0 0 fPRS 2 8 7 813 kHz 19 53 kHz 39 06 kHz 78 13 kHz 1 0 0 1 fPRS 2 9 3 906 kHz 9 77 kHz 19 53 kHz 39 06 kHz 1 0 1 0 fPRS 2 10 1 953 kHz 4 88 kHz 9 77 kHz 19 53 kHz 1 0 1 1 TM50 output Not...

Page 359: ...ddress FF57H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8 bit counter 0 0 0 0 0 Setting prohibited 0 0 0 0 1 0 0 0 8 fXCLK6 8 0 0 0 0 1 0 0 1 9 fXCLK6 9 0 0 0 0 1 0 1 0 10 fXCLK6 10 1 1 1 1 1 1 0 0 252 fXCLK6 252 1 1 1 1 1 1 0 1 253 fXCLK6 253 1 1 1 1 1 1 1 0 254 fXCLK6...

Page 360: ...5 RXE6 of ASIM6 1 However do not set both SBRT6 and SBTT6 to 1 by a refresh operation during SBF reception SBRT6 1 or SBF transmission until INTST6 occurs since SBTT6 has been set 1 because it may re trigger SBF reception or SBF transmission Figure 15 10 Format of Asynchronous Serial Interface Control Register 6 ASICL6 1 2 Address FF58H After reset 16H R W Note Symbol 7 6 5 4 3 2 1 0 ASICL6 SBRF6 ...

Page 361: ...the SBF reception mode The status of the SBRF6 flag is held 1 2 Before setting the SBRT6 bit make sure that bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 After setting the SBRT6 bit to 1 do not clear it to 0 before SBF reception is completed before an interrupt request signal is generated 3 The read value of the SBRT6 bit is always 0 SBRT6 is automatically cleared to 0 after SBF reception has been correc...

Page 362: ...SC 0 0 0 0 0 0 ISC1 ISC0 ISC1 TI000 input source selection 0 TI000 P00 1 RXD6 P14 ISC0 INTP0 input source selection 0 INTP0 P120 1 RXD6 P14 8 Port mode register 1 PM1 This register sets port 1 input output in 1 bit units When using the P13 TXD6 pin for serial interface data output clear PM13 to 0 and set the output latch of P13 to 1 When using the P14 RXD6 pin for serial interface data input set P...

Page 363: ...disables operation of internal operation clock 0 Note 1 Disables operation of the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit Note 2 TXE6 Enables disables transmission 0 Disables transmission operation synchronously resets the transmission circuit RXE6 Enables disables reception 0 Disables reception synchronously resets the reception circuit...

Page 364: ...gister see Figure 15 9 3 Set bits 0 to 4 ISRM6 SL6 CL6 PS60 PS61 of the ASIM6 register see Figure 15 5 4 Set bits 0 and 1 TXDLV6 DIR6 of the ASICL6 register see Figure 15 10 5 Set bit 7 POWER6 of the ASIM6 register to 1 6 Set bit 6 TXE6 of the ASIM6 register to 1 Transmission is enabled Set bit 5 RXE6 of the ASIM6 register to 1 Reception is enabled 7 Write data to transmit buffer register 6 TXB6 D...

Page 365: ...ransmission reception Start bit Parity bit D7 D6 D5 D4 D3 1 data frame Character bits D2 D1 D0 Stop bit One data frame consists of the following bits Start bit 1 bit Character bits 7 or 8 bits Parity bit Even parity odd parity 0 parity or no parity Stop bit 1 or 2 bits The character bit length parity and stop bit length in one data frame are specified by asynchronous serial interface operation mod...

Page 366: ...ty Stop bit 1 bit Communication data 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3 Data length 8 bits MSB first Parity Even parity Stop bit 1 bit Communication data 55H TXD6 pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4 Data length 7 bits LSB first Parity Odd parity Stop bit 2 bits Communication data 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity S...

Page 367: ...tion The number of bits that are 1 in the receive data including the parity bit is counted If it is odd a parity error occurs ii Odd parity Transmission Unlike even parity transmit data including the parity bit is controlled so that the number of bits that are 1 is odd If transmit data has an odd number of bits that are 1 0 If transmit data has an even number of bits that are 1 1 Reception The num...

Page 368: ...t shift register 6 TXS6 After that the transmit data is sequentially output from TXS6 to the TXD6 pin When transmission is completed the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request INTST6 is generated Transmission is stopped until the data to be transmitted next is written to TXB6 Figure 15 15 shows the timing of the transmission completion interr...

Page 369: ...n the device is incorporated in a LIN the continuous transmission function cannot be used Make sure that asynchronous serial interface transmission status register 6 ASIF6 is 00H before writing transmit data to transmit buffer register 6 TXB6 TXBF6 Writing to TXB6 Register 0 Writing enabled 1 Writing disabled Caution To transmit data continuously write the first transmit data first byte to the TXB...

Page 370: ...B6 Transfer executed necessary number of times Yes Read ASIF6 TXBF6 0 No No Yes Transmission completion interrupt occurs Read ASIF6 TXSF6 0 No No No Yes Yes Yes Yes Completion of transmission processing Transfer executed necessary number of times Remark TXB6 Transmit buffer register 6 ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 transmit buffer data flag ...

Page 371: ... 1 Data 1 Data 2 Data 3 Data 2 Data 1 Data 3 FF FF Parity Stop Data 2 Parity Stop TXB6 TXS6 TXBF6 TXSF6 Start Start Note Note When ASIF6 is read there is a period in which TXBF6 and TXSF6 1 1 Therefore judge whether writing is enabled using only the TXBF6 bit Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronou...

Page 372: ...top TXB6 TXS6 TXBF6 TXSF6 POWER6 or TXE6 Start Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 TXSF6 Bit 0 of ASIF6 POWER6 Bit 7 of asynchronous serial interface operation mode register ASIM6 TXE6 Bit 6 of asynchronous serial interface o...

Page 373: ...e stop bit has been received the reception completion interrupt INTSR6 is generated and the data of RXS6 is written to receive buffer register 6 RXB6 If an overrun error OVE6 occurs however the receive data is not written to RXB6 Even if a parity error PE6 occurs while reception is in progress reception continues to the reception position of the stop bit and a reception error interrupt INTSR6 INTS...

Page 374: ...eption Error Cause Parity error The parity specified for transmission does not match the parity of the receive data Framing error Stop bit is not detected Overrun error Reception of the next data is completed before data is read from receive buffer register 6 RXB6 The reception error interrupt can be separated into reception completion interrupt INTSR6 and error interrupt INTSRE6 by clearing bit 0...

Page 375: ...ansmission Operation When bit 7 POWER6 of asynchronous serial interface mode register 6 ASIM6 is set to 1 the TXD6 pin outputs high level Next when bit 6 TXE6 of ASIM6 is set to 1 the transmission enabled status is entered and SBF transmission is started by setting bit 5 SBTT6 of asynchronous serial interface control register 6 ASICL6 to 1 Thereafter a low level of bits 13 to 20 set by bits 4 to 2...

Page 376: ... request INTSR6 is generated as normal processing At this time the SBRF6 and SBRT6 bits are automatically cleared and SBF reception ends Detection of errors such as OVE6 PE6 and FE6 bits 0 to 2 of asynchronous serial interface reception error status register 6 ASIS6 is suppressed and error detection processing of UART communication is not performed In addition data transfer between receive shift r...

Page 377: ...el when POWER6 0 Transmission counter This counter stops operation cleared to 0 when bit 7 POWER6 or bit 6 TXE6 of asynchronous serial interface operation mode register 6 ASIM6 is 0 It starts counting when POWER6 1 and TXE6 1 The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 TXB6 If data are continuously transmitted the counter is cleared to 0 aga...

Page 378: ...e clock to be input to the 8 bit counter can be set by bits 3 to 0 TPS63 to TPS60 of CKSR6 and the division value fXCLK6 8 to fXCLK6 255 of the 8 bit counter can be set by bits 7 to 0 MDL67 to MDL60 of BRGC6 Table 15 4 Set Value of TPS63 to TPS60 Base Clock fXCLK6 Selection TPS63 TPS62 TPS61 TPS60 fPRS 2 MHz fPRS 5 MHz fPRS 10 MHz fPRS 20 MHz 0 0 0 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz 0 0 0 1 fPRS 2 1...

Page 379: ...g expression Error 1 100 Cautions 1 Keep the baud rate error during transmission to within the permissible error range at the reception destination 2 Make sure that the baud rate error during reception satisfies the range shown in 4 Permissible baud rate range during reception Example Frequency of base clock 10 MHz 10 000 000 Hz Set value of MDL67 to MDL60 bits of BRGC6 register 00100001B k 33 Tar...

Page 380: ...2H 65 9615 0 16 3H 65 9615 0 16 4H 65 9615 0 16 19200 2H 13 19231 0 16 1H 65 19231 0 16 2H 65 19231 0 16 3H 65 19231 0 16 24000 1H 21 23810 0 79 3H 13 24038 0 16 4H 13 24038 0 16 5H 13 24038 0 16 31250 1H 4 31250 0 4H 5 31250 0 5H 5 31250 0 6H 5 31250 0 38400 1H 13 38462 0 16 0H 65 38462 0 16 1H 65 38462 0 16 2H 65 38462 0 16 48000 0H 21 47619 0 79 2H 13 48077 0 16 3H 13 48077 0 16 4H 13 48077 0 1...

Page 381: ...tart bit Bit 0 Bit 1 Bit 7 Parity bit Minimum permissible data frame length Maximum permissible data frame length Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Latch timing Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 15 25 the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 BRGC6 after the start bit has b...

Page 382: ...ible baud rate error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions as follows Table 15 6 Maximum Minimum Permissible Baud Rate Error Division Ratio k Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 3 53 3 61 20 4 26 4 31 50 4 56 4 58 100 4 66 4 67 255 4 72 4 73 Remarks 1 The permissible error of r...

Page 383: ...ected because the timing is initialized on the reception side when the start bit is detected Figure 15 26 Data Frame Length During Continuous Transmission Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame FL FL FL FL FL FL FLstp Start bit of second byte Start bit Bit 0 Where the 1 bit data length is FL the stop bit length is FLstp and base clock frequency is fXCLK6 the following expr...

Page 384: ...ails see 16 4 1 Operation stop mode 2 3 wire serial I O mode MSB LSB first selectable This mode is used to communicate 8 bit data using three lines a serial clock line SCK1n and two serial data lines SI1n and SO1n The processing time of data communication can be shortened in the 3 wire serial I O mode because transmission and reception can be simultaneously executed In addition whether 8 bit data ...

Page 385: ...ter 1n CSIM1n Serial clock selection register 1n CSIC1n Port mode register 0 PM0 or port mode register 1 PM1 Port register 0 P0 or port register 1 P1 Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F0534 78F0535 78F0536 78F0537 78F0537D Figure 16 1 Block Diagram of Serial Interface CSI10 Internal bus SI10 P11 RXD0 INTCSI10 fPRS 2 fPRS 22 fPRS 23 fPRS 24 fPRS 25 fPRS 26 fPRS 27 SCK10 P10 TxD0 Tran...

Page 386: ...78F0535 78F0536 78F0537 78F0537D 8 8 Internal bus Output selector Output latch Transmit controller Clock start stop controller clock phase controller SO11 P02 INTCSI11 Transmit buffer register 11 SOTB11 Transmit data controller SI11 P03 Serial I O shift register 11 SIO11 fPRS 2 fPRS 22 fPRS 23 fPRS 24 fPRS 25 fPRS 26 fPRS 27 SSI11 Output latch P02 PM02 a Baud rate generator ...

Page 387: ...1n if bit 6 TRMD1n of serial operation mode register 1n CSIM1n is 0 During reception the data is read from the serial input pin SI1n to SIO1n Reset signal generation sets this register to 00H Cautions 1 Do not access SIO1n when CSOT1n 1 during serial communication 2 In the slave mode reception is started when data is read from SIO11 with a low level input to the SSI11 pin For details on the recept...

Page 388: ...FF80H After reset 00H R W Note 1 Symbol 7 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10 CSIE10 Operation control in 3 wire serial I O mode 0 Disables operation Note 2 and asynchronously resets the internal circuit Note 3 1 Enables operation TRMD10 Note 4 Transmit receive mode control 0 Note 5 Receive mode transmission disabled 1 Transmit receive mode DIR10 Note 6 First bit specification ...

Page 389: ...not used 1 SSI11 pin is used DIR11 Note 8 First bit specification 0 MSB 1 LSB CSOT11 Communication status flag 0 Communication is stopped 1 Communication is in progress Notes 1 Bit 0 is a read only bit 2 To use P02 SO11 P04 SCK11 and P05 SSI11 TI001 as general purpose ports set CSIM11 in the default status 00H 3 Bit 0 CSOT11 of CSIM11 and serial I O shift register 11 SIO11 are reset 4 Do not rewri...

Page 390: ...5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 3 1 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 4 CSI10 serial clock selection CKS102 CKS101 CKS100 fPRS 2 MHz fPRS 5 MHz fPRS 10 MHz fPRS 20 MHz Mode 0 0 0 fPRS 2 1 MHz 2 5 MHz 5 MHz 10 MHz 0 0 1 fPRS 2 2 500 kHz 1 25 MHz 2 5 MHz 5 MHz 0 1 0 fPRS 2 3 250 kHz 625 kHz 1 25 MHz 2 5 MHz...

Page 391: ...serial clock selection CKS112 CKS111 CKS110 fPRS 2 MHz fPRS 5 MHz fPRS 10 MHz fPRS 20 MHz Mode 0 0 0 fPRS 2 1 MHz 2 5 MHz 5 MHz 10 MHz 0 0 1 fPRS 2 2 500 kHz 1 25 MHz 2 5 MHz 5 MHz 0 1 0 fPRS 2 3 250 kHz 625 kHz 1 25 MHz 2 5 MHz 0 1 1 fPRS 2 4 125 kHz 312 5 kHz 625 kHz 1 25 MHz 1 0 0 fPRS 2 5 62 5 kHz 156 25 kHz 312 5 kHz 625 kHz 1 0 1 fPRS 2 6 31 25 kHz 78 13 kHz 156 25 kHz 312 5 kHz 1 1 0 fPRS 2...

Page 392: ... Note TI001 as the chip select input pin set PM10 PM04 PM11 PM03 and PM05 to 1 At this time the output latches of P10 P04 P11 P03 and P05 may be 0 or 1 PM0 and PM1 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets these registers to FFH Note Available only in the µPD78F0534 78F0535 78F0536 78F0537 78F0537D Figure 16 7 Format of Port Mode Register 0 PM0 7 1...

Page 393: ...on instruction Reset signal generation sets CSIM1n to 00H Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F0534 78F0535 78F0536 78F0537 78F0537D Serial operation mode register 10 CSIM10 Address FF80H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10 CSIE10 Operation control in 3 wire serial I O mode 0 Disables operation Note 1 and asynchronously resets the inter...

Page 394: ...r port register 1 P1 The basic procedure of setting an operation in the 3 wire serial I O mode is as follows 1 Set the CSIC1n register see Figures 16 5 and 16 6 2 Set bits 0 and 4 to 6 CSOT1n DIR1n SSE11 serial interface CSI11 only and TRMD1n of the CSIM1n register see Figures 16 3 and 16 4 3 Set bit 7 CSIE1n of the CSIM1n register to 1 Transmission reception is enabled 4 Write data to transmit bu...

Page 395: ...Slave transmission Note 3 RXD0 P11 SO10 SCK10 input Note 3 1 1 1 0 0 1 Slave transmission reception Note 3 SI10 SO10 SCK10 input Note 3 1 0 1 Note 1 Note 1 0 1 Master reception SI10 P12 SCK10 output 1 1 Note 1 Note 1 0 0 0 1 Master transmission RXD0 P11 SO10 SCK10 output 1 1 1 0 0 0 1 Master transmission reception SI10 SO10 SCK10 output Notes 1 Can be set as port function 2 To use P10 SCK10 TXD0 a...

Page 396: ... transmission Note 3 P03 SO11 SCK11 input Note 3 SSI11 0 Note 1 Note 1 TI001 P05 1 1 1 1 0 0 1 1 Slave transmission reception Note 3 SI11 SO11 SCK11 input Note 3 SSI11 1 0 0 1 Note 1 Note 1 0 1 Note 1 Note 1 Master reception SI11 P02 SCK11 output TI001 P05 1 1 0 Note 1 Note 1 0 0 0 1 Note 1 Note 1 Master transmission P03 SO11 SCK11 output TI001 P05 1 1 0 1 0 0 0 1 Note 1 Note 1 Master transmission...

Page 397: ... SSI11 pin Transmission reception or reception is held therefore even if SOTB11 is written or SIO11 is read transmission reception or reception will not be started 3 Data is written to SOTB11 or data is read from SIO11 while a high level is input to the SSI11 pin then a low level is input to the SSI11 pin Transmission reception or reception is started 4 A high level is input to the SSI11 pin durin...

Page 398: ...P1n 0 DAP1n 0 SSE11 1Note AAH ABH 56H ADH 5AH B5H 6AH D5H 55H communication data 55H is written to SOTB1n SCK1n SOTB1n SIO1n CSOT1n CSIIF1n SO1n SI1n receive AAH Read write trigger INTCSI1n SSI11Note Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11 and are used in the slave mode Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F0534 78F0535 78F0536 78F0537 78F0537D ...

Page 399: ...KP1n 0 DAP1n 1 SSE11 1Note ABH 56H ADH 5AH B5H 6AH D5H SCK1n SOTB1n SIO1n CSOT1n CSIIF1n SO1n SI1n input AAH AAH 55H communication data 55H is written to SOTB1n Read write trigger INTCSI1n SSI11Note Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11 and are used in the slave mode Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F0534 78F0535 78F0536 78F0537 78F0537D ...

Page 400: ... Writing to SOTB1n or reading from SIO1n SI1n capture CSIIF1n CSOT1n c Type 3 CKP1n 1 DAP1n 0 DIR1n 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK1n SO1n Writing to SOTB1n or reading from SIO1n SI1n capture CSIIF1n CSOT1n d Type 4 CKP1n 1 DAP1n 1 DIR1n 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK1n SO1n Writing to SOTB1n or reading from SIO1n SI1n capture CSIIF1n CSOT1n Remarks 1 n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F0534 7...

Page 401: ...h SO1n Writing to SOTB1n or reading from SIO1n First bit 2nd bit The first bit is directly latched by the SOTB1n register to the output latch at the falling or rising edge of SCK1n and output from the SO1n pin via an output selector Then the value of the SOTB1n register is transferred to the SIO1n register at the next rising or falling edge of SCK1n and shifted one bit At the same time the first b...

Page 402: ...t the falling edge of the write signal of the SOTB1n register or the read signal of the SIO1n register and output from the SO1n pin via an output selector Then the value of the SOTB1n register is transferred to the SIO1n register at the next falling or rising edge of SCK1n and shifted one bit At the same time the first bit of the receive data is stored in the SIO1n register via the SI1n pin The se...

Page 403: ...t bit Figure 16 12 Output Value of SO1n Pin Last Bit 1 2 a Type 1 CKP1n 0 DAP1n 0 SCK1n SOTB1n SIO1n SO1n Writing to SOTB1n or reading from SIO1n Next request is issued Last bit Output latch b Type 3 CKP1n 1 DAP1n 0 Last bit Next request is issued SCK1n SOTB1n SIO1n Output latch SO1n Writing to SOTB1n or reading from SIO1n Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F0534 78F0535 78F0536 78F0...

Page 404: ...2 CKP1n 0 DAP1n 1 SCK1n SOTB1n SIO1n SO1n Last bit Writing to SOTB1n or reading from SIO1n Next request is issued Output latch d Type 4 CKP1n 1 DAP1n 1 Last bit Next request is issued SCK1n SOTB1n SIO1n Output latch SO1n Writing to SOTB1n or reading from SIO1n Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F0534 78F0535 78F0536 78F0537 78F0537D ...

Page 405: ... Note 1 TRMD1n 0 Note 2 Outputs low level Note 2 DAP1n 0 Value of SO1n latch low level output DIR1n 0 Value of bit 7 of SOTB1n TRMD1n 1 DAP1n 1 DIR1n 1 Value of bit 0 of SOTB1n Notes 1 The actual output of the SO10 P12 or SO11 P02 pin is determined according to PM12 and P12 or PM02 and P02 as well as the SO1n output 2 Status after reset Caution If a value is written to TRMD1n DAP1n and DIR1n the o...

Page 406: ...ck SCL0 line and a serial data bus SDA0 line This mode complies with the I2 C bus format and the master device can generated start condition address transfer direction specification data and stop condition data to the slave device via the serial data bus The slave device automatically detects these received status and data by hardware This function can simplify the part of application program that...

Page 407: ...generator Wake up controller ACK detector Output control Stop condition detector Serial clock counter Interrupt request signal generator Serial clock controller Serial clock wait controller Prescaler INTIIC0 IIC shift register 0 IIC0 IICC0 STT0 SPT0 IICS0 MSTS0 EXC0 COI0 IICS0 MSTS0 EXC0 COI0 fPRS LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 Start condition det...

Page 408: ...ial bus configuration example Figure 17 2 Serial Bus Configuration Example Using I2 C Bus Master CPU1 Slave CPU1 Address 0 SDA0 SCL0 Serial data bus Serial clock VDD VDD SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 Master CPU2 Slave CPU2 Address 1 Slave CPU3 Address 2 Slave IC Address 3 Slave IC Address N ...

Page 409: ... the wait state and start data transfer by writing data to IIC0 during the wait period IIC0 is set by an 8 bit memory manipulation instruction Reset signal generation sets IIC0 to 00H Figure 17 3 Format of IIC Shift Register 0 IIC0 Symbol IIC0 Address FFA5H After reset 00H R W 7 6 5 4 3 2 1 0 Cautions 1 Do not write data to IIC0 during data transfer 2 Write or read IIC0 only during the wait period...

Page 410: ...l clock set by WTIM0 bit Interrupt request generated when a stop condition is detected set by SPIE0 bit Remark WTIM0 bit Bit 3 of IIC control register 0 IICC0 SPIE0 bit Bit 4 of IIC control register 0 IICC0 8 Serial clock controller In master mode this circuit generates the clock output via the SCL0 pin from a sampling clock 9 Serial clock wait controller This circuit controls the wait timing 10 A...

Page 411: ...top conditions However as the bus status cannot be detected immediately following operation the initial status is set by the STCEN bit Remark STT0 bit Bit 1 of IIC control register 0 IICC0 SPT0 bit Bit 0 of IIC control register 0 IICC0 IICRSV bit Bit 0 of IIC flag register 0 IICBSY bit Bit 6 of IIC flag register 0 STCF bit Bit 7 of IIC flag register 0 STCEN bit Bit 1 of IIC flag register 0 ...

Page 412: ...gister 0 IICCL0 IIC function expansion register 0 IICX0 Port mode register 6 PM6 Port register 6 P6 1 IIC control register 0 IICC0 This register is used to enable stop I2 C operations set wait timing and set other I 2 C operations IICC0 is set by a 1 bit or 8 bit memory manipulation instruction However set the SPIE0 WTIM0 and ACKE0 bits while IICE0 bit 0 or during the wait period These bits can be...

Page 413: ...ing exit from communications remains in effect until the following communications entry conditions are met After a stop condition is detected restart is in master mode An address match or extension code reception occurs after the start condition Condition for clearing LREL0 0 Condition for setting LREL0 1 Automatically cleared after execution Reset Set by instruction WREL0 Note 2 Wait cancellation...

Page 414: ...address transfer independently of the setting of this bit The setting of this bit is valid when the address transfer is completed When in master mode a wait is inserted at the falling edge of the ninth clock during address transfers For a slave device that has received a local address a wait is inserted at the falling edge of the ninth clock after an acknowledge ACK is issued However when the slav...

Page 415: ... when master device Generates a restart condition after releasing the wait Cautions concerning set timing For master reception Cannot be set to 1 during transfer Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been notified of final reception For master transmission A start condition cannot be generated normally during the acknowledge period Set to 1 durin...

Page 416: ...as been cleared to 0 if SPT0 is set to 1 during the wait period that follows output of eight clocks note that a stop condition will be generated during the high level period of the ninth clock WTIM0 should be changed from 0 to 1 during the wait period following the output of eight clocks and SPT0 should be set to 1 during the wait period that follows the output of the ninth clock Setting SPT0 to 1...

Page 417: ...on stop Reset When a start condition is generated ALD0 Detection of arbitration loss 0 This status means either that there was no arbitration or that the arbitration result was a win 1 This status indicates the arbitration result was a loss MSTS0 is cleared Condition for clearing ALD0 0 Condition for setting ALD0 1 Automatically cleared after IICS0 is read Note When IICE0 changes from 1 to 0 opera...

Page 418: ...or clearing TRC0 0 Condition for setting TRC0 1 Both master and slave When a stop condition is detected Cleared by LREL0 1 exit from communications When IICE0 changes from 1 to 0 operation stop Cleared by WREL0 1 Note wait cancel When ALD0 changes from 0 to 1 arbitration loss Reset Master When 1 is output to the first byte s LSB transfer direction specification bit Slave When a start condition is ...

Page 419: ...etected SPD0 Detection of stop condition 0 Stop condition was not detected 1 Stop condition was detected The master device s communication is terminated and the bus is released Condition for clearing SPD0 0 Condition for setting SPD0 1 At the rising edge of the address transfer byte s first clock following setting of this bit and detection of a start condition When IICE0 changes from 1 to 0 operat...

Page 420: ...STCEN 0 Detection of stop condition Reset Condition for setting STCEN 1 Set by instruction STCEN 0 1 After operation is enabled IICE0 1 enable generation of a start condition upon detection of a stop condition After operation is enabled IICE0 1 enable generation of a start condition without detecting a stop condition Initial start enable trigger Condition for clearing IICRSV 0 Cleared by instructi...

Page 421: ...in was detected at low level 1 The SCL0 pin was detected at high level Condition for clearing CLD0 0 Condition for setting CLD0 1 When the SCL0 pin is at low level When IICE0 0 operation stop Reset When the SCL0 pin is at high level DAD0 Detection of SDA0 pin level valid only when IICE0 1 0 The SDA0 pin was detected at low level 1 The SDA0 pin was detected at high level Condition for clearing DAD0...

Page 422: ...IICCL0 see 17 3 6 I2 C transfer clock setting method Set IICX0 while bit 7 IICE0 of IIC control register 0 IICC0 is 0 Reset signal generation sets IICX0 to 00H Figure 17 9 Format of IIC Function Expansion Register 0 IICX0 Address FFA9H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IICX0 0 0 0 0 0 0 0 CLX0 6 I2 C transfer clock setting method The I2 C transfer clock frequency fSCL is calculated using ...

Page 423: ...lock fW Transfer Clock fW m Settable Selection Clock fW Range Operation Mode 0 0 0 0 fPRS 2 fW 44 2 00 to 4 19 MHz 0 0 0 1 fPRS 2 fW 86 0 0 1 0 fPRS 4 fW 86 4 19 to 8 38 MHz 0 0 1 1 fEXSCL0 fW 66 6 4 MHz Normal mode SMC0 bit 0 0 1 0 fPRS 2 fW 24 0 1 1 0 fPRS 4 fW 24 4 00 to 8 38 MHz 0 1 1 1 fEXSCL0 fW 18 6 4 MHz High speed mode SMC0 bit 1 1 0 Setting prohibited 1 1 0 fPRS 2 fW 12 1 1 1 0 fPRS 4 fW...

Page 424: ...0 Set IICE0 bit 7 of IIC control register 0 IICC0 to 1 before setting the output mode because the P60 SCL0 and P61 SDA0 pins output a low level fixed when IICE0 is 0 PM6 is set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets PM6 to FFH Figure 17 10 Format of Port Mode Register 6 PM6 PM60 PM61 PM62 PM63 1 1 1 1 P6n pin I O mode selection n 0 to 3 Output mode output ...

Page 425: ...ave devices Input is Schmitt input 2 SDA0 This pin is used for serial data input and output This pin is an N ch open drain output for both master and slave devices Input is Schmitt input Since outputs from the serial clock line and the serial data bus line are N ch open drain outputs an external pull up resistor is required Figure 17 11 Pin Configuration Diagram Master device Clock output Clock in...

Page 426: ...e device normally it is output by the device that receives 8 bit data The serial clock SCL0 is continuously output by the master device However in the slave device the SCL0 s low level period can be extended and a wait can be inserted 17 5 1 Start conditions A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level The start conditions for th...

Page 427: ...d if data other than a local address or extension code is received during slave device operation The slave address and the eighth bit which specifies the transfer direction as described in 17 5 3 Transfer direction specification below are together written to IIC shift register 0 IIC0 and are then output Received addresses are written to IIC0 The slave address is assigned to the higher 7 bits of II...

Page 428: ...0 to 1 Bit 3 TRC0 of the IICS0 register is set by the data of the eighth bit that follows 7 bit address information Usually set ACKE0 to 1 for reception TRC0 0 If a slave can receive no more data during reception TRC0 0 or does not require the next data item then the slave must inform the master by clearing ACKE0 to 0 that it will not receive any more data When the master does not require the next...

Page 429: ...that the master device generates to the slave device when serial transfer has been completed When the device is used as a slave stop conditions can be detected Figure 17 17 Stop Condition SCL0 SDA0 H A stop condition is generated when bit 0 SPT0 of IIC control register 0 IICC0 is set to 1 When the stop condition is detected bit 0 SPD0 of IIC status register 0 IICS0 is set to 1 and INTIIC0 is gener...

Page 430: ...he master and slave devices the next data transfer can begin Figure 17 18 Wait 1 2 1 When master device has a nine clock wait and slave device has an eight clock wait master transmits slave receives and ACKE0 1 Master IIC0 SCL0 Slave IIC0 SCL0 ACKE0 Transfer lines SCL0 SDA0 6 7 8 9 1 2 3 Master returns to high impedance but slave is in wait state low level Wait after output of ninth clock IIC0 dat...

Page 431: ... 9 1 2 3 D2 D1 D0 ACK D7 D6 D5 Generate according to previously set ACKE0 value Remark ACKE0 Bit 2 of IIC control register 0 IICC0 WREL0 Bit 5 of IIC control register 0 IICC0 A wait may be automatically generated depending on the setting of bit 3 WTIM0 of IIC control register 0 IICC0 Normally the receiving side cancels the wait state when bit 5 WREL0 of IICC0 is set to 1 or when FFH is written to ...

Page 432: ...state can be canceled If the I2 C bus has deadlocked due to noise processing is saved from communication by setting bit 6 LREL0 of IICC0 so that the wait state can be canceled 17 5 8 Interrupt request INTIIC0 generation timing and wait control The setting of bit 3 WTIM0 of IIC control register 0 IICC0 determines the timing by which INTIIC0 is generated and the corresponding wait control as shown i...

Page 433: ...ister generating stop condition Note Note Master only When an 8 clock wait has been selected WTIM0 0 the presence absence of ACK generation must be determined prior to wait cancellation 5 Stop condition detection INTIIC0 is generated when a stop condition is detected only when SPIE0 1 17 5 9 Address match detection method In I2 C bus mode the master device can select a particular slave device by t...

Page 434: ...IC status register 0 IICS0 COI0 Bit 4 of IIC status register 0 IICS0 3 Since the processing after the interrupt request occurs differs according to the data that follows the extension code such processing is performed by software If the extension code is received while a slave device is operating then the slave device is participating in communication even if its address does not match For example...

Page 435: ...0 is set 1 via the timing by which the arbitration loss occurred and the SCL0 and SDA0 lines are both set to high impedance which releases the bus The arbitration loss is detected based on the timing of the next interrupt request the eighth or ninth clock when a stop condition is detected etc and the ALD0 1 setting that has been made by software For details of interrupt request timing see 17 5 17 ...

Page 436: ...ng to generate a restart condition At falling edge of eighth or ninth clock following byte transfer Note 1 Notes 1 When WTIM0 bit 3 of IIC control register 0 IICC0 1 an interrupt request occurs at the falling edge of the ninth clock When WTIM0 0 and the extension code s slave address is received an interrupt request occurs at the falling edge of the eighth clock 2 When there is a chance that arbit...

Page 437: ... bit 4 SPIE0 of IICC0 was set to 1 and it was detected by generation of an interrupt request signal INTIIC0 that the bus was released detection of the stop condition then the device automatically starts communication as the master Data written to IIC0 before the stop condition is detected is invalid When STT0 has been set to 1 the operation mode as start condition or as communication reservation i...

Page 438: ...register 0 STT0 Bit 1 of IIC control register 0 IICC0 STD0 Bit 1 of IIC status register 0 IICS0 SPD0 Bit 0 of IIC status register 0 IICS0 Communication reservations are accepted via the following timing After bit 1 STD0 of IIC status register 0 IICS0 is set to 1 a communication reservation can be made by setting bit 1 STT0 of IIC control register 0 IICC0 to 1 before a stop condition is detected Fi...

Page 439: ... Bit 1 of IIC control register 0 IICC0 MSTS0 Bit 7 of IIC status register 0 IICS0 IIC0 IIC shift register 0 2 When communication reservation function is disabled bit 0 IICRSV of IIC flag register 0 IICF0 1 When bit 1 STT0 of IIC control register 0 IICC0 is set to 1 when the bus is not used in a communication during bus communication this request is rejected and a start condition is not generated T...

Page 440: ...regardless of the actual bus status To generate the first start condition STT0 bit 1 of IIC control register 0 IICC0 1 it is necessary to confirm that the bus has been released so as to not disturb other communications 3 If other I2 C communications are already in progress If I2 C operation is enabled and the device participates in communication already in progress when the SDA0 pin is low and the...

Page 441: ...so that an interrupt request is generated when the stop condition is detected Transfer is started when communication data is written to IIC0 after the interrupt request is generated Unless the interrupt is generated when the stop condition is detected the device stops in the wait state because the interrupt request is not generated when communication is started However it is not necessary to set S...

Page 442: ...on Starts communication specifies an address and transfer direction Waits for detection of acknowledge Waits for data transmission Starts transmission Communication processing Initial setting Starts reception Waits for data reception No Yes INTIIC0 interrupt occurs Waits for detection of acknowledge Prepares for starting communication generates a stop condition Waits for detection of the stop cond...

Page 443: ...cal address Sets a start condition Communication start request No communication start request Waiting to be specified as a slave by other master Waiting for a communication start request depends on user program Prepares for starting communication generates a stop condition Waits for detection of the stop condition No Yes Yes No INTIIC0 interrupt occurs INTIIC0 interrupt occurs Yes No Yes No SPD0 1...

Page 444: ...Wait state after stop condition was detected and start condition was generated by the communication reservation function No INTIIC0 interrupt occurs Yes Yes No No A C STT0 1 Wait Slave operation Yes IICBSY 0 EXC0 1 or COI0 1 Prepares for starting communication generates a start condition Disables reserving communication Enables reserving communication Secure wait time by software see Table 18 7 Wa...

Page 445: ...interrupt occurs No Yes ACKD0 1 No Yes No C 2 Yes MSTS0 1 No Yes Transfer end No Yes ACKD0 1 No 2 Yes MSTS0 1 No 2 Waits for detection of ACK Yes No INTIIC0 interrupt occurs Yes MSTS0 1 No C 2 Yes EXC0 1 or COI0 1 No 1 2 SPT0 1 STT0 1 Slave operation END Communication processing Communication processing Remarks 1 Conform to the specifications of the product that is communicating with respect to th...

Page 446: ...e flags and passing them to the main processing instead of INTIIC0 1 Communication mode flag This flag indicates the following two communication statuses Clear mode Status in which data communication is not performed Communication mode Status in which data communication is performed from valid address detection to stop condition detection no detection of ACK from master address mismatch 2 Ready fl...

Page 447: ... next data After that the master generates a stop condition or restart condition Exit from the communication status occurs in this way Figure 17 25 Slave Operation Flowchart 1 Yes Yes Yes Yes Yes Yes Yes No No No No No No START Communication mode flag 1 Communication mode flag 1 Communication direction flag 1 Ready flag 1 Communication direction flag 1 Reading IIC0 Clearing ready flag Clearing rea...

Page 448: ...s does not match If the address matches the communication mode is set wait is cancelled and processing returns from the interrupt the ready flag is cleared 3 For data transmit receive only the ready flag is set Processing returns from the interrupt with the I2 C bus remaining in the wait state Remark 1 to 3 above correspond to 1 to 3 in Figure 17 26 Slave Operation Flowchart 2 Figure 17 26 Slave O...

Page 449: ...7 Timing of I 2 C interrupt request INTIIC0 occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIIC0 and the value of the IICS0 register when the INTIIC0 signal is generated are shown below Remark ST Start condition AD6 to AD0 Address ...

Page 450: ...B Sets WTIM0 to 1 Note 4 IICS0 1000 00B Sets SPT0 to 1 Note 5 IICS0 00000001B Note To generate a stop condition set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP SPT0 1 3 4 2 1 1 IICS0 1000 110B 2 IICS0 1000 100B 3 IICS0 1000 00B S...

Page 451: ...0000001B Notes 1 To generate a start condition set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal 2 Clear WTIM0 to 0 to restore the original setting 3 To generate a stop condition set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 ...

Page 452: ...M0 to 1 Note 4 IICS0 1010 00B Sets SPT0 to 1 5 IICS0 00000001B Note To generate a stop condition set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt request signal Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP SPT0 1 3 4 2 1 1 IICS0 1010 110B 2 IICS0 1010 100B 3 IICS0 1010 00B Sets SPT0 to 1 4...

Page 453: ...0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 1 IICS0 0001 110B 2 IICS0 0001 000B 3 IICS0 0001 000B 4 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 1 IICS0 0001 110B 2 IICS0 0001 100B 3 IICS0 0001 00B 4 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ...

Page 454: ...3 4 5 2 1 1 IICS0 0001 110B 2 IICS0 0001 000B 3 IICS0 0001 110B 4 IICS0 0001 000B 5 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart matches with SVA0 ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 5 2 1 1 IICS0 0001 110B 2 IICS0 0001 00B 3 IICS0 0001 110B 4 IICS0 0001 00B 5 IICS0 00000001B Remark Always gene...

Page 455: ...IICS0 0001 110B 2 IICS0 0001 000B 3 IICS0 0010 010B 4 IICS0 0010 000B 5 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart does not match address extension code ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 5 6 2 1 4 1 IICS0 0001 110B 2 IICS0 0001 00B 3 IICS0 0010 010B 4 IICS0 0010 110B 5 IICS0 0010 00B 6 IICS0 ...

Page 456: ...T R W D7 to D0 ACK 3 4 2 1 1 IICS0 0001 110B 2 IICS0 0001 000B 3 IICS0 00000110B 4 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart does not match address not extension code ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 2 1 1 IICS0 0001 110B 2 IICS0 0001 00B 3 IICS0 00000110B 4 IICS0 00000001B Remark Always ...

Page 457: ... Stop i When WTIM0 0 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 1 IICS0 0010 010B 2 IICS0 0010 000B 3 IICS0 0010 000B 4 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 5 2 1 1 IICS0 0010 010B 2 IICS0 0010 110B 3 IICS0 0010 100B 4 IICS0 0010 00B 5 IICS0 00000001B Remark Always gener...

Page 458: ...IICS0 0010 010B 2 IICS0 0010 000B 3 IICS0 0001 110B 4 IICS0 0001 000B 5 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart matches SVA0 ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 6 2 1 5 1 IICS0 0010 010B 2 IICS0 0010 110B 3 IICS0 0010 00B 4 IICS0 0001 110B 5 IICS0 0001 00B 6 IICS0 00000001B Remark Always g...

Page 459: ...010B 2 IICS0 0010 000B 3 IICS0 0010 010B 4 IICS0 0010 000B 5 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart extension code reception ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 7 2 1 5 6 1 IICS0 0010 010B 2 IICS0 0010 110B 3 IICS0 0010 00B 4 IICS0 0010 010B 5 IICS0 0010 110B 6 IICS0 0010 00B 7 IICS0 0000...

Page 460: ...D0 ACK 3 4 2 1 1 IICS0 00100010B 2 IICS0 00100000B 3 IICS0 00000110B 4 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart does not match address not extension code ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 5 2 1 1 IICS0 00100010B 2 IICS0 00100110B 3 IICS0 00100 00B 4 IICS0 00000110B 5 IICS0 00000001B Remar...

Page 461: ...n as slave after arbitration loss When the device is used as a master in a multi master system read the MSTS0 bit each time interrupt request signal INTIIC0 has occurred to check the arbitration result a When arbitration loss occurs during transmission of slave address data i When WTIM0 0 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 1 IICS0 0101 110B 2 IICS0 0001 000B 3 IICS0 0001 00...

Page 462: ...1 100B 3 IICS0 0001 00B 4 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care b When arbitration loss occurs during transmission of extension code i When WTIM0 0 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 1 IICS0 0110 010B 2 IICS0 0010 000B 3 IICS0 0010 000B 4 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ...

Page 463: ...0 1 Don t care 6 Operation when arbitration loss occurs no communication after arbitration loss When the device is used as a master in a multi master system read the MSTS0 bit each time interrupt request signal INTIIC0 has occurred to check the arbitration result a When arbitration loss occurs during transmission of slave address data when WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP...

Page 464: ...to D0 ACK ACK SP 2 1 1 IICS0 0110 010B Sets LREL0 1 by software 2 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care c When arbitration loss occurs during transmission of data i When WTIM0 0 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 2 1 1 IICS0 10001110B 2 IICS0 01000000B 3 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 ...

Page 465: ...B 3 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 d When loss occurs due to restart condition during data transfer i Not extension code Example unmatches with SVA0 ST AD6 to AD0 R W ACK D7 to Dn AD6 to AD0 ACK SP ST R W D7 to D0 ACK 3 2 1 1 IICS0 1000 110B 2 IICS0 01000110B 3 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care n 6 to 0 ...

Page 466: ... 3 2 1 1 IICS0 1000 110B 2 IICS0 01100010B Sets LREL0 1 by software 3 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care n 6 to 0 e When loss occurs due to stop condition during data transfer ST AD6 to AD0 R W ACK D7 to Dn SP 2 1 1 IICS0 10000110B 2 IICS0 01000001B Remark Always generated Generated only when SPIE0 1 Don t care n 6 to 0 ...

Page 467: ... ACK STT0 1 3 4 5 2 1 1 IICS0 1000 110B 2 IICS0 1000 000B Sets WTIM0 to 1 3 IICS0 1000 100B Clears WTIM0 to 0 4 IICS0 01000000B 5 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK SP ACK D7 to D0 ACK STT0 1 3 4 2 1 1 IICS0 1000 110B 2 IICS0 1000 100B Sets STT0 to 1 3 IICS0 01000100B 4 IICS0 00000001B Remark Al...

Page 468: ... AD0 R W ACK D7 to D0 ACK SP STT0 1 3 4 2 1 1 IICS0 1000 110B 2 IICS0 1000 000B Sets WTIM0 to 1 3 IICS0 1000 00B Sets STT0 to 1 4 IICS0 01000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 ACK SP STT0 1 2 3 1 1 IICS0 1000 110B 2 IICS0 1000 00B Sets STT0 to 1 3 IICS0 01000001B Remark Always generated Generated only when SPIE0 1 Don ...

Page 469: ...ACK SPT0 1 3 4 5 2 1 1 IICS0 1000 110B 2 IICS0 1000 000B Sets WTIM0 to 1 3 IICS0 1000 100B Clears WTIM0 to 0 4 IICS0 01000100B 5 IICS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK SP ACK D7 to D0 ACK SPT0 1 3 4 2 1 1 IICS0 1000 110B 2 IICS0 1000 100B Sets SPT0 to 1 3 IICS0 01000100B 4 IICS0 00000001B Remark Alw...

Page 470: ...ransmits the TRC0 bit bit 3 of IIC status register 0 IICS0 which specifies the data transfer direction and then starts serial communication with the slave device Figures 17 27 and 17 28 show timing charts of the data communication IIC shift register 0 IIC0 s shift operation is synchronized with the falling edge of the serial clock SCL0 The transmit data is transferred to the SO0 latch and is outpu...

Page 471: ...PD0 WTIM0 H H L L L L H H H L L ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 W ACK D4 D5 D6 D7 IIC0 address IIC0 data IIC0 FFH Transmit Start condition Receive When EXC0 1 Note Note Note To cancel slave...

Page 472: ...H H L L L L L L H H H H L L L L L ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 Processing by master device Transfer lines Processing by slave device 1 9 8 2 3 4 5 6 7 8 9 3 2 1 D7 D0 D6 D5 D4 D3 D2 D1 D0 D5 D6 D7 IIC0 data IIC0 FFH IIC0 FFH IIC0 data Transmit Receive Note Note ACK ACK Note Note Note To cancel slave wait writ...

Page 473: ... H H H L ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 AD5 AD6 IIC0 data IIC0 address IIC0 FFH Note IIC0 FFH Note Stop condition Start condition Transmit Note Note When SPIE0 1 Receive When SPIE0 1 ACK Note To c...

Page 474: ...ess IIC0 ACKD0 STD0 SPD0 WTIM0 H H L L L H L ACKE0 MSTS0 STT0 L L SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 4 5 6 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R D4 D3 D2 D5 D6 D7 IIC0 address IIC0 FFH Note Note IIC0 data Start condition ACK Note To cancel master ...

Page 475: ...PD0 WTIM0 H H H L L L L L L L H H L L L L L ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 Processing by master device Transfer lines Processing by slave device 1 8 9 2 3 4 5 6 7 8 9 3 2 1 D7 D0 ACK D6 D5 D4 D3 D2 D1 D0 ACK D5 D6 D7 Note Note Receive Transmit IIC0 data IIC0 data IIC0 FFH Note IIC0 FFH Note Note To cancel maste...

Page 476: ...on IIC0 ACKD0 STD0 SPD0 WTIM0 H H L L L ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8 9 1 D7 D6 D5 D4 D3 D2 D1 D0 AD6 IIC0 address IIC0 FFH Note Note IIC0 data Stop condition Start condition When SPIE0 1 NACK When SPIE0 1 Note To cancel mast...

Page 477: ...6 bits 16 bits 32 bits multiplication 32 bits 16 bits 32 bits 16 bit remainder division 18 2 Configuration of Multiplier Divider The multiplier divider includes the following hardware Table 18 1 Configuration of Multiplier Divider Item Configuration Registers Remainder data register 0 SDR0 Multiplication division data registers A0 MDA0H MDA0L Multiplication division data registers B0 MDB0 Control ...

Page 478: ...iplier Divider Internal bus CPU clock Start Clear 17 bit adder Controller Multiplication division data register B0 MDB0 MDB0H MDB0L Remainder data register 0 SDR0 SDR0H SDR0L 6 bit counter DMUSEL0 Multiplier divider control register 0 DMUC0 Controller Multiplication division data register A0 MDA0H MDA0HH MDA0HL MDA0L MDA0LH MDA0LL Controller DMUE MDA000 INTDMU ...

Page 479: ...ister A0 MDA0H MDA0L MDA0 is a 32 bit register that sets a 16 bit multiplier A in the multiplication mode and a 32 bit dividend in the division mode and stores the 32 bit result of the operation higher 16 bits MDA0H lower 16 bits MDA0L Figure 18 3 Format of Multiplication Division Data Register A0 MDA0H MDA0L Address FF62H FF63H FF64H FF65H After reset 0000H 0000H R W Symbol FF65H MDA0HH FF64H MDA...

Page 480: ...lock is input when bit 7 DMUE of multiplier divider control register 0 DMUC0 is set to 1 MDA0H and MDA0L can be set by an 8 bit or 16 bit memory manipulation instruction Reset signal generation clears MDA0H and MDA0L to 0000H 3 Multiplication division data register B0 MDB0 MDB0 is a register that stores a 16 bit multiplier B in the multiplication mode and a 16 bit divisor in the division mode MDB0...

Page 481: ... reset 00H R W Symbol 4 3 2 1 0 6 7 5 Note When DMUE is set to 1 the operation is started DMUE is automatically cleared to 0 after the operation is complete Cautions 1 If DMUE is cleared to 0 during operation processing when DMUE is 1 the operation result is not guaranteed If the operation is completed while the clearing instruction is being executed the operation result is guaranteed provided tha...

Page 482: ...on 3 The operation will be completed when 16 internal clocks have been issued after the start of the operation intermediate data is stored in the MDA0L and MDA0H registers during operation and therefore the read values of these registers are not guaranteed End of operation 4 The operation result data is stored in the MDA0L and MDA0H registers 5 DMUE is cleared to 0 end of operation 6 After the ope...

Page 483: ...ration clock MDA0 SDR0 MDB0 1 2 3 4 5 6 7 8 9 A B C D E F 10 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 006D 0000 00DA XXXX 00DA XXXX XXXX XXXX 0049 8036 0024 C01B 005B E00D 0077 7006 003B B803 0067 5C01 007D 2E00 003E 9700 001F 4B80 000F A5C0 0007 D2E0 0003 E970 0001 F4B8 0000 FA5C 0000 7D2E 0093 XXXX Internal clock DMUE DMUSEL0 Counter INTDMU ...

Page 484: ... be completed when 32 internal clocks have been issued after the start of the operation intermediate data is stored in the MDA0L and MDA0H registers and remainder data register 0 SDR0 during operation and therefore the read values of these registers are not guaranteed End of operation 4 The result data is stored in the MDA0L MDA0H and SDR0 registers 5 DMUE is cleared to 0 end of operation 6 After ...

Page 485: ...eration clock MDA0 SDR0 MDB0 1 2 3 4 5 6 7 8 19 1A 1B 1C 1D 1E 1F 20 0 0 0000 0001 0003 0006 000D 0003 0007 000E 0004 000B 0016 0014 0010 0008 0011 000B 0016 B974 4B0C DCBA 2586 XXXX XXXX XXXX 72E8 9618 E5D1 2C30 CBA2 5860 9744 B0C1 2E89 6182 5D12 C304 BA25 8609 0C12 64D8 1824 C9B0 3049 9361 6093 26C3 C126 4D87 824C 9B0E 0499 361D 0932 6C3A 0018 XXXX Internal clock DMUE DMUSEL0 Counter INTDMU ...

Page 486: ...upt servicing For the priority order see Table 19 1 A standby release signal is generated and STOP and HALT modes are released External interrupt requests and internal interrupt requests are provided as maskable interrupts µPD78F0531 78F0532 78F0533 External 9 internal 16 µPD78F0534 78F0535 78F0536 78F0537 78F0537D External 9 internal 19 2 Software interrupt This is a vectored interrupt generated ...

Page 487: ...TM000 Match between TM00 and CR000 when compare register is specified TI010 pin valid edge detection when capture register is specified 0020H 15 INTTM010 Match between TM00 and CR010 when compare register is specified TI000 pin valid edge detection when capture register is specified 0022H 16 INTAD End of A D conversion 0024H 17 INTSR0 End of UART0 reception or reception error generation 0026H 18 I...

Page 488: ...7 INTTM011 Note3 Match between TM01 and CR011 when compare register is specified TI001 pin valid edge detection when capture register is specified Internal 003AH A Software BRK BRK instruction execution 003EH D RESET Reset input POC Power on clear LVI Low voltage detection Note 4 Reset WDT WDT overflow 0000H Notes 1 The default priority is the priority applicable when two or more maskable interrup...

Page 489: ...troller Vector table address generator Standby release signal B External maskable interrupt INTP0 to INTP7 Internal bus Interrupt request IF MK IE PR ISP Priority controller Vector table address generator Standby release signal External interrupt edge enable register EGP EGN Edge detector IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Prio...

Page 490: ...terrupt request Priority controller Vector table address generator Standby release signal Key interrupt detector 1 when KRMn 1 n 0 to 7 D Software interrupt Internal bus Interrupt request Priority controller Vector table address generator IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority specification flag KRM Key return mode registe...

Page 491: ...st flag register IF0L IF0H IF1L IF1H Interrupt mask flag register MK0L MK0H MK1L MK1H Priority specification flag register PR0L PR0H PR1L PR1H External interrupt rising edge enable register EGP External interrupt falling edge enable register EGN Program status word PSW Table 19 2 shows a list of interrupt request flags interrupt mask flags and priority specification flags corresponding to interrup...

Page 492: ...IFH1 TMMKH1 TMPRH1 INTTMH0 TMIFH0 TMMKH0 TMPRH0 INTTM50 TMIF50 TMMK50 TMPR50 INTTM000 TMIF000 TMMK000 TMPR000 INTTM010 TMIF010 TMMK010 TMPR010 INTAD ADIF IF1L ADMK MK1L ADPR PR1L INTSR0 SRIF0 SRMK0 SRPR0 INTWTI WTIIF WTIMK WTIPR INTTM51 TMIF51 TMMK51 TMPR51 INTKR KRIF KRMK KRPR INTWT WTIF WTMK WTPR INTP6 PIF6 PMK6 PPR6 INTP7 PIF7 PMK7 PPR7 INTIIC0 IICIF0 IICMK0 IICPR0 INTDMU Note 3 DMUIF Note 3 IF...

Page 493: ...0L IF0H IF1L IF1H Address FFE0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0L SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF Address FFE1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0H TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 DUALIF0 CSIIF10 STIF0 STIF6 SRIF6 Address FFE2H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF1L PIF7 PIF6 WTIF KRIF TMIF51 WTIIF SRIF0 ADIF Address FFE3H After reset 00H R W Symb...

Page 494: ...a 1 bit memory manipulation instruction CLR1 If a program is described in C language using an 8 bit memory manipulation instruction such as IF0L 0xfe and compiled it becomes the assembler of three instructions mov a IF0L and a 0FEH mov IF0L a In this case even if the request flag of another bit of the same interrupt request flag register IF0L is set to 1 at the timing between mov a IF0L and mov IF...

Page 495: ... After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0L SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK Address FFE5H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1 DUALMK0 CSIMK0 STMK0 STMK6 SRMK6 Address FFE6H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK1L PMK7 PMK6 WTMK KRMK TMMK51 WTIMK SRMK0 ADMK Address FFE7H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK1H 1 1 1 1 ...

Page 496: ...PR1L PR1H Address FFE8H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0L SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 LVIPR Address FFE9H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0H TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1 DUALPR0 CSIPR10 STPR0 STPR6 SRPR6 Address FFEAH After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR1L PPR7 PPR6 WTPR KRPR TMPR51 WTIPR SRPR0 ADPR Address FFEBH After reset FFH R W Symbol 7 6 5...

Page 497: ...EGP2 EGP1 EGP0 Address FF49H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGN EGN7 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 EGPn EGNn INTPn pin valid edge selection n 0 to 7 0 0 Edge detection disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both rising and falling edges Table 19 3 shows the ports corresponding to EGPn and EGNn Table 19 3 Ports Corresponding to EGPn and EGNn Detection Enable Register Edge De...

Page 498: ...ed into a stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag The PSW contents are also saved into the stack with the PUSH PSW instruction They are restored from the stack with the RETI RETB and POP PSW instructions Reset signal generation sets PSW to 02H Fi...

Page 499: ...e When PR 0 7 clocks 32 clocks When PR 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction the wait time becomes longer Remark 1 clock 1 fCPU fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request with a higher priority level specified in the priority specification flag is acknowledged first If two or more inte...

Page 500: ...uest held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Vectored interrupt servicing Any high priority interrupt request among those simultaneously generated Any high priority interrupt request among those simultaneously generated with PR 0 IF Interrupt request flag MK Interrupt mask flag PR Priority specificatio...

Page 501: ...rrupt servicing program CPU processing IF PR 1 IF PR 0 6 clocks 25 clocks Remark 1 clock 1 fCPU fCPU CPU clock 19 4 2 Software interrupt request acknowledgement A software interrupt acknowledge is acknowledged by BRK instruction execution Software interrupts cannot be disabled If a software interrupt request is acknowledged the contents are saved into the stacks in the order of the program status ...

Page 502: ...t currently being serviced is generated during interrupt servicing it is not acknowledged for multiple interrupt servicing Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending When servicing of the current interrupt ends the pending interrupt request is acknowledged following execution of at least one ...

Page 503: ...knowledged the EI instruction must always be issued to enable interrupt request acknowledgment Example 2 Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing INTxx PR 0 INTyy PR 1 EI RETI IE 0 IE 0 EI 1 instruction execution RETI IE 1 IE 1 Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because it...

Page 504: ...EI 1 instruction execution RETI RETI INTxx PR 0 INTyy PR 0 IE 0 IE 0 IE 1 IE 1 Interrupts are not enabled during servicing of interrupt INTxx EI instruction is not issued therefore interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one main processing instruction PR ...

Page 505: ...IF0H IF1L IF1H MK0L MK0H MK1L MK1H PR0L PR0H PR1L and PR1H registers Caution The BRK instruction is not one of the above listed interrupt request hold instructions However the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared Therefore even if a maskable interrupt request is generated during execution of the BRK instruction the interrupt request is not ...

Page 506: ...al in 1 bit units KRM2 Controls KR2 signal in 1 bit units KRM3 Controls KR3 signal in 1 bit units KRM4 Controls KR4 signal in 1 bit units KRM5 Controls KR5 signal in 1 bit units KRM6 Controls KR6 signal in 1 bit units KRM7 Controls KR7 signal in 1 bit units 20 2 Configuration of Key Interrupt The key interrupt includes the following hardware Table 20 2 Configuration of Key Interrupt Item Configura...

Page 507: ...M7 Does not detect key interrupt signal Detects key interrupt signal KRMn 0 1 Key interrupt mode control KRM KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Address FF6EH After reset 00H R W Symbol 7 6 5 4 3 2 0 Cautions 1 If any of the KRM0 to KRM7 bits used is set to 1 set bits 0 to 7 PU70 to PU77 of the corresponding pull up resistor register 7 PU7 to 1 2 If KRM is changed the interrupt request flag may be ...

Page 508: ...ure the oscillation stabilization time after the STOP mode is released when the X1 clock is selected select the HALT mode if it is necessary to start processing immediately upon interrupt request generation In either of these two modes all the contents of registers flags and data memory just before the standby mode is set are held The I O port output latches and output buffer statuses are also hel...

Page 509: ...n time status fX 10 MHz fX 20 MHz 1 0 0 0 0 2 11 fX min 204 8 µs min 102 4 µs min 1 1 0 0 0 2 13 fX min 819 2 µs min 409 6 µs min 1 1 1 0 0 2 14 fX min 1 64 ms min 819 2 µs min 1 1 1 1 0 2 15 fX min 3 27 ms min 1 64 ms min 1 1 1 1 1 2 16 fX min 6 55 ms min 3 27 ms min Cautions 1 After the above time has elapsed the bits are set to 1 in order from MOST11 and remain 1 2 The oscillation stabilization...

Page 510: ...me selection fX 10 MHz fX 20 MHz 0 0 1 2 11 fX 204 8 µs 102 4 µs 0 1 0 2 13 fX 819 2 µs 409 6 µs 0 1 1 2 14 fX 1 64 ms 819 2 µs 1 0 0 2 15 fX 3 27 ms 1 64 ms 1 0 1 2 16 fX 6 55 ms 3 27 ms Other than above Setting prohibited Cautions 1 To set the STOP mode when the X1 clock is used as the CPU clock set OSTS before executing the STOP instruction 2 Do not change the value of the OSTS register during ...

Page 511: ... 21 2 1 HALT mode 1 HALT mode The HALT mode is set by executing the HALT instruction HALT mode can be set regardless of whether the CPU clock before the setting was the high speed system clock internal high speed oscillation clock or subsystem clock The operating statuses in the HALT mode are shown below ...

Page 512: ...as set is retained Subsystem clock fEXCLKS Operates or stops by external clock input fRL Status before HALT mode was set is retained CPU Operation stopped Flash memory Operation stopped RAM Status before HALT mode was set is retained Port latch Status before HALT mode was set is retained 00 16 bit timer event counter 01 Note 50 8 bit timer event counter 51 H0 8 bit timer H1 Watch timer Operable Wa...

Page 513: ...as set is retained 00 Note1 16 bit timer event counter 01 Note1 2 50 Note1 8 bit timer event counter 51 Note1 H0 8 bit timer H1 Watch timer Operable Watchdog timer Operable Clock supply to watchdog timer stops when internal low speed oscillator can be stopped by software is set by option byte Clock output Operable Buzzer output A D converter Operable However operation disabled when peripheral hard...

Page 514: ...ext address instruction is executed Figure 21 3 HALT Mode Release by Interrupt Request Generation HALT instruction Wait Wait Operating mode HALT mode Operating mode Oscillation High speed system clock internal high speed oscillation clock or subsystem clock Status of CPU Standby release signal Interrupt request Remarks 1 The broken lines indicate the case when the interrupt request which has relea...

Page 515: ...d Starting X1 oscillation is specified by software Reset processing 20 s TYP µ 2 When internal high speed oscillation clock is used as CPU clock HALT instruction Reset signal Internal high speed oscillation clock Normal operation internal high speed oscillation clock HALT mode Reset period Normal operation internal high speed oscillation clock Oscillates Oscillation stopped Oscillates Status of CP...

Page 516: ...uses The STOP mode is set by executing the STOP instruction and it can be set only when the CPU clock before the setting was the main system clock Caution Because the interrupt request signal is used to clear the standby mode if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset the standby mode is immediately cleared if set Thus the STOP mode is res...

Page 517: ...is selected as the count clock H0 Operable only when TM50 output is selected as the count clock during 8 bit timer event counter 50 operation 8 bit timer H1 Operable only when fRL fRL 2 7 fRL 2 9 is selected as the count clock Watch timer Operable only when subsystem clock is selected as the count clock Watchdog timer Operable Clock supply to watchdog timer stops when internal low speed oscillator...

Page 518: ...ock to the high speed system clock X1 oscillation after the STOP mode is released check the oscillation stabilization time with the oscillation stabilization time counter status register OSTC 4 If the STOP instruction is executed with AMPH set to 1 when the internal high speed oscillation clock or external main system clock is used as the CPU clock the internal high speed oscillation clock or exte...

Page 519: ... mode high speed system clock Oscillates Oscillates STOP instruction STOP mode Wait set by OSTS Standby release signal Oscillation stabilization wait HALT mode status Oscillation stopped High speed system clock X1 oscillation Status of CPU Oscillation stabilization time set by OSTS 2 When internal high speed oscillation clock is used as CPU clock Normal operation internal high speed oscillation cl...

Page 520: ...rting X1 oscillation is specified by software Oscillation stopped Reset processing 20 s TYP µ 2 When internal high speed oscillation clock is used as CPU clock STOP instruction Reset signal Internal high speed oscillation clock Normal operation internal high speed oscillation clock STOP mode Reset period Normal operation internal high speed oscillation clock Oscillates Oscillation stopped Status o...

Page 521: ...evel is input to the RESET pin the device is reset It is released from the reset status when a high level is input to the RESET pin and program execution is started with the internal high speed oscillation clock after reset processing A reset by the watchdog timer is automatically released and program execution starts using the internal high speed oscillation clock see Figures 22 2 to 22 4 after r...

Page 522: ...ESF Internal bus Watchdog timer reset signal RESET Power on clear circuit reset signal Low voltage detector reset signal Reset signal Reset signal to LVIM LVIS register Clear Set Clear Set Caution An LVI circuit internal reset does not reset the LVI circuit Remarks 1 LVIM Low voltage detection register 2 LVIS Low voltage detection level selection register ...

Page 523: ...l before reset is effected the output signal of P130 can be dummy output as the CPU reset signal Figure 22 3 Timing of Reset Due to Watchdog Timer Overflow Normal operation Reset period oscillation stop CPU clock Watchdog timer overflow Internal reset signal Hi Z Port pin except P130 Port pin P130 Note High speed system clock when X1 oscillation is selected Internal high speed oscillation clock St...

Page 524: ...t pin P130 Note Starting X1 oscillation is specified by software Normal operation internal high speed oscillation clock Reset processing 20 s TYP Wait for oscillation accuracy stabilization Delay 5 s TYP µ µ Note Set P130 to high level output by software Remarks 1 When reset is effected P130 outputs a low level If P130 is set to output a high level before reset is effected the output signal of P13...

Page 525: ...ry RAM Operation stopped Port latch 00 16 bit timer event counter 01 Note 50 8 bit timer event counter 51 H0 8 bit timer H1 Watch timer Watchdog timer Clock output Buzzer output A D converter UART0 UART6 CSI10 CSI11 Note Serial interface IIC0 Multiplier divider Note Operation stopped Power on clear function Operable Low voltage detection function External interrupt Operation stopped Note µPD78F053...

Page 526: ...select register BANK 00H Clock operation mode select register OSCCTL 00H Processor clock control register PCC 01H Internal oscillation mode register RCM 80H Main OSC control register MOC 80H Main clock mode register MCM 00H Oscillation stabilization time counter status register OSTC 00H Oscillation stabilization time select register OSTS 05H Timer counters 00 01 TM00 TM01 0000H Capture compare reg...

Page 527: ...1H Asynchronous serial interface reception error status register 0 ASIS0 00H Serial interface UART0 Baud rate generator control register 0 BRGC0 1FH Receive buffer register 6 RXB6 FFH Transmit buffer register 6 TXB6 FFH Asynchronous serial interface operation mode register 6 ASIM6 01H Asynchronous serial interface reception error status register 6 ASIS6 00H Asynchronous serial interface transmissi...

Page 528: ...detection register LVIM 00H Note 3 Low voltage detector Low voltage detection level selection register LVIS 00H Note 3 Request flag registers 0L 0H 1L 1H IF0L IF0H IF1L IF1H 00H Mask flag registers 0L 0H 1L 1H MK0L MK0H MK1L MK1H FFH Priority specification flag registers 0L 0H 1L 1H PR0L PR0H PR1L PR1H FFH External interrupt rising edge enable register EGP 00H Interrupt External interrupt falling ...

Page 529: ... 1 0 RESF 0 0 0 WDTRF 0 0 0 LVIRF WDTRF Internal reset request by watchdog timer WDT 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated LVIRF Internal reset request by low voltage detector LVI 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated Note The value after reset varies depending on the reset sou...

Page 530: ...e VDD and detection voltage VPOC 1 59 V 0 15 V generates internal reset signal when VDD VPOC and releases reset when VDD VPOC Caution If an internal reset signal is generated in the POC circuit the reset control flag register RESF is cleared to 00H Remark This product incorporates multiple hardware functions that generate an internal reset signal A flag that indicates the reset source is located i...

Page 531: ... VPOC 1 59 V 0 15 V the reset status is released The supply voltage VDD and detection voltage VPOC 1 59 V 0 15 V are compared When VDD VPOC the internal reset signal is generated It is released when VDD VPOC 2 In 2 7 V 1 59 V POC mode option byte POCMODE 1 An internal reset signal is generated on power application When the supply voltage VDD exceeds the detection voltage VDDPOC 2 7 V 0 2 V the res...

Page 532: ... be used for reset Set LVI to be used for reset Set LVI to be used for interrupt Wait for oscillation accuracy stabilization Internal reset signal Reset processing 20 s TYP µ Reset processing 20 s TYP µ Reset processing 20 s TYP µ Notes 1 The operation guaranteed range is 1 8 V VDD 5 5 V To make the state at lower than 1 8 V reset state when the supply voltage falls use the reset function of the l...

Page 533: ...e 1 Wait for oscillation accuracy stabilization Wait for oscillation accuracy stabilization Wait for oscillation accuracy stabilization Reset processing 20 s TYP µ Reset processing 20 s TYP µ Reset processing 20 s TYP µ Set LVI to be used for reset Set LVI to be used for reset Set LVI to be used for interrupt Notes 1 The operation guaranteed range is 1 8 V VDD 5 5 V To make the state at lower than...

Page 534: ...ounter that uses a timer and then initialize the ports Figure 23 3 Example of Software Processing After Reset Release 1 2 If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Check the reset sourceNote 2 Initialize the port Note 1 Reset Initialization processing 1 50 ms has passed TMIFH1 1 Initialization processing 2 Setting 8 bit timer H1 to measure 50 ms Setting of...

Page 535: ...re 23 3 Example of Software Processing After Reset Release 2 2 Checking reset source Yes No Check reset source Power on clear external reset generated Reset processing by watchdog timer Reset processing by low voltage detector No WDTRF of RESF register 1 LVIRF of RESF register 1 Yes ...

Page 536: ... EXLVI VEXLVI The supply voltage VDD or voltage input from an external input pin EXLVI can be selected by software Interrupt or reset function can be selected by software Operable in STOP mode When the low voltage detector is used to reset bit 0 LVIRF of the reset control flag register RESF is set to 1 if reset occurs For details of RESF see CHAPTER 22 RESET FUNCTION 24 2 Configuration of Low Volt...

Page 537: ...Manual U17260EJ3V1UD 537 24 3 Registers Controlling Low Voltage Detector The low voltage detector is controlled by the following registers Low voltage detection register LVIM Low voltage detection level selection register LVIS Port mode register 12 PM12 ...

Page 538: ...n voltage VLVI LVISEL 1 Generates internal reset signal when input voltage from external input pin EXLVI detection voltage VEXLVI LVIF Note 4 Low voltage detection flag 0 LVISEL 0 Supply voltage VDD detection voltage VLVI or when operation is disabled LVISEL 1 Input voltage from external input pin EXLVI detection voltage VEXLVI or when operation is disabled 1 LVISEL 0 Supply voltage VDD detection ...

Page 539: ...on level 0 0 0 0 VLVI0 4 24 V 0 1 V 0 0 0 1 VLVI1 4 09 V 0 1 V 0 0 1 0 VLVI2 3 93 V 0 1 V 0 0 1 1 VLVI3 3 78 V 0 1 V 0 1 0 0 VLVI4 3 62 V 0 1 V 0 1 0 1 VLVI5 3 47 V 0 1 V 0 1 1 0 VLVI6 3 32 V 0 1 V 0 1 1 1 VLVI7 3 16 V 0 1 V 1 0 0 0 VLVI8 3 01 V 0 1 V 1 0 0 1 VLVI9 2 85 V 0 1 V 1 0 1 0 VLVI10 2 70 V 0 1 V 1 0 1 1 VLVI11 2 55 V 0 1 V 1 1 0 0 VLVI12 2 39 V 0 1 V 1 1 0 1 VLVI13 2 24 V 0 1 V 1 1 1 0 V...

Page 540: ...w Voltage Detector The low voltage detector can be used in the following two modes 1 Used as reset If LVISEL 0 compares the supply voltage VDD and detection voltage VLVI generates an internal reset signal when VDD VLVI and releases internal reset when VDD VLVI If LVISEL 1 compares the input voltage from external input pin EXLVI and detection voltage VEXLVI 1 21 V TYP generates an internal reset si...

Page 541: ...ked that supply voltage VDD detection voltage VLVI by bit 0 LVIF of LVIM 7 Set bit 1 LVIMD of LVIM to 1 generates internal reset signal when supply voltage VDD detection voltage VLVI Figure 24 5 shows the timing of the internal reset signal generated by the low voltage detector The numbers in this timing chart correspond to 1 to 7 above Cautions 1 1 must always be executed When LVIMK 0 an interrup...

Page 542: ...d by software Not cleared Not cleared Not cleared Not cleared Cleared by software 4 7 Clear Clear Clear 5 Wait time LVION flag set by software LVIMD flag set by software HNote 1 L LVISEL flag set by software 6 2 VLVI VPOC 1 59 V TYP Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The LVIF flag may be set 1 3 LVIRF is bit 0 of the reset control flag register RESF For details of RESF...

Page 543: ...ared by software Not cleared Not cleared Not cleared Not cleared Cleared by software 4 7 Clear Clear Clear 5 Wait time LVION flag set by software LVIMD flag set by software HNote 1 L LVISEL flag set by software 6 2 2 7 V TYP VPOC 1 59 V TYP Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The LVIF flag may be set 1 3 LVIRF is bit 0 of the reset control flag register RESF For details...

Page 544: ...wait for an operation stabilization time 10 µs MAX Note 5 Wait until it is checked that input voltage from external input pin EXLVI detection voltage VEXLVI 1 21 V TYP by bit 0 LVIF of LVIM 6 Set bit 1 LVIMD of LVIM to 1 generates internal reset signal when input voltage from external input pin EXLVI detection voltage VEXLVI 1 21 V TYP Figure 24 6 shows the timing of the internal reset signal gene...

Page 545: ...ot cleared Not cleared Not cleared Not cleared Cleared by software 3 6 LVION flag set by software LVIMD flag set by software HNote 1 LVISEL flag set by software 5 2 Not cleared Not cleared 4 Wait time Not cleared Not cleared Not cleared Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The LVIF flag may be set 1 3 LVIRF is bit 0 of the reset control flag register RESF For details of ...

Page 546: ...ilization time 10 µs MAX 6 Confirm that supply voltage VDD detection voltage VLVI at bit 0 LVIF of LVIM 7 Clear the interrupt request flag of LVI LVIIF to 0 8 Release the interrupt mask flag of LVI LVIMK 9 Clear bit 1 LVIMD of LVIM to 0 generates interrupt signal when supply voltage VDD detection voltage VLVI default value 10 Execute the EI instruction when vector interrupts are used Figure 24 7 s...

Page 547: ...INTLVI LVIIF flag Internal reset signal 4 6 7 Cleared by software 5 Wait time LVION flag set by software Note 2 Note 2 3 L LVISEL flag set by software 2 LVIMD flag set by software L 9 VLVI VPOC 1 59 V TYP Note 2 Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The interrupt request signal INTLVI is generated and the LVIF and LVIIF flags may be set 1 Remark 1 to 9 in Figure 24 7 abov...

Page 548: ...TLVI LVIIF flag Internal reset signal 4 6 7 Cleared by software 5 Wait time LVION flag set by software Note 2 Note 2 3 L LVISEL flag set by software 2 LVIMD flag set by software L 9 VLVI 2 7 V TYP VPOC 1 59 V TYP Note 2 Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The interrupt request signal INTLVI is generated and the LVIF and LVIIF flags may be set 1 Remark 1 to 9 in Figure 2...

Page 549: ...1 V TYP at bit 0 LVIF of LVIM 6 Clear the interrupt request flag of LVI LVIIF to 0 7 Release the interrupt mask flag of LVI LVIMK 8 Clear bit 1 LVIMD of LVIM to 0 generates interrupt signal when supply voltage VDD detection voltage VLVI default value 9 Execute the EI instruction when vector interrupts are used Figure 24 8 shows the timing of the interrupt signal generated by the low voltage detect...

Page 550: ...ag set by software LVIF flag INTLVI LVIIF flag 3 5 6 Cleared by software 4 Wait time LVION flag set by software Note 2 Note 2 LVISEL flag set by software 2 LVIMD flag set by software L 8 Note 2 Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The interrupt request signal INTLVI is generated and the LVIF and LVIIF flags may be set 1 Remark 1 to 8 in Figure 24 8 above correspond to 1 ...

Page 551: ...e reset signal wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer and then initialize the ports see Figure 24 9 2 When used as interrupt a Check that supply voltage VDD detection voltage VLVI in the servicing routine of the LVI interrupt by using bit 0 LVIF of the low voltage detection register LVIM Clear bit 0 LVIIF of interrupt request ...

Page 552: ...0 ms has passed TMIFH1 1 Initialization processing 2 Setting 8 bit timer H1 to measure 50 ms Setting of division ratio of system clock such as setting of timer or A D converter Yes No Setting LVI Clearing WDT Detection voltage or higher LVIF 0 Yes LVIF 0 Restarting timer H1 TMHE1 0 TMHE1 1 No The low voltage detection flag is cleared The timer counter is cleared and the timer is started LVI reset ...

Page 553: ...e 24 9 Example of Software Processing After Reset Release 2 2 Checking reset source Yes No Check reset source Power on clear external reset generated Reset processing by watchdog timer Reset processing by low voltage detector Yes WDTRF of RESF register 1 LVIRF of RESF register 1 No ...

Page 554: ...f the supply voltage rises to 1 8 V after power application at a pace slower than 0 5 V ms MAX use of the 2 7 V 1 59 V POC mode is recommended During 1 59 V POC mode operation POCMODE 0 The device is in the reset state upon power application and until the supply voltage reaches 1 59 V TYP It is released from the reset state when the voltage exceeds 1 59 V TYP After that POC is detected at 1 59 V T...

Page 555: ...tor operation 0 Can be stopped by software stopped when 1 is written to bit 0 LSRSTOP of RCM register 1 Cannot be stopped not stopped even if 1 is written to LSRSTOP bit Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the boot swap operation Cautions 1 The combination of WDCS2 WDCS1 WDCS0 0 and WINDOW1 WINDOW0 0 is prohibited 2 The watchdog t...

Page 556: ...00H to 0082H and 0083H as these addresses are reserved areas Also set 00H to 1082 and 1083H because 0082H and 0083H are switched with 1082H and 1083H when the boot swap operation is used Address 0084H 1084H Notes1 2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 OCDEN1 OCDEN0 OCDEN1 OCDEN0 On chip debug operation control 0 0 Operation disabled 0 1 Setting prohibited 1 0 Operation enabled Does not erase data of the f...

Page 557: ...illegal access detection operation Window open period of watchdog timer 50 Overflow time of watchdog timer 210 fRL Internal low speed oscillator can be stopped by software DB 00H 1 59 V POC mode DB 00H Reserved area DB 00H Reserved area DB 00H On chip debug operation disabled Remark Referencing of the option byte is performed during reset processing For the reset processing timing see CHAPTER 22 R...

Page 558: ...ch product to the values shown in Table 26 1 after a reset release Figure 26 1 Format of Internal Memory Size Switching Register IMS Address FFF0H After reset CFH R W Symbol 7 6 5 4 3 2 1 0 IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 Internal high speed RAM capacity selection 0 0 0 768 bytes 1 1 0 1024 bytes Other than above Setting prohibited ROM3 ROM2 ROM1 ROM0 Internal ROM capacity ...

Page 559: ...PD78F0533 C8H µPD78F0534 CCH µPD78F0535 CFH µPD78F0536 CCH Note µPD78F0537 78F0537D CCH Note Note The µPD78F0536 µPD78F0537 and 78F0537D have internal ROMs of 96 KB and 128 KB respectively However the set values for the IMS of these devices is the same as those for the 48 KB product because memory banks are used For how to set the memory banks see Figure 4 2 Format of Memory Bank Select Register B...

Page 560: ...gister IXS Address FFF4H After reset 0CH R W Symbol 7 6 5 4 3 2 1 0 IXS 0 0 0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 Internal expansion RAM capacity selection 0 1 1 0 0 0 byte 0 1 0 1 0 1024 bytes 0 1 0 0 0 2048 bytes 0 0 1 0 0 4096 bytes 0 0 0 0 0 6144 bytes Other than above Setting prohibited Caution To set memory size set IMS and then IXS Set memory size so that t...

Page 561: ...0 KE2 and Dedicated Flash Programmer Pin Configuration of Dedicated Flash Programmer With CSI10 With UART6 Signal Name I O Pin Function Pin Name Pin No Pin Name Pin No SI RxD Input Receive signal SO10 P12 44 TxD6 P13 43 SO TxD Output Transmit signal SI10 RxD0 P11 45 RxD6 P14 42 SCK Output Transfer clock SCK10 TxD0 P10 46 CLK Output Clock to 78K0 KE2 Note 1 EXCLK X2 P122 Note 2 10 RESET Output Rese...

Page 562: ...wn below Figure 26 3 Example of Wiring Adapter for Flash Memory Writing in 3 Wire Serial I O CSI10 Mode GND VDD VDD2 WRITER INTERFACE VDD 2 7 to 5 5 V GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SI SO SCK CLK RESET FLMD0 ...

Page 563: ...r for Flash Memory Writing in UART UART6 Mode GND VDD VDD2 WRITER INTERFACE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SI SO SCK CLK RESET FLMD0 VDD 2 7 to 5 5 V ...

Page 564: ... To interface between the dedicated flash programmer and the 78K0 KE2 CSI10 or UART6 is used for manipulation such as writing and erasing To write the flash memory off board a dedicated program adapter FA series is necessary 26 5 Communication Mode Communication between the dedicated flash programmer and the 78K0 KE2 is established by serial communication via CSI10 or UART6 of the 78K0 KE2 1 CSI10...

Page 565: ...ignal Name I O Pin Function Pin Name CSI10 UART6 FLMD0 Output Mode signal FLMD0 VDD I O VDD voltage generation power monitoring VDD EVDD AVREF GND Ground VSS EVSS AVSS CLK Output Clock output to 78K0 KE2 EXCLK Note 1 Note 2 RESET Output Reset signal RESET SI RxD Input Receive signal SO10 TxD6 SO TxD Output Transmit signal SI10 RxD6 SCK Output Transfer clock SCK10 Notes 1 Only the internal high spe...

Page 566: ... the pins must be handled as described below 26 6 1 FLMD0 pin In the normal operation mode 0 V is input to the FLMD0 pin In the flash memory programming mode the VDD write voltage is supplied to the FLMD0 pin An FLMD0 pin connection example is shown below Figure 26 8 FLMD0 Pin Connection Example 78K0 KE2 FLMD0 Dedicated flash programmer connection pin 26 6 2 Serial interface pins The pins used by ...

Page 567: ...Therefore isolate the signal of the other device 78K0 KE2 2 Malfunction of other device If the dedicated flash programmer output or input is connected to a pin input or output of a serial interface connected to another device input a signal may be output to the other device causing the device to malfunction To avoid this malfunction isolate the connection with the other device Figure 26 10 Malfunc...

Page 568: ...r the same status as that immediately after reset If external devices connected to the ports do not recognize the port status immediately after reset the port pin must be connected to VDD or VSS via a resistor 26 6 5 REGC pin Connect the REGC pin to GND via a capacitor 0 47 µF target in the same manner as during normal operation 26 6 6 Other signal pins Connect X1 and X2 in the same status as in t...

Page 569: ...sh memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer set the 78K0 KE2 in the flash memory programming mode To set the mode set the FLMD0 pin to VDD and clear the reset signal Change the mode by using a jumper when writing the flash memory on board Figure 26 13 Flash Memory Programming Mode VDD RESET 5 5 V 0 V VDD 0 V Flash memory programmin...

Page 570: ... fX 0 UART UART6 UART ch0 115200 bps Note 3 TxD6 RxD6 fEXCLK 3 3 wire serial I O CSI10 SIO ch0 2 4 kHz to 2 5 MHz Optional 1 to 20 MHz Note 2 1 0 SO10 SI10 SCK10 fRH 8 Notes 1 Selection items for Standard settings on FlashPro4 2 The possible setting range differs depending on the voltage For details refer to the chapter of electrical specifications 3 Because factors other than the baud rate error ...

Page 571: ...Erases the contents of the entire memory Blank check Batch blank check command Checks the erasure status of the entire memory High speed write command Writes data by specifying the write address and number of bytes to be written and executes a verify check Data write Successive write command Writes data from the address following that of the high speed write command executed immediately before and...

Page 572: ...flash memory is prohibited by this setting This prohibition setting can be cancelled using the batch erase chip erase command Disabling rewriting boot cluster 0 Execution of the batch erase chip erase command block erase command and write command on boot cluster 0 0000H to 0FFFH in the flash memory is prohibited by this setting Caution If a security setting that rewrites boot cluster 0 has been ap...

Page 573: ...rd Off Board Programming Self Programming Programming Mode Security Setting Security Setting Security Operation Security Setting Security Operation Disabling batch erase chip erase Disabling block erase Disabling write Disabled Invalid Note 2 Disabling rewriting boot cluster 0 Enabled Valid Note 1 Enabled Valid Notes 1 Execution of each command is prohibited by the security setting 2 Execution of ...

Page 574: ... that is not masked even in the DI status To prevent this mask the interrupt by using the interrupt mask flag registers MK0L MK0H MK1L and MK1H 5 Self programming is executed with the internal high speed oscillation clock If the CPU operates with the X1 clock or external main system clock the oscillation stabilization wait time of the internal high speed oscillation clock elapses during self progr...

Page 575: ...RAM area Execute DI instruction FLMD0 pin High level Start self programming FLMD0 pin Low level Confirm library return value End of self programming Entry program user program Library Entry program user program Set parameters to entry RAM Execute library and access flash memory according to library contents No interrupt request Interrupt request Interrupt servicing Self programming being suspended...

Page 576: ... correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next If the program has been correctly written to boot cluster 0 restore the original boot area by using the set information function of the firmware of the 78K0 KE2 Note A boot cluster is a 4 KB area and boot clusters 0 and 1 are swapped by the boot swap function Boot cluster 0 0000H to 0FFFH O...

Page 577: ... 6 5 4 Boot program Boot program Boot program New boot program New boot program New boot program New boot program Boot program 3 2 1 0 7 6 5 4 Boot program Boot program Boot program New boot program New boot program New boot program New boot program Erasing block 0 Erasing block 1 Erasing block 2 Erasing block 3 3 2 1 0 7 6 5 4 Boot program Boot program Boot program New boot program New boot progr...

Page 578: ...debug function has been used given the issue of the number of times the flash memory can be rewritten NEC Electronics does not accept complaints concerning this product Figure 27 1 Connection Example of QB 78K0MINI and µPD78F0537D When OCD0A X1 and OCD0B X2 Are Used VDD PD78F0537D P31 FLMD0 OCD0A X1 OCD0B X2 Target reset RESET_IN X2 X1 FLMD0 RESET VDD RESET_OUT GND QB 78K0MINI target connector GND...

Page 579: ...g Security ID The µPD78F0537D has an on chip debug operation control flag in the flash memory at 0084H see CHAPTER 25 OPTION BYTE and an on chip debug security ID setting area at 0085H to 008EH When the boot swap function is used also set a value that is the same as that of 1084H and 1085H to 108EH in advance because 0084H 0085H to 008EH and 1084H and 1085H to 108EH are switched For details on the...

Page 580: ...When using a label be sure to write the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for specification Table 28 1 Operand Identifiers and Specification Methods Identifier Specification Method r rp sfr sfrp X R0 A R1 C R2 B R3 E R4 D R5 L R6 H R7 AX RP0 BC RP1 DE RP2 HL RP3 Sp...

Page 581: ...status word CY Carry flag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag Memory contents indicated by address or register contents in parentheses XH XL Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit data...

Page 582: ... 1 4 5 HL A A HL byte 2 8 9 A HL byte HL byte A 2 8 9 HL byte A A HL B 1 6 7 A HL B HL B A 1 6 7 HL B A A HL C 1 6 7 A HL C MOV HL C A 1 6 7 HL C A A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 A addr16 A DE 1 4 6 A DE A HL 1 4 6 A HL A HL byte 2 8 10 A HL byte A HL B 2 8 10 A HL B 8 bit data transfer XCH A HL C 2 8 10 A HL C Notes 1 When the internal high speed RAM area...

Page 583: ... 8 9 A CY A addr16 A HL 1 4 5 A CY A HL A HL byte 2 8 9 A CY A HL byte A HL B 2 8 9 A CY A HL B ADD A HL C 2 8 9 A CY A HL C A byte 2 4 A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr 2 4 5 A CY A saddr CY A addr16 3 8 9 A CY A addr16 C A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY 8 bit operation...

Page 584: ...Y A addr16 3 8 9 A CY A addr16 CY A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY SUBC A HL C 2 8 9 A CY A HL C CY A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A 2 4 r r A A saddr 2 4 5 A A saddr A addr16 3 8 9 A A addr16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B 8 bit operation AND A HL C 2 8 9 A A HL ...

Page 585: ... addr16 3 8 9 A A addr16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B XOR A HL C 2 8 9 A A HL C A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9 A addr16 A HL 1 4 5 A HL A HL byte 2 8 9 A HL byte A HL B 2 8 9 A HL B 8 bit operation CMP A HL C 2 8 9 A HL C Notes 1 When the internal high speed RAM area is accesse...

Page 586: ... A3 0 HL 3 0 HL 7 4 A3 0 HL 3 0 HL 7 4 Rotate ROL4 HL 2 10 12 A3 0 HL 7 4 HL 3 0 A3 0 HL 7 4 HL 3 0 ADJBA 2 4 Decimal Adjust Accumulator after Addition BCD adjustment ADJBS 2 4 Decimal Adjust Accumulator after Subtract CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit CY A bit 2 4 CY A bit CY PSW bit 3 7 CY PSW bit CY HL bit 2 6 7 CY HL bit saddr bit CY 3 6 8 saddr bit CY sfr bit CY 3 8 sf...

Page 587: ...t 2 4 CY CY A bit CY PSW bit 3 7 CY CY PSW bit XOR1 CY HL bit 2 6 7 CY CY HL bit saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 SET1 HL bit 2 6 8 HL bit 1 saddr bit 2 4 6 saddr bit 0 sfr bit 3 8 sfr bit 0 A bit 2 4 A bit 0 PSW bit 2 6 PSW bit 0 CLR1 HL bit 2 6 8 HL bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 Bit manipulate NOT1 CY 1 2 CY CY Notes 1 When t...

Page 588: ... 2 SP 1 PSW SP SP 1 PUSH rp 1 4 SP 1 rpH SP 2 rpL SP SP 2 PSW 1 2 PSW SP SP SP 1 R R R POP rp 1 4 rpH SP 1 rpL SP SP SP 2 SP word 4 10 SP word SP AX 2 8 SP AX Stack manipulate MOVW AX SP 2 8 AX SP addr16 3 6 PC addr16 addr16 2 6 PC PC 2 jdisp8 Unconditional branch BR AX 2 8 PCH A PCL X BC addr16 2 6 PC PC 2 jdisp8 if CY 1 BNC addr16 2 6 PC PC 2 jdisp8 if CY 0 BZ addr16 2 6 PC PC 2 jdisp8 if Z 1 Co...

Page 589: ...4 12 PC PC 4 jdisp8 if sfr bit 1 then reset sfr bit A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 then reset A bit PSW bit addr16 4 12 PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit BTCLR HL bit addr16 3 10 12 PC PC 3 jdisp8 if HL bit 1 then reset HL bit B addr16 2 6 B B 1 then PC PC 2 jdisp8 if B 0 C addr16 2 6 C C 1 then PC PC 2 jdisp8 if C 0 Conditional branch DBNZ saddr addr16 3 8 10 saddr saddr ...

Page 590: ...r16 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP INC DEC B C DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR ...

Page 591: ...drp MOVW MOVW addr16 MOVW SP MOVW MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand First Operand A bit sfr bit saddr bit PSW bit HL bit CY addr16 None A bit MOV1 BT BF BTCLR SET1 CLR1 sfr bit MOV1 BT BF BTCLR SET1 CLR1 saddr bit MOV1 BT BF BTCLR SET1 CLR1 PSW bit MOV1 BT BF BTCLR SET1 CLR1 HL bit MOV1 BT BF BTCLR SET1 CLR1...

Page 592: ...ch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand First Operand AX addr16 addr11 addr5 addr16 Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP EI DI HALT STOP ...

Page 593: ...0 to P27 P30 to P33 P40 to P43 P50 to P53 P70 to P77 P120 to P124 P140 P141 X1 X2 XT1 XT2 RESET 0 3 to VDD 0 3 Note V Input voltage VI2 P60 to P63 N ch open drain 0 3 to 6 5 V Output voltage VO 0 3 to VDD 0 3 Note V Analog input voltage VAN ANI0 to ANI7 0 3 to AVREF 0 3 Note and 0 3 to VDD 0 3 Note V Per pin 10 mA P00 to P04 P40 to P43 P120 P130 P140 P141 25 mA Output current high IOH Total of all...

Page 594: ...ating ambient temperature TA In flash memory programming mode 40 to 85 C Storage temperature Tstg 40 to 150 C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions t...

Page 595: ...CIFICATIONS TARGET Preliminary User s Manual U17260EJ3V1UD 595 X1 Oscillator Characteristics TA 40 to 85 C 1 8 V VDD EVDD 5 5 V VSS EVSS AVSS 0 V Resonator Recommended Circuit Parameter Conditions MIN Th1T MI9 0 V TJ G Th1T MI9 ...

Page 596: ...T2 C4 C3 Rd XT1 clock oscillation frequency fXT Note 32 32 768 35 kHz Note Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Cautions 1 When using the XT1 oscillator wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cros...

Page 597: ...P130 P140 P141 Note 3 1 8 V VDD 2 7 V 9 0 mA 4 0 V VDD 5 5 V 45 0 mA 2 7 V VDD 4 0 V 35 0 mA Total of P05 P06 P10 to P17 P30 to P33 P50 to P53 P60 to P63 P70 to P77 Note 3 1 8 V VDD 2 7 V 20 0 mA 4 0 V VDD 5 5 V 65 0 mA 2 7 V VDD 4 0 V 50 0 mA IOL1 Total of all pins Note 3 1 8 V VDD 2 7 V 29 0 mA Per pin for P20 to P27 AVREF VDD 0 4 mA Output current low Note 2 IOL2 Per pin for P121 to P124 0 4 mA...

Page 598: ...nit VIH1 P02 P12 P13 P15 P40 to P43 P50 to P53 P63 P121 to P124 0 7VDD VDD V VIH2 P00 P01 P03 to P06 P10 P11 P14 P16 P17 P30 to P33 P60 to P62 P70 to P77 P120 P140 P141 RESET 0 8VDD VDD V Input voltage high µPD78F0534 78F0535 78F0536 78F0537 78F0537D VIH3 P20 to P27 AVREF VDD 0 7AVREF AVREF V VIH1 P02 to P06 P12 P13 P15 P40 to P43 P50 to P53 P63 P121 to P124 0 7VDD VDD V VIH2 P00 P01 P10 P11 P14 P...

Page 599: ...tage low VOL3 P60 to P63 1 8 V VDD 2 7 V IOL1 2 0 mA 0 4 V ILIH1 P00 to P06 P10 to P17 P30 to P33 P40 to P43 P50 to P53 P60 to P63 P70 to P77 P120 P130 P140 P141 VI VDD 1 µA ILIH2 P20 to P27 VI AVREF VDD 1 µA P121 to 124 VI VDD I O port mode 1 µA Input leakage current high ILIH3 X1 X2 XT1 XT2 VI VDD OSC mode 20 µA ILIL1 P00 to P06 P10 to P17 P30 to P33 P40 to P43 P50 to P53 P60 to P63 P70 to P77 P...

Page 600: ...nal power supply VDD including the peripheral operation current however the current flowing into the pull up resistors of the port and A D converter is not included 2 Square wave input 3 When AMPH bit 0 of clock operation mode select register OSCCTL 0 4 When main system clock is stopped 5 Total current flowing into the internal power supply VDD including the peripheral operating current however th...

Page 601: ...evel width low level width tEXCLKSH tEXCLKSL 1 fEXCLKS 1 2 5 ns 4 0 V VDD 5 5 V 2 fsam 0 1 Note 3 µs TI000 TI010 TI001 Note 2 TI011 Note 2 input high level width low level width tTIH0 tTIL0 2 7 V VDD 4 0 V 2 fsam 0 2 Note 3 µs 4 0 V VDD 5 5 V 10 MHz 2 7 V VDD 4 0 V 10 MHz TI50 TI51 input frequency fTI5 1 8 V VDD 2 7 V 5 MHz 4 0 V VDD 5 5 V 50 ns 2 7 V VDD 4 0 V 50 ns TI50 TI51 input high level wid...

Page 602: ... 100 0 01 1 8 32 Supply voltage VDD V Cycle time T CY s Guaranteed operation range µ AC Timing Test Points Excluding External Main System Clock and External Subsystem Clock 0 8VDD 0 2VDD Test points 0 8VDD 0 2VDD External Main System Clock Timing External Subsystem Clock Timing EXCLK 0 7VDD MIN 0 3VDD MAX 1 fEXCLK tEXCLKL tEXCLKH 1 fEXCLKS tEXCLKSL tEXCLKSH EXCLKS 0 7VDD MIN 0 3VDD MAX ...

Page 603: ...3V1UD 603 TI Timing TI000 TI010 TI001Note TI011Note tTIL0 tTIH0 TI50 TI51 1 fTI5 tTIL5 tTIH5 Interrupt Request Input Timing INTP0 to INTP7 tINTL tINTH Key Interrupt Input Timing KR0 to KR7 tKR RESET Input Timing RESET tRSL Note µPD78F0534 78F0535 78F0536 78F0537 and 78F0537D only ...

Page 604: ...ception tSU DAT 0 0 µs Data hold time transmission Note 2 tHD DAT 0 47 4 0 0 23 1 00 µs Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MAX of tHD DAT is during normal transfer and a wait state is inserted in the ACK acknowledge timing d CSI1n master mode SCK1n internal clock output Parameter Symbol Conditions MIN TYP MA...

Page 605: ...P MAX Unit SCK1n cycle time tKCY2 400 ns SCK1n high low level width tKH2 tKL2 tKCY2 2 ns SI1n setup time to SCK1n tSIK2 80 ns SI1n hold time from SCK1n tKSI2 50 ns Delay time from SCK1n to SO1n output tKSO2 C 50 pF Note 120 ns Note C is the load capacitance of the SO1n output line Remark n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F0534 78F0535 78F0536 78F0537 78F0537D ...

Page 606: ...ming IIC0 tLOW tHIGH tHD STA Stop condition Start condition Restart condition Stop condition tSU DAT tSU STA tHD STA tHD DAT SCL0 SDA0 CSI1n SI1n SO1n tKCYm tKLm tKHm tSIKm tKSIm Input data tKSOm Output data SCK1n Remark m 1 2 n 0 µPD78F0531 78F0532 78F0533 n 0 1 µPD78F0534 78F0535 78F0536 78F0537 78F0537D ...

Page 607: ...0 6 FSR Full scale error Notes 1 2 EFS 2 3 V AVREF 2 7 V 0 6 FSR 4 0 V AVREF 5 5 V 2 5 LSB 2 7 V AVREF 4 0 V 4 5 LSB Integral non linearity error Note 1 ILE 2 3 V AVREF 2 7 V 6 5 LSB 4 0 V AVREF 5 5 V 1 5 LSB 2 7 V AVREF 4 0 V 2 0 LSB Differential non linearity error Note 1 DLE 2 3 V AVREF 2 7 V 2 0 FSR Analog input voltage VAIN AVSS AVREF V Notes 1 Excludes quantization error 1 2 LSB 2 This value...

Page 608: ...um time to rise to 1 8 V VDD MIN releasing RESET input VDD 1 8 V tPUP2 POCMODE option byte 0 when RESET input is used 1 9 ms Supply Voltage Rise Time Timing When RESET pin input is not used When RESET pin input is used Supply voltage VDD Time 1 8 V tPUP1 Supply voltage VDD Time 1 8 V tPUP2 VPOC RESET pin 2 7 V POC Circuit Characteristics TA 40 to 85 C VSS EVSS 0 V Parameter Symbol Conditions MIN T...

Page 609: ...VLVI10 2 60 2 70 2 80 V VLVI11 2 45 2 55 2 65 V VLVI12 2 29 2 39 2 49 V VLVI13 2 14 2 24 2 34 V VLVI14 1 98 2 08 2 18 V Supply voltage level VLVI15 1 83 1 93 2 03 V Detection voltage External input pin Note 1 EXLVI EXLVI VDD 1 8 V VDD 5 5 V 1 21 V Minimum pulse width tLW 200 µs Operation stabilization wait time Note 2 tLWAIT 10 µs Notes 1 The EXLVI P120 INTP0 pin is used 2 Time required from setti...

Page 610: ...mbol Conditions MIN TYP MAX Unit Data retention supply voltage VDDDR 1 44 Note 5 5 V Note The value depends on the POC detection voltage When the voltage drops the data is retained until a POC reset is effected but data is not retained when a POC reset is effected VDD STOP instruction execution Standby release signal interrupt request STOP mode Data retention mode VDDDR Operation mode ...

Page 611: ...r erase 1 rewrite Note 2 100 Times Notes 1 The prewrite time before erasure and the erase verify time writeback time are not included 2 When a product is first written after shipment erase write and write only are both taken as one rewrite Remark fXP Main system clock oscillation frequency 2 Serial write operation characteristics Parameter Symbol Conditions MIN TYP MAX Unit Time from RESET to FLMD...

Page 612: ...E A A1 A2 A3 10 00 0 20 10 00 0 20 12 00 0 20 12 00 0 20 1 60 MAX 0 10 0 05 1 40 0 05 0 25 c θ e x y ZD ZE 0 50 0 08 0 08 1 25 1 25 L Lp L1 0 50 0 60 0 15 1 00 0 20 P64GB 50 UEU 1 3 5 3 NOTE Each lead centerline is located within 0 08 mm of its true position at maximum material condition detail of lead end 0 22 0 05 b 16 32 1 64 17 33 49 48 64 PIN PLASTIC LQFP FINE PITCH 10x10 ...

Page 613: ...HE A A1 A2 A3 14 00 0 20 14 00 0 20 17 20 0 20 17 20 0 20 1 70 MAX 0 125 0 075 1 40 0 05 0 25 c θ e x y ZD ZE 0 80 0 20 0 10 1 00 1 00 L Lp L1 0 80 0 886 0 15 1 60 0 20 P64GC 80 UBS 3 5 3 NOTE Each lead centerline is located within 0 20 mm of its true position at maximum material condition detail of lead end 0 37 0 08 0 07 b 16 32 64 17 33 49 48 1 64 PIN PLASTIC LQFP 14x14 ...

Page 614: ...detail of lead end θ L c Lp HD HE ZD ZE L1 A1 A2 A D E 16 32 1 64 17 33 49 48 S y e S x b M A3 S 0 145 0 055 0 045 UNIT mm ITEM DIMENSIONS D E HD HE A A1 A2 A3 12 00 0 20 12 00 0 20 14 00 0 20 14 00 0 20 1 60 MAX 0 10 0 05 1 40 0 05 0 25 c θ e x y ZD ZE 0 65 0 13 0 10 1 125 1 125 L Lp L1 0 50 0 60 0 15 1 00 0 20 P64GK 65 UET 1 3 5 3 0 32 0 08 0 07 b 64 PIN PLASTIC LQFP 12x12 ...

Page 615: ... 7 00 0 20 7 00 0 20 9 00 0 20 9 00 0 20 1 20 MAX 0 10 0 05 1 00 0 05 0 25 c θ e x y ZD ZE 0 40 0 07 0 08 0 50 0 50 L Lp L1 0 50 0 60 0 15 1 00 0 20 P64GA 40 9EV 1 3 5 3 NOTE Each lead centerline is located within 0 07 mm of its true position at maximum material condition 0 18 0 05 b 16 32 1 64 17 33 49 48 θ L c Lp L1 A3 detail of lead end 64 PIN PLASTIC TQFP FINE PITCH 7x7 ...

Page 616: ...RT y S x A B M e φ 60x b φ b φ 0 34 0 05 0 55 0 70 0 05 0 55 0 05 0 70 0 05 0 55 0 05 0 75 0 75 0 55 0 55 R0 17 0 05 R0 17 0 05 R0 12 0 05 R0 12 0 05 R0 275 0 05 R0 35 0 05 0 75 0 55 0 05 0 70 0 05 0 55 0 75 0 55 0 05 0 70 0 05 φ S w B ZD ZE INDEX MARK B C D A S w A D E 3 90 3 90 DETAIL OF D PART DETAIL OF E PART E 1 2 H G F E D C B A 3 4 5 6 7 8 Land pad Aperture of solder resist P64FC 50 AA1 1 6...

Page 617: ...cted illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware When accessing the peripheral hardware that may cause a conflict therefore the CPU repeatedly executes processing until the correct data is passed As a result the CPU does not start the next instruction processing but waits If this happens the number of execution clocks of an instruction inc...

Page 618: ...verter The above number of clocks is when the same source clock is selected for fCPU and fPRS The number of wait clocks can be calculated by the following expression and under the following conditions Calculating number of wait clocks Number of wait clocks 1 fAD 2 1 fCPU 1 Fraction is truncated if the number of wait clocks 0 5 and rounded up if the number of wait clocks 0 5 fAD A D conversion cloc...

Page 619: ...hows the development tool configuration Support for PC98 NX series Unless otherwise specified products supported by IBM PC ATTM compatibles are compatible with PC98 NX series computers When using PC98 NX series computers refer to the explanation for IBM PC AT compatibles WindowsTM Unless otherwise specified Windows means the following OSs Windows 98 Windows NTTM Windows 2000 Windows XP ...

Page 620: ... Target system Flash programmer Flash memory write adapter Flash memory Software package Project manager Software package Flash memory write environment Control software Windows only Note 2 Power supply unit USB interface cable Notes 1 The C library source file is not included in the software package 2 The project manager PM is included in the assembler package The PM is only used for Windows 3 In...

Page 621: ...ip debug emulatorNote 3 Connection cable Target connector Target system Flash programmer Flash memory write adapter Flash memory Software package Project manager Software package Flash memory write environment Control software Windows only Note 2 Notes 1 The C library source file is not included in the software package 2 The project manager PM is included in the assembler package The PM is only us...

Page 622: ...age Part number µS RA78K0 This compiler converts programs written in C language into object codes executable with a microcontroller This compiler should be used in combination with an assembler package and device file both sold separately Precaution when using CC78K0 in PC environment This C compiler package is a DOS based application It can also be used in Windows however by using the Project Man...

Page 623: ...ger Caution The project manager is included in the assembler package RA78K0 It can only be used in Windows A 4 Flash Memory Writing Tools FlashPro4 part number FL PR4 PG FP4 Flash memory programmer Flash memory programmer dedicated to microcontrollers with on chip flash memory FlashPro4 part number PG FPL3 Simple flash memory programmer Simple flash memory programmer dedicated to microcontrollers ...

Page 624: ...the height between the target system and in circuit emulator QB 64GB YS 01T 64 pin plastic LQFP GB UEU type QB 64GC YS 01T 64 pin plastic LQFP GC UBS type QB 64GK YS 01T 64 pin plastic LQFP GK UET type QB 64GA YS 01T 64 pin plastic TQFP GA 9EV type QB 64GB YQ 01T QB 64GC YQ 01T QB 64GK YQ 01T QB 64GA YQ 01T YQ connector This YQ connector is used to connect the target connector and exchange adapter...

Page 625: ...trol software the integrated debugger ID78K0 QB is supplied A 6 Debugging Tools Software The SM for 78K0 KX2 is Windows based software It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine Use of the SM for 78K0 KX2 allows the execution of application logical testing and performance testing on an independent b...

Page 626: ... where there are component mounting height restrictions when the QB 78K0KX2 is used Figure B 1 For 64 Pin GB Package 15 10 5 13 375 10 15 10 5 17 375 10 Exchange adapter area Components up to 17 45 mm in height can be mounted Note Emulation probe tip area Components up to 24 45 mm in height can be mounted Note Note Height can be adjusted by using space adapters each adds 2 4 mm ...

Page 627: ...ation probe tip area Components up to 24 45 mm in height can be mountedNote Note Height can be adjusted by using space adapters each adds 2 4 mm Figure B 3 For 64 Pin GK Package 15 10 5 13 375 10 15 10 5 17 375 10 Exchange adapter area Components up to 17 45 mm in height can be mounted Note Emulation probe tip area Components up to 24 45 mm in height can be mountedNote Note Height can be adjusted ...

Page 628: ...compare control register 00 CRC00 179 Capture compare control register 01 CRC01 179 Clock operation mode select register OSCCTL 137 Clock output selection register CKS 301 Clock selection register 6 CKSR6 358 E 8 bit A D conversion result register ADCRH 311 8 bit timer compare register 50 CR50 247 8 bit timer compare register 51 CR51 247 8 bit timer counter 50 TM50 247 8 bit timer counter 51 TM51 ...

Page 629: ...register 1L IF1L 493 K Key return mode register KRM 507 L Low voltage detection level selection register LVIS 538 Low voltage detection register LVIM 539 M Main clock mode register MCM 143 Main OSC control register MOC 142 Memory bank select register BANK 90 Multiplication division data register A0 MDA0H MDA0L 479 Multiplication division data register B0 MDB0 481 Multiplier divider control registe...

Page 630: ...28 Pull up resistor option register 4 PU4 128 Pull up resistor option register 5 PU5 128 Pull up resistor option register 6 PU6 128 Pull up resistor option register 7 PU7 128 Pull up resistor option register 12 PU12 128 Pull up resistor option register 14 PU14 128 R Receive buffer register 0 RXB0 329 Receive buffer register 6 RXB6 353 Remainder data register 0 SDR0 479 Reset control flag register ...

Page 631: ... control register 01 TOC01 181 Slave address register 0 SVA0 409 T Timer clock selection register 50 TCL50 248 Timer clock selection register 51 TCL51 248 10 bit A D conversion result register ADCR 310 Transmit buffer register 10 SOTB10 386 Transmit buffer register 11 SOTB11 386 Transmit buffer register 6 TXB6 353 Transmit shift register 0 TXS0 329 W Watch timer operation mode register WTM 289 Wat...

Page 632: ...rol register 0 333 BRGC6 Baud rate generator control register 6 359 C CKS Clock output selection register 301 CKSR6 Clock selection register 6 358 CMP00 8 bit timer H compare register 00 265 CMP01 8 bit timer H compare register 01 265 CMP10 8 bit timer H compare register 10 265 CMP11 8 bit timer H compare register 11 265 CR000 16 bit timer capture compare register 000 173 CR001 16 bit timer captur...

Page 633: ...e detection register 538 LVIS Low voltage detection level selection register 539 M MCM Main clock mode register 143 MDA0H Multiplication division data register A0 479 MDA0L Multiplication division data register A0 479 MDB0 Multiplication division data register B0 480 MK0H Interrupt mask flag register 0H 495 MK0L Interrupt mask flag register 0L 495 MK1H Interrupt mask flag register 1H 495 MK1L Inte...

Page 634: ...r 00 184 PRM01 Prescaler mode register 01 184 PU0 Pull up resistor option register 0 128 PU1 Pull up resistor option register 1 128 PU3 Pull up resistor option register 3 128 PU4 Pull up resistor option register 4 128 PU5 Pull up resistor option register 5 128 PU7 Pull up resistor option register 7 128 PU12 Pull up resistor option register 12 128 PU14 Pull up resistor option register 14 128 R RCM ...

Page 635: ...trol register 50 250 TMC51 8 bit timer mode control register 51 250 TMCYC1 8 bit timer H carrier control register 1 270 TMHMD0 8 bit timer H mode register 0 266 TMHMD1 8 bit timer H mode register 1 266 TOC00 16 bit timer output control register 00 181 TOC01 16 bit timer output control register 01 181 TXB6 Transmit buffer register 6 353 TXS0 Transmit shift register 0 329 W WDTE Watchdog timer enabl...

Page 636: ...p 32 to 35 Addition of Note to 2 1 Pin Function List p 41 Modification of descriptions in 2 2 12 AVREF p 41 Addition of Caution to 2 2 15 REGC p 42 Modification of descriptions in 2 2 16 VDD and EVDD and 2 2 17 VSS and EVSS p 44 Modification of recommended connection of unused pins of P121 X1 P122 X2 EXCLK P123 XT1 and P124 XT2 EXCLKS in Table 2 2 Pin I O Circuit Types CHAPTER 3 CPU ARCHITECTURE p...

Page 637: ... 5 3 Registers Controlling Port Function pp 132 133 Addition of Remark 2 and Notes 1 and 2 to Table 5 5 Settings of Port Mode Register and Output Latch When Using Alternate Function 2 2 CHAPTER 6 CLOCK GENERATOR p 134 Modification of oscillation frequency range X1 oscillator and external main system clock in 6 1 1 Main system clock p 135 Addition to description in 6 1 3 Internal low speed oscillat...

Page 638: ...MP0n and 2 8 bit time r H compare register 1n CMP1n in 9 2 p 269 Modification of Figure 9 6 Format of 8 Bit Timer H Mode Register 1 TMHMD1 p 279 Modification of Figure 9 12 e Operation by changing CMP1n CMP1n 02H 03H CMP0n A5H p 280 Modification of description in 9 4 3 Carrier generator operation 8 bit timer H1 only p 281 Addition of 3 to Figure 9 13 Transfer Timing p 282 Addition of 8 to Setting ...

Page 639: ...sfer rate and Cautions 4 and 5 to 15 1 2 Asynchronous serial interface UART mode p 348 Modification of Figure 15 1 LIN Transmission Operation p 349 Modification of Figure 15 2 LIN Reception Operation p 353 Addition of Caution 3 to 15 2 3 Transmit buffer register 6 TXB6 p 355 Addition of Cautions 4 and 5 to Figure 15 5 Format of Asynchronous Serial Interface Operation Mode Register 6 ASIM6 p 356 Mo...

Page 640: ...to 17 5 4 Acknowledge ACK p 432 Addition of 17 5 7 Canceling wait p 437 Modification of Table 17 6 Wait Periods and Figure 17 20 Communication Reservation Timing p 440 Modification of Table 17 7 Wait Periods pp 440 441 Addition of 4 to 6 to 17 5 15 Other cautions pp 442 443 Modification of 17 5 16 1 Master operation single master system and 2 Master operation multi master system pp 447 448 Modific...

Page 641: ...of Figure 21 5 Operation Timing When STOP Mode Is Released p 520 Modification of Figure 21 7 STOP Mode Release by Reset CHAPTER 22 RESET FUNCTION p 523 Modification of Figure 22 2 Timing of Reset by RESET Input p 523 Modification of Figure 22 3 Timing of Reset Due to Watchdog Timer Overflow p 524 Modification of Figure 22 4 Timing of Reset in STOP Mode by RESET Input p 525 Addition of clock output...

Page 642: ...RT UART6 Mode pp 564 565 Modification of transfer rate in 1 CSI10 and 2 UART6 in 26 5 p 570 Modification of transfer rate in Speed column of Table 26 7 Communication Modes p 572 Addition of 26 8 Security Settings p 576 Modification of 26 9 1 Boot swap function p 577 Modification of Figure 26 18 Boot Swap Function CHAPTER 27 ON CHIP DEBUG FUNCTION µPD78F0537D ONLY p 578 Revision of chapter CHAPTER ...

Page 643: ...aution in 2 One shot pulse output with external trigger Modification of a One shot pulse output by software and b One shot pulse output with external trigger of 5 Re triggering one shot pulse in 6 5 Cautions for 16 Bit Timer Event Counters 00 and 01 CHAPTER 6 16 BIT TIMER EVENT COUNTERS 00 AND 01 Modification of Caution in 6 Asynchronous serial interface control register 6 ASICL6 of 14 3 Registers...

Page 644: ...tal revision of CHAPTER 26 ON CHIP DEBUG FUNCTION µPD78F0537D ONLY CHAPTER 26 ON CHIP DEBUG FUNCTION µPD78F0537D ONLY Total revision of CHAPTER 28 ELECTRICAL SPECIFICATIONS TARGET CHAPTER 28 ELECTRICAL SPECIFICATIONS TARGET 2nd edition Total revision of APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS ...

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