CHAPTER 21 STANDBY FUNCTION
Preliminary User’s Manual U17260EJ3V1UD
513
Table 21-1. Operating Statuses in HALT Mode (2/2)
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
HALT Mode Setting
Item
When CPU Is Operating on XT1 Clock (f
XT
)
When CPU Is Operating on External
Subsystem Clock (f
EXCLKS
)
System clock
Clock supply to the CPU is stopped
f
RH
f
X
Status before HALT mode was set is retained
Main system clock
f
EXCLK
Operates or stops by external clock input
f
XT
Operation continues (cannot be stopped)
Status before HALT mode was set is retained
Subsystem clock
f
EXCLKS
Operates or stops by external clock input
Operation continues (cannot be stopped)
f
RL
Status before HALT mode was set is retained
CPU Operation
stopped
Flash memory
Operation stopped
RAM
Status before HALT mode was set is retained
Port (latch)
Status before HALT mode was set is retained
00
Note1
16-bit timer/event
counter
01
Note1. 2
50
Note1
8-bit timer/event
counter
51
Note1
H0
8-bit timer
H1
Watch timer
Operable
Watchdog timer
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Clock output
Operable
Buzzer output
A/D converter
Operable. However, operation disabled when peripheral hardware clock (f
PRS
) is stopped.
UART0
UART6
CSI10
Note1
CSI11
Note1, 2
Serial interface
IIC0
Note1
Multiplier/divider
Note2
Power-on-clear function
Low-voltage detection function
External interrupt
Operable
Notes 1.
When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been
stopped, do not start operation of these functions on the external clock input from peripheral hardware pins.
2.
µ
PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only.
Remark
f
RH
:
Internal high-speed oscillation clock
f
X
: X1
clock
f
EXCLK
:
External main system clock
f
XT
: XT1
clock
f
EXCLKS
: External subsystem clock
f
RL
:
Internal low-speed oscillation clock
