CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET)
Preliminary User’s Manual U17260EJ3V1UD
601
AC Characteristics
(1) Basic
operation
(T
A
=
−
40 to +85
°
C, 1.8 V
≤
V
DD
= EV
DD
≤
5.5 V, AV
REF
≤
V
DD
, V
SS
= EV
SS
= AV
SS
= 0 V)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V
≤
V
DD
≤
5.5 V
0.1
32
µ
s
2.7 V
≤
V
DD
< 4.0 V
0.2
32
µ
s
Main system clock (f
XP
)
operation
1.8 V
≤
V
DD
< 2.7 V
0.4
Note 1
32
µ
s
Instruction cycle (minimum
instruction execution time)
T
CY
Subsystem clock (f
SUB
) operation
114
122
125
µ
s
4.0 V
≤
V
DD
≤
5.5 V
1.0
20.0
MHz
2.7 V
≤
V
DD
< 4.0 V
1.0
10.0
MHz
External main system clock
frequency
f
EXCLK
1.8 V
≤
V
DD
< 2.7 V
1.0
5.0
MHz
External main system clock input
high-level width, low-level width
t
EXCLKH
,
t
EXCLKL
(1/f
EXCLK
×
1/2)
−
1
ns
External subsystem clock
frequency
f
EXCLKS
32 32.768 35 kHz
External subsystem clock input
high-level width, low-level width
t
EXCLKSH
,
t
EXCLKSL
(1/f
EXCLKS
×
1/2)
−
5
ns
4.0 V
≤
V
DD
≤
5.5 V
2/f
sam
+
0.1
Note 3
µ
s
TI000, TI010, TI001
Note 2
, TI011
Note 2
input high-level width, low-level
width
t
TIH0
,
t
TIL0
2.7 V
≤
V
DD
< 4.0 V
2/f
sam
+
0.2
Note 3
µ
s
4.0 V
≤
V
DD
≤
5.5 V
10
MHz
2.7 V
≤
V
DD
< 4.0 V
10
MHz
TI50, TI51 input frequency
f
TI5
1.8 V
≤
V
DD
< 2.7 V
5
MHz
4.0 V
≤
V
DD
≤
5.5 V
50
ns
2.7 V
≤
V
DD
< 4.0 V
50
ns
TI50, TI51 input high-level width,
low-level width
t
TIH5
,
t
TIL5
1.8 V
≤
V
DD
< 2.7 V
100
ns
Interrupt input high-level width,
low-level width
t
INTH
,
t
INTL
1
µ
s
Key interrupt input low-level width t
KR
250 ns
RESET low-level width
t
RSL
10
µ
s
Notes 1.
0.38
µ
s when operating with the 8 MHz internal oscillator.
2.
µ
PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D only.
3.
Selection of f
sam
= f
PRS
, f
PRS
/4, f
PRS
/256, or f
PRS
, f
PRS
/16, f
PRS
/64 is possible using bits 0 and 1 (PRM000,
PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that
when selecting the TI000 or TI001 valid edge as the count clock, f
sam
= f
PRS.
