CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U17260EJ3V1UD
51
Figure 3-4. Memory Map (
µ
PD78F0534)
Internal expansion RAM
1024 x 8 bits
RAM spcae in
which instruction
can be fetched
Program RAM area
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
49152 x 8 bits
Program
memory space
Data memory
space
Vector table area
64 x 8 bits
CALLT table area
64 x 8 bits
Program area
1915 x 8 bits
Option byte area
Note1
5 x 8 bits
CALLF entry area
2048 x 8 bits
Program area
Program area
Option byte area
Note1
5 x 8 bits
Boot cluster 0
Note2
Boost cluster 1
Reserved
F F F F H
F F 0 0 H
F E F F H
F E E 0 H
F E D F H
F B 0 0 H
F A F F H
C 0 0 0 H
B F F F H
0 0 0 0 H
0 0 4 0 H
0 0 3 F H
0 0 0 0 H
0 0 8 0 H
0 0 7 F H
0 8 0 0 H
0 7 F F H
1 0 0 0 H
0 F F F H
1 0 8 5 H
1 0 8 4 H
1 0 8 0 H
1 0 7 F H
0 0 8 5 H
0 0 8 4 H
B F F F H
1 F F F H
F 8 0 0 H
F 7 F F H
F 4 0 0 H
F 3 F F H
Notes 1.
When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used:
Set the option bytes to 0080H to 0084H and 1080H to 1084H.
2.
Writing boot cluster 0 can be prohibited depending on the setting of security (see
26.8 Security
Setting
).
