CHAPTER 17 SERIAL INTERFACE IIC0
Preliminary User’s Manual U17260EJ3V1UD
418
Figure 17-6. Format of IIC Status Register 0 (IICS0) (2/3)
COI0
Detection of matching addresses
0
Addresses do not match.
1 Addresses
match.
Condition for clearing (COI0 = 0)
Condition for setting (COI0 = 1)
•
When a start condition is detected
•
When a stop condition is detected
•
Cleared by LREL0 = 1 (exit from communications)
•
When IICE0 changes from 1 to 0 (operation stop)
•
Reset
•
When the received address matches the local address
(slave address register 0 (SVA0))
(set at the rising edge of the eighth clock).
TRC0
Detection of transmit/receive status
0
Receive status (other than transmit status). The SDA0 line is set for high impedance.
1
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at the
falling edge of the first byte’s ninth clock).
Condition for clearing (TRC0 = 0)
Condition for setting (TRC0 = 1)
<Both master and slave>
•
When a stop condition is detected
•
Cleared by LREL0 = 1 (exit from communications)
•
When IICE0 changes from 1 to 0 (operation stop)
•
Cleared by WREL0 = 1
Note
(wait cancel)
•
When ALD0 changes from 0 to 1 (arbitration loss)
•
Reset
<Master>
•
When “1” is output to the first byte’s LSB (transfer
direction specification bit)
<Slave>
•
When a start condition is detected
•
When “0” is input to the first byte’s LSB (transfer direction
specification bit)
<When not used for communication>
<Master>
•
When a start condition is generated
•
When “0” is output to the first byte’s LSB (transfer
direction specification bit)
<Slave>
•
When “1” is input to the first byte’s LSB (transfer
direction specification bit)
Note
If the wait status is canceled by setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1 at the ninth
clock when bit 3 (TRC0) of IIC status register 0 (IICS0) is 1, TRC0 is cleared, and the SDA0 line goes
into a high-impedance state.
Remark
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0: Bit 7 of IIC control register 0 (IICC0)
