Chapter 4
Register Descriptions
© National Instruments Corporation
4-25
VME-MXI-2 User Manual
VME-MXI-2 Status Register (VMSR)
VMEbus A16 Offset:
20 (hex)
Attributes:
Read Only
16, 8-bit accessible
15
14
13
12
11
10
9
8
0
CMODE
1
POSTERR
MXSCTO
INTLCK
DSYSFAIL
FAIR
7
6
5
4
3
2
1
0
MXISC
0
0
0
SCFG
MBERR
0
PARERR
This VME-MXI-2-specific register provides status bits for various operations.
Bit
Mnemonic
Description
15
0
Reserved
This bit is reserved and returns 0 when read.
14
CMODE
Comparison Mode Status
This bit reflects the state of the CMODE bit in
the VME-MXI-2 Control register (VMCR).
13
1
Reserved
This bit is reserved and returns 1 when read.
12
POSTERR
Write Post Error Status
This bit returns 1 when a write-posted cycle
results in an error. This is actually two bits; one
can be read from the MXIbus, the other can be
read from the VMEbus. When a VMEbus master
reads this bit as a 1, a VMEbus data cycle that
mapped to the MXIbus and was posted results in
an error. When a MXIbus master reads this bit as
a 1, a MXIbus data cycle that mapped to the
VMEbus and was posted results in an error.
Each bit clears when read and on hard and soft
resets. Write posting can be enabled using the
VXIplug&play soft front panel for the
VME-MXI-2.
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